diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
| commit | 09b2430e95df4f744a000bac34100eeb9ebcb878 (patch) | |
| tree | 1db0ab99b4186f15335a866fd7239ba51755b7d9 /tests | |
| parent | f205d83359dfb3c4f75159f83081b5e356c3c4b4 (diff) | |
| download | gem5-09b2430e95df4f744a000bac34100eeb9ebcb878.tar.xz | |
stats: update patches for branch predictor and fetch updates.
Diffstat (limited to 'tests')
40 files changed, 8943 insertions, 8901 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 366d8d2c3..c2660d718 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -707,6 +707,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 28e40a40b..b7a2e0ce5 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -21,14 +22,13 @@ warn: 2291164927000: Instruction results do not match! (Values may not actually warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: 2483733168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2497502762000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2498707540000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2497502713500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2498707539500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 warn: 2519748168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2520262198000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2525920507000: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0x200da -warn: 2525942893500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2526450197000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2527009496000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2527010611500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2527557612000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 +warn: 2520262039500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2525942762500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2526449392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2527008451000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2527009567500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2527556775500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index e0cb5000c..444ce680b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:38:19 -gem5 started Feb 13 2013 20:59:50 -gem5 executing on u200540-lin +gem5 compiled Feb 25 2013 18:24:48 +gem5 started Feb 25 2013 22:59:32 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2533147650000 because m5_exit instruction encountered +Exiting @ tick 2533144795000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index b54fd326b..6f639a911 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,128 +1,128 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.533144 # Number of seconds simulated -sim_ticks 2533143504000 # Number of ticks simulated -final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2533143973500 # Number of ticks simulated +final_tick 2533143973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65433 # Simulator instruction rate (inst/s) -host_op_rate 84194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2748425484 # Simulator tick rate (ticks/s) -host_mem_usage 408856 # Number of bytes of host memory used -host_seconds 921.67 # Real time elapsed on the host +host_inst_rate 55009 # Simulator instruction rate (inst/s) +host_op_rate 70781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2310577470 # Simulator tick rate (ticks/s) +host_mem_usage 405260 # Number of bytes of host memory used +host_seconds 1096.33 # Real time elapsed on the host sim_insts 60307579 # Number of instructions simulated sim_ops 77599125 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory -system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory +system.physmem.bytes_read::total 129430480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798408 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096817 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59099 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813117 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1061 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493139 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2683783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1061 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096820 # Total number of read requests seen -system.physmem.writeReqs 813121 # Total number of write requests seen -system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966196480 # Total number of bytes read from memory -system.physmem.bytesWritten 52039744 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 314474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096817 # Total number of read requests seen +system.physmem.writeReqs 813117 # Total number of write requests seen +system.physmem.cpureqs 218351 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966196288 # Total number of bytes read from memory +system.physmem.bytesWritten 52039488 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129430480 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798408 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943948 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943206 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943088 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 943622 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50900 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533142364000 # Total gap between requests +system.physmem.totGap 2533142848500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154576 # Categorize read packet sizes +system.physmem.readPktSize::6 154573 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59103 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59099 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108698 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16712 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10857 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -139,8 +139,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2634 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see @@ -160,8 +160,8 @@ system.physmem.wrQLenPdf::17 35353 # Wh system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::28 32584 # Wh system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests -system.physmem.totBusLat 75482965000 # Total cycles spent in databus access -system.physmem.totBankLat 16912788750 # Total cycles spent in bank access -system.physmem.avgQLat 26048.65 # Average queueing delay per request -system.physmem.avgBankLat 1120.31 # Average bank access latency per request +system.physmem.totQLat 393251142750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485645877750 # Sum of mem lat for all requests +system.physmem.totBusLat 75482950000 # Total cycles spent in databus access +system.physmem.totBankLat 16911785000 # Total cycles spent in bank access +system.physmem.avgQLat 26049.00 # Average queueing delay per request +system.physmem.avgBankLat 1120.24 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32168.96 # Average memory access latency +system.physmem.avgMemAccLat 32169.24 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -187,11 +187,11 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time system.physmem.avgWrQLen 9.55 # Average write queue length over time -system.physmem.readRowHits 15020273 # Number of row buffer hits during reads -system.physmem.writeRowHits 793117 # Number of row buffer hits during writes +system.physmem.readRowHits 15020272 # Number of row buffer hits during reads +system.physmem.writeRowHits 793090 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159217.58 # Average gap between requests +system.physmem.avgGap 159217.68 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -210,14 +210,14 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14678084 # Number of BP lookups -system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits +system.cpu.branchPred.lookups 14675749 # Number of BP lookups +system.cpu.branchPred.condPredicted 11761615 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705306 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9809113 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7951342 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 81.060765 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398937 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses @@ -266,27 +266,27 @@ system.cpu.checker.numWorkItemsStarted 0 # nu system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51401633 # DTB read hits -system.cpu.dtb.read_misses 64365 # DTB read misses -system.cpu.dtb.write_hits 11702282 # DTB write hits -system.cpu.dtb.write_misses 15903 # DTB write misses +system.cpu.dtb.read_hits 51399217 # DTB read hits +system.cpu.dtb.read_misses 64403 # DTB read misses +system.cpu.dtb.write_hits 11701345 # DTB write hits +system.cpu.dtb.write_misses 15902 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6544 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6540 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2566 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 409 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51465998 # DTB read accesses -system.cpu.dtb.write_accesses 11718185 # DTB write accesses +system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51463620 # DTB read accesses +system.cpu.dtb.write_accesses 11717247 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63103915 # DTB hits -system.cpu.dtb.misses 80268 # DTB misses -system.cpu.dtb.accesses 63184183 # DTB accesses -system.cpu.itb.inst_hits 12333169 # ITB inst hits -system.cpu.itb.inst_misses 11311 # ITB inst misses +system.cpu.dtb.hits 63100562 # DTB hits +system.cpu.dtb.misses 80305 # DTB misses +system.cpu.dtb.accesses 63180867 # DTB accesses +system.cpu.itb.inst_hits 12332677 # ITB inst hits +system.cpu.itb.inst_misses 11271 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -295,113 +295,113 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4950 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4946 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2981 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12344480 # ITB inst accesses -system.cpu.itb.hits 12333169 # DTB hits -system.cpu.itb.misses 11311 # DTB misses -system.cpu.itb.accesses 12344480 # DTB accesses -system.cpu.numCycles 471839315 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12343948 # ITB inst accesses +system.cpu.itb.hits 12332677 # DTB hits +system.cpu.itb.misses 11271 # DTB misses +system.cpu.itb.accesses 12343948 # DTB accesses +system.cpu.numCycles 471840254 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30570540 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96039987 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14675749 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9350279 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21160212 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5300332 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123049 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95587623 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87979 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195754 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12329197 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5353 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151365911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785063 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150272 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130221030 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303083 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712964 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496255 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2215475 1.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108052 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2757455 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745629 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8805968 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 151365911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203543 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32532272 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95215917 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19186051 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962874 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3468797 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957839 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171569 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112632707 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 566700 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3468797 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34474935 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36706470 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52522148 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18150584 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6042977 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106114460 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20538 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4062916 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 612 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110534596 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485505463 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485414558 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90905 # Number of floating rename lookups system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 32144721 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830610 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737120 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12168217 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20326621 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13518825 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978093 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2487494 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97939378 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983579 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124329035 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167924 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21751378 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57069924 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501194 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151365911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821381 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534880 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107121434 70.77% 70.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13552589 8.95% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7069165 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5942277 3.93% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12602111 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2786608 1.84% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1699306 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465403 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127018 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151365911 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60927 0.69% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available @@ -430,13 +430,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365559 94.64% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412870 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58631029 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93272 0.08% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued @@ -452,7 +452,7 @@ system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued @@ -464,84 +464,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52917261 42.56% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12321634 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued -system.cpu.iq.rate 0.263513 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested +system.cpu.iq.FU_type_0::total 124329035 # Type of FU issued +system.cpu.iq.rate 0.263498 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839358 # FU busy when requested system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 409088132 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121690697 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85968255 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23084 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12548 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132792486 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12241 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623354 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 4672096 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6462 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1786745 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107738 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893837 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3469224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27949054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100148718 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 201036 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20329502 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13519419 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411238 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112362 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3468797 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27950970 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433267 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100144689 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200366 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20326621 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13518825 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410950 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112625 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3575 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269150 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619996 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121555637 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52088672 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2779958 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 350763 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269062 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619825 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121548947 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52086338 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2780088 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220929 # number of nop insts executed -system.cpu.iew.exec_refs 64302587 # number of memory reference insts executed -system.cpu.iew.exec_branches 11562998 # Number of branches executed -system.cpu.iew.exec_stores 12213915 # Number of stores executed -system.cpu.iew.exec_rate 0.257621 # Inst execution rate -system.cpu.iew.wb_sent 120394624 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85985291 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47225460 # num instructions producing a value -system.cpu.iew.wb_consumers 88174567 # num instructions consuming a value +system.cpu.iew.exec_nop 221732 # number of nop insts executed +system.cpu.iew.exec_refs 64299340 # number of memory reference insts executed +system.cpu.iew.exec_branches 11561583 # Number of branches executed +system.cpu.iew.exec_stores 12213002 # Number of stores executed +system.cpu.iew.exec_rate 0.257606 # Inst execution rate +system.cpu.iew.wb_sent 120388158 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85978549 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47221894 # num instructions producing a value +system.cpu.iew.wb_consumers 88170402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182220 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535575 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21490031 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 21486542 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147900474 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.515007 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 536246 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147897114 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525700 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515001 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13317188 9.00% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2119368 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1600636 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889854 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120445936 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13320013 9.01% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3904517 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2120442 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1947230 1.32% 95.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 967442 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598856 1.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701557 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2891121 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147900474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 147897114 # Number of insts commited each cycle system.cpu.commit.committedInsts 60457960 # Number of instructions committed system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -552,261 +552,261 @@ system.cpu.commit.branches 9961316 # Nu system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. system.cpu.commit.function_calls 991257 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889854 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2891121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242401590 # The number of ROB reads -system.cpu.rob.rob_writes 202045449 # The number of ROB writes -system.cpu.timesIdled 1769758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320469617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 242393474 # The number of ROB reads +system.cpu.rob.rob_writes 202038068 # The number of ROB writes +system.cpu.timesIdled 1769308 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320474343 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 60307579 # Number of Instructions Simulated system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated -system.cpu.cpi 7.823881 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823881 # CPI: Total CPI of All Threads +system.cpu.cpi 7.823896 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823896 # CPI: Total CPI of All Threads system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550352195 # number of integer regfile reads -system.cpu.int_regfile_writes 88467764 # number of integer regfile writes -system.cpu.fp_regfile_reads 8269 # number of floating regfile reads -system.cpu.fp_regfile_writes 2928 # number of floating regfile writes -system.cpu.misc_regfile_reads 30128398 # number of misc regfile reads +system.cpu.int_regfile_reads 550318453 # number of integer regfile reads +system.cpu.int_regfile_writes 88458214 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 30125052 # number of misc regfile reads system.cpu.misc_regfile_writes 831890 # number of misc regfile writes -system.cpu.icache.replacements 979593 # number of replacements +system.cpu.icache.replacements 979629 # number of replacements system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use -system.cpu.icache.total_refs 11270072 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980105 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.498841 # Average number of references to valid blocks. +system.cpu.icache.total_refs 11269534 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980141 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.497870 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11270072 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11270072 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11270072 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11270072 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11270072 # number of overall hits -system.cpu.icache.overall_hits::total 11270072 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059286 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059286 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059286 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059286 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059286 # number of overall misses -system.cpu.icache.overall_misses::total 1059286 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13991116996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13991116996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13991116996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13991116996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13991116996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13991116996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12329358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12329358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12329358 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12329358 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12329358 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12329358 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085916 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085916 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085916 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085916 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085916 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085916 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13208.063730 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13208.063730 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13208.063730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13208.063730 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4509 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11269534 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11269534 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11269534 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11269534 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11269534 # number of overall hits +system.cpu.icache.overall_hits::total 11269534 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059538 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059538 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059538 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059538 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059538 # number of overall misses +system.cpu.icache.overall_misses::total 1059538 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993400496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13993400496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13993400496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13993400496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13993400496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13993400496 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12329072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12329072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12329072 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12329072 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12329072 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12329072 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085938 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085938 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085938 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085938 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085938 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085938 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.077515 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13207.077515 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13207.077515 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13207.077515 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4855 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 305 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.639610 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.918033 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79147 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79147 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79147 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79147 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79147 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79147 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980139 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980139 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980139 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980139 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980139 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980139 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11380145996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11380145996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11380145996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11380145996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11380145996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11380145996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79361 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79361 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79361 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79361 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79361 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79361 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980177 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980177 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980177 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980177 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980177 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980177 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11379164996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11379164996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11379164996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11379164996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11379164996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11379164996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079496 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079496 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079496 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11610.747043 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11610.747043 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11610.747043 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11610.747043 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11610.747043 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11610.747043 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079501 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079501 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079501 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11609.296072 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11609.296072 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11609.296072 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11609.296072 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11609.296072 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11609.296072 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64347 # number of replacements -system.cpu.l2cache.tagsinuse 51347.741462 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1885858 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129741 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.535559 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498197510500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36929.511487 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.548284 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 64344 # number of replacements +system.cpu.l2cache.tagsinuse 51347.743422 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1885451 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129735 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.533094 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498197459500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36929.519444 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.551079 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8159.884348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6231.796994 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8159.886035 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6231.786516 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.563500 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000405 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.124510 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.095090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.783504 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52622 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10526 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966687 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387256 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1417091 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607840 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607840 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52475 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10450 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966729 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387264 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1416918 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607832 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607832 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112895 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112895 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52622 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10526 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 966687 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500151 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529986 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52622 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10526 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 966687 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500151 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529986 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 112902 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112902 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52475 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10450 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966729 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500166 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529820 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52475 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10450 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966729 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500166 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529820 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 42 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12342 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10709 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23094 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12340 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10707 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23091 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133191 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133191 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133192 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133192 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 42 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12342 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143900 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156285 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12340 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143899 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156283 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 42 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12342 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143900 # number of overall misses -system.cpu.l2cache.overall_misses::total 156285 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2975000 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 12340 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143899 # number of overall misses +system.cpu.l2cache.overall_misses::total 156283 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3043500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 697957500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 634176999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1335227499 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 522000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 522000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6733037500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6733037500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2975000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 696478000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 634908499 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1334547999 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 523500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 523500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6738135500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6738135500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3043500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 697957500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7367214499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8068264999 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2975000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 696478000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7373043999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8072683499 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3043500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 697957500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7367214499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8068264999 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52663 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10528 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979029 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397965 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440185 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607840 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607840 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 696478000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7373043999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8072683499 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52517 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10452 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 979069 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397971 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1440009 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607832 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607832 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246086 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246086 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52663 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10528 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979029 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686271 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52663 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10528 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979029 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686271 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000779 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012606 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026909 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246094 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246094 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52517 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10452 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 979069 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 644065 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1686103 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52517 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10452 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979069 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 644065 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1686103 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000800 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012604 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026904 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.016035 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986491 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986491 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985825 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985825 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541238 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541238 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000779 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012606 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223430 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092681 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000779 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012606 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223430 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092681 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72560.975610 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541224 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541224 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000800 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012604 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223423 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092689 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000800 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012604 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223423 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092689 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72464.285714 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56551.409820 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59219.067980 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57817.073655 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 178.705923 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 178.705923 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50551.745238 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50551.745238 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72560.975610 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56440.680713 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59298.449519 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57795.158243 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 179.219445 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 179.219445 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50589.641270 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50589.641270 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72464.285714 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56551.409820 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51196.765108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51625.331919 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72560.975610 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56440.680713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51237.631943 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51654.265013 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72464.285714 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56551.409820 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51196.765108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51625.331919 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56440.680713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51237.631943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51654.265013 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -815,8 +815,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59103 # number of writebacks -system.cpu.l2cache.writebacks::total 59103 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59099 # number of writebacks +system.cpu.l2cache.writebacks::total 59099 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits @@ -826,98 +826,98 @@ system.cpu.l2cache.demand_mshr_hits::total 74 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 42 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12330 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10647 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23020 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10645 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23017 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133191 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133191 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133192 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133192 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 42 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12330 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143838 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156211 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143837 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156209 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 42 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12330 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143838 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156211 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2463540 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143837 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156209 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2519791 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 543887277 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 499142740 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1045586808 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 542440021 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 499891739 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1044944802 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5073016629 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5073016629 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2463540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5078126850 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5078126850 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2519791 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 543887277 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5572159369 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6118603437 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2463540 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 542440021 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578018589 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6123071652 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2519791 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 543887277 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5572159369 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6118603437 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 542440021 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578018589 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6123071652 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079330 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002492267 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007571597 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903234989 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903234989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002548267 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007627597 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903237989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903237989 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079330 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905727256 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910806586 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026754 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905786256 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910865586 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026748 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015984 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986491 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986491 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985825 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985825 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541238 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541238 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092637 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092637 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541224 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541224 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092645 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092645 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44110.890268 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46881.068846 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45420.799652 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44000.650633 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46960.238516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45398.827041 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38088.283961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38088.283961 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38126.365322 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38126.365322 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -927,161 +927,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643539 # number of replacements +system.cpu.dcache.replacements 643553 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21509590 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644051 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.397340 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21507678 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644065 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.393645 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13756144 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13756144 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259539 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259539 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243175 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243175 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13754193 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13754193 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259605 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259605 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243146 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243146 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21015683 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21015683 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21015683 # number of overall hits -system.cpu.dcache.overall_hits::total 21015683 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737609 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737609 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962812 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962812 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13513 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13513 # number of LoadLockedReq misses +system.cpu.dcache.demand_hits::cpu.data 21013798 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21013798 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21013798 # number of overall hits +system.cpu.dcache.overall_hits::total 21013798 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737832 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737832 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962746 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962746 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13508 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700421 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700421 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700421 # number of overall misses -system.cpu.dcache.overall_misses::total 3700421 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9797923500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9797923500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104330736229 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104330736229 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180578000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180578000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3700578 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700578 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700578 # number of overall misses +system.cpu.dcache.overall_misses::total 3700578 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9800700500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9800700500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104414938731 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104414938731 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180553500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180553500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114128659729 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114128659729 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114128659729 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114128659729 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14493753 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14493753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 114215639231 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114215639231 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114215639231 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114215639231 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492025 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492025 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256688 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256688 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256654 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24716104 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24716104 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24716104 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24716104 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050892 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050892 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289837 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052644 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052644 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 24714376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714376 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714376 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714376 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050913 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289830 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289830 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052631 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052631 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149717 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149717 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149717 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149717 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.356765 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.356765 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35213.417601 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35213.417601 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13363.279805 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13363.279805 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.149734 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149734 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149734 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149734 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.105775 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.105775 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35242.622463 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35242.622463 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13366.412496 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.412496 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30842.074383 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30842.074383 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29695 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17222 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2648 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30864.270185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30864.270185 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29973 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17225 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2670 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.214124 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 68.341270 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.225843 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 68.353175 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607840 # number of writebacks -system.cpu.dcache.writebacks::total 607840 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351729 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351729 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713855 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713855 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1338 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1338 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065584 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065584 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065584 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385880 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385880 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248957 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248957 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks +system.cpu.dcache.writebacks::total 607832 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351946 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351946 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713780 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713780 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1332 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1332 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065726 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065726 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065726 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065726 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385886 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385886 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248966 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248966 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12176 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12176 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634837 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634837 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634837 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634837 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4811592500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4811592500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182885914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182885914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141167000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 634852 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634852 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634852 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634852 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4812474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4812474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8188067914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8188067914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141180000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141180000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12994478414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12994478414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12994478414 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12994478414 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395775000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395775000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742499011 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742499011 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138274011 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138274011 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024354 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024354 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047431 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13000541914 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13000541914 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13000541914 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13000541914 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395833000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395833000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742502511 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742502511 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138335511 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138335511 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047441 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047441 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025685 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025685 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12469.141961 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12469.141961 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32868.671755 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32868.671755 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.825462 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025688 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025688 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12471.232437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12471.232437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32888.297655 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32888.297655 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.940867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.940867 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1103,10 +1103,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610797601 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229610797601 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 2403b9510..053c6a286 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1077,6 +1077,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index e8e271d58..4ccac5e7b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index d8e2a14f0..8d856e1ed 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:38:19 -gem5 started Feb 13 2013 21:11:40 -gem5 executing on u200540-lin +gem5 compiled Feb 25 2013 18:24:48 +gem5 started Feb 25 2013 23:05:46 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1102937390000 because m5_exit instruction encountered +Exiting @ tick 1102934903000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 434326c81..5e12f3369 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102950 # Number of seconds simulated -sim_ticks 1102950399000 # Number of ticks simulated -final_tick 1102950399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102940 # Number of seconds simulated +sim_ticks 1102940172000 # Number of ticks simulated +final_tick 1102940172000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57810 # Simulator instruction rate (inst/s) -host_op_rate 74418 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1035290197 # Simulator tick rate (ticks/s) -host_mem_usage 414988 # Number of bytes of host memory used -host_seconds 1065.35 # Real time elapsed on the host -sim_insts 61588287 # Number of instructions simulated -sim_ops 79281553 # Number of ops (including micro ops) simulated +host_inst_rate 65652 # Simulator instruction rate (inst/s) +host_op_rate 84510 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1175755462 # Simulator tick rate (ticks/s) +host_mem_usage 411412 # Number of bytes of host memory used +host_seconds 938.07 # Real time elapsed on the host +sim_insts 61586245 # Number of instructions simulated +sim_ops 79276446 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4368244 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 409472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4368500 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5247408 # Number of bytes read from this memory -system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409024 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory +system.physmem.bytes_read::total 59192100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 409472 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 814656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4268864 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4269568 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296208 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296912 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6391 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68326 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6398 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82017 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66701 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257967 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66712 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823537 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44207595 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823548 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44208004 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 370845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3960508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 371255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3960777 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4757610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53666243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 370845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 738615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3870404 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4757770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53667553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 371255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367773 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3871079 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729356 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6615173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3870404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44207595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729381 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6615873 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3871079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44208004 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 370845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3975921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 371255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3976190 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7486966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60281416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257953 # Total number of read requests seen -system.physmem.writeReqs 823537 # Total number of write requests seen -system.physmem.cpureqs 242283 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400508992 # Total number of bytes read from memory -system.physmem.bytesWritten 52706368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296208 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 367773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7487151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60283426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257967 # Total number of read requests seen +system.physmem.writeReqs 823548 # Total number of write requests seen +system.physmem.cpureqs 242288 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400509888 # Total number of bytes read from memory +system.physmem.bytesWritten 52707072 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59192100 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296912 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12582 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391384 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 12562 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391216 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391537 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391542 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390911 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390957 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391406 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390709 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390512 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391260 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51392 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 391259 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51233 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50996 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51009 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52043 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51565 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51007 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51500 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51252 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102949217500 # Total gap between requests +system.physmem.totGap 1102939019000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163000 # Categorize read packet sizes +system.physmem.readPktSize::6 163014 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66701 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 493596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26922 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5936 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66712 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 493693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1086258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5937 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -160,16 +160,16 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see @@ -182,8 +182,8 @@ system.physmem.wrQLenPdf::18 35806 # Wh system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see @@ -192,14 +192,14 @@ system.physmem.wrQLenPdf::28 32711 # Wh system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see -system.physmem.totQLat 199191841750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239011336750 # Sum of mem lat for all requests -system.physmem.totBusLat 31289160000 # Total cycles spent in databus access -system.physmem.totBankLat 8530335000 # Total cycles spent in bank access -system.physmem.avgQLat 31830.81 # Average queueing delay per request -system.physmem.avgBankLat 1363.15 # Average bank access latency per request +system.physmem.totQLat 199192058500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239013617250 # Sum of mem lat for all requests +system.physmem.totBusLat 31289230000 # Total cycles spent in databus access +system.physmem.totBankLat 8532328750 # Total cycles spent in bank access +system.physmem.avgQLat 31830.77 # Average queueing delay per request +system.physmem.avgBankLat 1363.46 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38193.95 # Average memory access latency +system.physmem.avgMemAccLat 38194.23 # Average memory access latency system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s @@ -207,12 +207,12 @@ system.physmem.avgConsumedWrBW 6.62 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 11.98 # Average write queue length over time -system.physmem.readRowHits 6213974 # Number of row buffer hits during reads -system.physmem.writeRowHits 800028 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.05 # Average write queue length over time +system.physmem.readRowHits 6213954 # Number of row buffer hits during reads +system.physmem.writeRowHits 800040 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155751.01 # Average gap between requests +system.physmem.avgGap 155749.02 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -231,251 +231,251 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72704 # number of replacements -system.l2c.tagsinuse 53743.106475 # Cycle average of tags in use -system.l2c.total_refs 1840692 # Total number of references to valid blocks. -system.l2c.sampled_refs 137860 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.351893 # Average number of references to valid blocks. +system.l2c.replacements 72718 # number of replacements +system.l2c.tagsinuse 53743.140165 # Cycle average of tags in use +system.l2c.total_refs 1840331 # Total number of references to valid blocks. +system.l2c.sampled_refs 137862 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.349081 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39373.484726 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.828040 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 1.177687 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4008.510797 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2822.170311 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.062329 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.921455 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3716.471787 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3805.479341 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600792 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39373.587396 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.826422 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 1.187080 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4008.736100 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2822.118244 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.062372 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.921462 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3716.187342 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3805.513745 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600793 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000018 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061165 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043063 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.061168 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.043062 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056709 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.058067 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.056705 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.058068 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.820055 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21930 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4443 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166642 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30274 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5231 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 590416 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 197851 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403403 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581067 # number of Writeback hits -system.l2c.Writeback_hits::total 581067 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1230 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 737 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1967 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 199 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 342 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48406 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58608 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107014 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21930 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4443 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 215048 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30274 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5231 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 590416 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256459 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510417 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21930 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4443 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386616 # number of overall hits -system.l2c.overall_hits::cpu0.data 215048 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30274 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5231 # number of overall hits -system.l2c.overall_hits::cpu1.inst 590416 # number of overall hits -system.l2c.overall_hits::cpu1.data 256459 # number of overall hits -system.l2c.overall_hits::total 1510417 # number of overall hits +system.l2c.ReadReq_hits::cpu0.dtb.walker 22141 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386239 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166660 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30329 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5168 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 590386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 197820 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1403245 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 580806 # number of Writeback hits +system.l2c.Writeback_hits::total 580806 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1235 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 743 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1978 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 145 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 346 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48231 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58599 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106830 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22141 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386239 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214891 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30329 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5168 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 590386 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256419 # number of demand (read+write) hits +system.l2c.demand_hits::total 1510075 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22141 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4502 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386239 # number of overall hits +system.l2c.overall_hits::cpu0.data 214891 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30329 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5168 # number of overall hits +system.l2c.overall_hits::cpu1.inst 590386 # number of overall hits +system.l2c.overall_hits::cpu1.data 256419 # number of overall hits +system.l2c.overall_hits::total 1510075 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6270 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6414 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6277 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6416 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 6302 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 6301 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25320 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5137 # number of UpgradeReq misses +system.l2c.ReadReq_misses::total 25330 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5125 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 3774 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8911 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 641 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 414 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1055 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63277 # number of ReadExReq misses +system.l2c.UpgradeReq_misses::total 8899 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 638 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 411 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1049 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63279 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 76923 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140200 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140202 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6270 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69691 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6277 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69695 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 6302 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 83224 # number of demand (read+write) misses -system.l2c.demand_misses::total 165520 # number of demand (read+write) misses +system.l2c.demand_misses::total 165532 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6270 # number of overall misses -system.l2c.overall_misses::cpu0.data 69691 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6277 # number of overall misses +system.l2c.overall_misses::cpu0.data 69695 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu1.inst 6302 # number of overall misses system.l2c.overall_misses::cpu1.data 83224 # number of overall misses -system.l2c.overall_misses::total 165520 # number of overall misses +system.l2c.overall_misses::total 165532 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 728500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 255500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 345548000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 371089999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 324500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 347861000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 370402499 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1384000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 378000500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 393265500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1490340499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8952484 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 11872000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 20824484 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 614000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2820500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3434500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3142895481 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4127198996 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7270094477 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 379078500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 392453000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1492300499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8816984 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 11833500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 20650484 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 568000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2844000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3412000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3138283486 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4133582496 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7271865982 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 728500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 255500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 345548000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3513985480 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 324500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 347861000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3508685985 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 1384000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 68500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 378000500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4520464496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8760434976 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 379078500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4526035496 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8764166481 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 728500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 255500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 345548000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3513985480 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 324500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 347861000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3508685985 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 1384000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 68500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 378000500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4520464496 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8760434976 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 21941 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4447 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 392886 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 173056 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30291 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5232 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 596718 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 204152 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1428723 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 581067 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 581067 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6367 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4511 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10878 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 840 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 557 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1397 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111683 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135531 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247214 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 21941 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4447 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 392886 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 284739 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30291 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5232 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 596718 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 339683 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1675937 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 21941 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4447 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 392886 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 284739 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30291 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5232 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 596718 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 339683 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1675937 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000899 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015959 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.037063 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000191 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010561 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030864 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017722 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.806816 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836622 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.819176 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.763095 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.743268 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.755190 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.566577 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.567568 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.567120 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000899 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015959 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244754 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000191 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.245005 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098763 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000501 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000899 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015959 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244754 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000191 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.245005 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098763 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu1.inst 379078500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4526035496 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8764166481 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 22152 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4507 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 392516 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 173076 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30346 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5169 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 596688 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204121 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1428575 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 580806 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 580806 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6360 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4517 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10877 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 839 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 556 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1395 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111510 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135522 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247032 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 22152 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4507 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 392516 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 284586 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30346 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5169 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 596688 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 339643 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1675607 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 22152 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4507 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 392516 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 284586 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30346 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5169 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 596688 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 339643 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1675607 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001109 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015992 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.037070 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000193 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010562 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030869 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017731 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805818 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835510 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.818148 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.760429 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.739209 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.751971 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.567474 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.567605 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.567546 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001109 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015992 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.244900 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000193 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010562 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.245034 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098789 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001109 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015992 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.244900 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000193 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010562 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.245034 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098789 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 63875 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55111.323764 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 57856.251793 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 64900 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55418.352716 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 57731.062812 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 59981.037766 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 62413.188383 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 58860.209281 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1742.745571 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3145.733969 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2336.941308 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 957.878315 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6812.801932 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3255.450237 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49668.844620 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53653.640602 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 51855.167454 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60152.094573 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 62284.240597 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 58914.350533 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1720.387122 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3135.532591 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2320.539836 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 890.282132 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6919.708029 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3252.621544 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49594.391283 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53736.626185 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 51867.063109 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55111.323764 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50422.371325 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 64900 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55418.352716 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 50343.439056 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 59981.037766 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 54316.837643 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52926.745868 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 60152.094573 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 54383.777468 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52945.451520 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55111.323764 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50422.371325 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 64900 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55418.352716 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 50343.439056 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 59981.037766 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 54316.837643 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52926.745868 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 60152.094573 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 54383.777468 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52945.451520 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -484,8 +484,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66701 # number of writebacks -system.l2c.writebacks::total 66701 # number of writebacks +system.l2c.writebacks::writebacks 66712 # number of writebacks +system.l2c.writebacks::total 66712 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits @@ -502,162 +502,162 @@ system.l2c.overall_mshr_hits::cpu1.inst 7 # nu system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6266 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6377 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6273 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6379 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 6295 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 6277 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25248 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5137 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25258 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5125 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 3774 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8911 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 641 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 414 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1055 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63277 # number of ReadExReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8899 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 638 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 411 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1049 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63279 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 76923 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140200 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140202 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6266 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69654 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6273 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69658 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 17 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 6295 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 83200 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165448 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165460 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6266 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69654 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6273 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69658 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 6295 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 83200 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165448 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165460 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 591261 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 205753 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 267326853 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 290309543 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 262004 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 269548612 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 289309796 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 299283802 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 313561196 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1172505926 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51651498 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38386206 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 90037704 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6474116 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4151410 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10625526 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2358673626 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3165005465 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5523679091 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300356052 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312753448 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1174048691 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51546985 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38368705 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 89915690 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6444113 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4119409 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10563522 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2354035161 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3171377741 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5525412902 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 591261 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 205753 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 267326853 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2648983169 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 262004 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 269548612 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2643344957 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 299283802 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3478566661 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6696185017 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 300356052 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3484131189 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6699461593 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 591261 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 205753 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 267326853 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2648983169 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 262004 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 269548612 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2643344957 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 299283802 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3478566661 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6696185017 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 300356052 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3484131189 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6699461593 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5299085 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408173048 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408099047 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2100282 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667335749 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167082908164 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050136738 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25922783304 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 26972920042 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667429748 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167082928162 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050132738 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25922779804 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 26972912542 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299085 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458309786 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458231785 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2100282 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180590119053 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 194055828206 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036849 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030747 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017672 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806816 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836622 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.819176 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.763095 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.743268 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755190 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566577 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567568 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.567120 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098720 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098720 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180590209552 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 194055840704 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030751 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017681 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805818 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835510 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.818148 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.760429 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.739209 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.751971 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567474 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567605 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567546 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098746 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098746 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45524.469657 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45353.471704 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49953.990123 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46439.556638 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10054.798131 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10171.225755 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.107732 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.024961 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.560386 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.588626 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37275.370609 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41145.112190 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39398.566983 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49825.306357 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46482.250812 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.948293 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10166.588500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.021800 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.490596 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892944 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10070.087703 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37200.890675 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41227.951861 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39410.371478 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -678,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6001263 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4576664 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295188 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3775279 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2913941 # Number of BTB hits +system.cpu0.branchPred.lookups 5998401 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4575821 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 294349 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3757481 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2911128 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.184786 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673658 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28611 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.475521 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672992 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28616 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8907872 # DTB read hits -system.cpu0.dtb.read_misses 28815 # DTB read misses -system.cpu0.dtb.write_hits 5138143 # DTB write hits -system.cpu0.dtb.write_misses 5606 # DTB write misses +system.cpu0.dtb.read_hits 8907261 # DTB read hits +system.cpu0.dtb.read_misses 28773 # DTB read misses +system.cpu0.dtb.write_hits 5136781 # DTB write hits +system.cpu0.dtb.write_misses 5705 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.flush_entries 1814 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8936687 # DTB read accesses -system.cpu0.dtb.write_accesses 5143749 # DTB write accesses +system.cpu0.dtb.perms_faults 560 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8936034 # DTB read accesses +system.cpu0.dtb.write_accesses 5142486 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14046015 # DTB hits -system.cpu0.dtb.misses 34421 # DTB misses -system.cpu0.dtb.accesses 14080436 # DTB accesses -system.cpu0.itb.inst_hits 4220167 # ITB inst hits -system.cpu0.itb.inst_misses 5223 # ITB inst misses +system.cpu0.dtb.hits 14044042 # DTB hits +system.cpu0.dtb.misses 34478 # DTB misses +system.cpu0.dtb.accesses 14078520 # DTB accesses +system.cpu0.itb.inst_hits 4215431 # ITB inst hits +system.cpu0.itb.inst_misses 5154 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -718,530 +718,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1350 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1535 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4225390 # ITB inst accesses -system.cpu0.itb.hits 4220167 # DTB hits -system.cpu0.itb.misses 5223 # DTB misses -system.cpu0.itb.accesses 4225390 # DTB accesses -system.cpu0.numCycles 67827032 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4220585 # ITB inst accesses +system.cpu0.itb.hits 4215431 # DTB hits +system.cpu0.itb.misses 5154 # DTB misses +system.cpu0.itb.accesses 4220585 # DTB accesses +system.cpu0.numCycles 67803924 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11757994 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32012326 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6001263 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3587599 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7516289 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1452567 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61154 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20647681 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4894 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47403 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85456 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.icacheStallCycles 11747073 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32000754 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5998401 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3584120 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7510773 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1450164 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 64498 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20642358 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46878 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85526 # Number of stall cycles due to pending quiesce instructions system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4218433 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 158199 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2369 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41163993 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004932 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385225 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.CacheLines 4213800 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157670 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2178 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41143503 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385262 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33655210 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565659 1.37% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816805 1.98% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 675504 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773580 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559421 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 670235 1.63% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352235 0.86% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3095344 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33640113 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 564874 1.37% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 815232 1.98% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 675522 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773200 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558709 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 669860 1.63% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351529 0.85% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3094464 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41163993 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088479 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471970 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12263422 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20589298 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6819290 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512710 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 979273 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935723 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64727 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40009195 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212284 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 979273 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12830808 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5739819 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12737837 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6714966 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2161290 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38908996 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1807 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435519 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1234283 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39260907 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175730932 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175696732 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34200 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30930361 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8330545 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411120 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370260 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5349265 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7648868 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5685535 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1126587 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1232322 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36830553 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895643 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37237747 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80326 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6284476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13189556 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256860 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41163993 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904619 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512118 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41143503 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088467 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471960 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12253117 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20585756 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6814381 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512539 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977710 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 934268 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64694 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39987776 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212486 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977710 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12820427 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5742393 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12731772 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6709970 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2161231 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38889294 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1829 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 434890 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1234500 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 47 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39244828 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175643455 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175609334 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34121 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30926653 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8318174 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411256 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370334 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5351915 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7647673 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5682766 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124413 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1217910 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36816448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895564 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37227077 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80165 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6275180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13166441 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256842 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41143503 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904811 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512506 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26023978 63.22% 63.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5734172 13.93% 77.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3165060 7.69% 84.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2475453 6.01% 90.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2094791 5.09% 95.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 945417 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 488035 1.19% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184059 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53028 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26013518 63.23% 63.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5726772 13.92% 77.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3163675 7.69% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2471330 6.01% 90.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2096927 5.10% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 946781 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 487184 1.18% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184280 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53036 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41163993 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41143503 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25953 2.43% 2.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 456 0.04% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841491 78.81% 81.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 199811 18.71% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25911 2.42% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841841 78.68% 81.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 201703 18.85% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22327853 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46961 0.13% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22320567 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46962 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9364731 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5445265 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9363552 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5443123 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37237747 # Type of FU issued -system.cpu0.iq.rate 0.549010 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1067711 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028673 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116813355 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44018555 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34334136 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8379 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3876 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38248858 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306561 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37227077 # Type of FU issued +system.cpu0.iq.rate 0.549040 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1069907 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028740 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116773591 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43995152 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34325365 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8374 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4656 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38240450 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4385 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307272 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372448 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2379 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13100 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 535058 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1372635 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2428 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13158 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 533443 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192712 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5628 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192715 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5605 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 979273 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4122692 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98715 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37844885 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85302 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7648868 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5685535 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571530 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40279 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2826 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13100 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150418 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117037 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267455 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36861439 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9223512 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 376308 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977710 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4125178 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98819 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37830480 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 84891 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7647673 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5682766 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571414 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40435 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2836 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13158 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149420 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117102 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 266522 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36852561 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9222790 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 374516 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118689 # number of nop insts executed -system.cpu0.iew.exec_refs 14621351 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4854206 # Number of branches executed -system.cpu0.iew.exec_stores 5397839 # Number of stores executed -system.cpu0.iew.exec_rate 0.543462 # Inst execution rate -system.cpu0.iew.wb_sent 36666981 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34338012 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18281082 # num instructions producing a value -system.cpu0.iew.wb_consumers 35173096 # num instructions consuming a value +system.cpu0.iew.exec_nop 118468 # number of nop insts executed +system.cpu0.iew.exec_refs 14619280 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4853073 # Number of branches executed +system.cpu0.iew.exec_stores 5396490 # Number of stores executed +system.cpu0.iew.exec_rate 0.543517 # Inst execution rate +system.cpu0.iew.wb_sent 36658484 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34329238 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18277167 # num instructions producing a value +system.cpu0.iew.wb_consumers 35166979 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506259 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519746 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506302 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519725 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6098128 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638783 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231564 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40184720 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778562 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740417 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6089898 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638722 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 230765 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40165793 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778810 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740848 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28508400 70.94% 70.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5724488 14.25% 85.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1913763 4.76% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974414 2.42% 92.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 785086 1.95% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 523080 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 385100 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 218421 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1151968 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28496220 70.95% 70.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5717219 14.23% 85.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1914261 4.77% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974261 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784320 1.95% 94.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 523319 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386116 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 218199 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1151878 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40184720 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23679748 # Number of instructions committed -system.cpu0.commit.committedOps 31286291 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40165793 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23678008 # Number of instructions committed +system.cpu0.commit.committedOps 31281512 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11426897 # Number of memory references committed -system.cpu0.commit.loads 6276420 # Number of loads committed -system.cpu0.commit.membars 229667 # Number of memory barriers committed -system.cpu0.commit.branches 4245051 # Number of branches committed +system.cpu0.commit.refs 11424361 # Number of memory references committed +system.cpu0.commit.loads 6275038 # Number of loads committed +system.cpu0.commit.membars 229662 # Number of memory barriers committed +system.cpu0.commit.branches 4244821 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27642937 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489354 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1151968 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27638419 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489334 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1151878 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75566033 # The number of ROB reads -system.cpu0.rob.rob_writes 75750322 # The number of ROB writes -system.cpu0.timesIdled 360462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26663039 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138032042 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23599006 # Number of Instructions Simulated -system.cpu0.committedOps 31205549 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23599006 # Number of Instructions Simulated -system.cpu0.cpi 2.874148 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.874148 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.347929 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.347929 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171822030 # number of integer regfile reads -system.cpu0.int_regfile_writes 34087122 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3256 # number of floating regfile reads -system.cpu0.fp_regfile_writes 900 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13007989 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451063 # number of misc regfile writes -system.cpu0.icache.replacements 392871 # number of replacements -system.cpu0.icache.tagsinuse 511.076375 # Cycle average of tags in use -system.cpu0.icache.total_refs 3794104 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393383 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.644809 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 75534199 # The number of ROB reads +system.cpu0.rob.rob_writes 75722713 # The number of ROB writes +system.cpu0.timesIdled 360446 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26660421 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138034694 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23597266 # Number of Instructions Simulated +system.cpu0.committedOps 31200770 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23597266 # Number of Instructions Simulated +system.cpu0.cpi 2.873381 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.873381 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.348022 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.348022 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171786019 # number of integer regfile reads +system.cpu0.int_regfile_writes 34080976 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3260 # number of floating regfile reads +system.cpu0.fp_regfile_writes 902 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13006141 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451094 # number of misc regfile writes +system.cpu0.icache.replacements 392511 # number of replacements +system.cpu0.icache.tagsinuse 511.076367 # Cycle average of tags in use +system.cpu0.icache.total_refs 3789958 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393023 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.643095 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076375 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.076367 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3794104 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3794104 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3794104 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3794104 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3794104 # number of overall hits -system.cpu0.icache.overall_hits::total 3794104 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 424196 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 424196 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 424196 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 424196 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 424196 # number of overall misses -system.cpu0.icache.overall_misses::total 424196 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5806369997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5806369997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5806369997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5806369997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5806369997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5806369997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4218300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4218300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4218300 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4218300 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4218300 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4218300 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100561 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100561 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100561 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100561 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100561 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100561 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13687.941416 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13687.941416 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13687.941416 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13687.941416 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2612 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3789958 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3789958 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3789958 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3789958 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3789958 # number of overall hits +system.cpu0.icache.overall_hits::total 3789958 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423709 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423709 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423709 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423709 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423709 # number of overall misses +system.cpu0.icache.overall_misses::total 423709 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803688497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5803688497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5803688497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5803688497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5803688497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5803688497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213667 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4213667 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4213667 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4213667 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4213667 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4213667 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13697.345341 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13697.345341 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13697.345341 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13697.345341 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2656 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 149 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.071895 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.825503 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30799 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30799 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30799 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30799 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30799 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30799 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393397 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393397 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393397 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393397 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393397 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393397 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4747932997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4747932997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4747932997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4747932997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4747932997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4747932997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30672 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30672 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30672 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30672 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30672 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30672 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393037 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393037 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393037 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393037 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393037 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393037 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4746801497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4746801497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4746801497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4746801497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4746801497 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4746801497 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093260 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093260 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093260 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.062542 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093277 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093277 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093277 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.238268 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 276008 # number of replacements -system.cpu0.dcache.tagsinuse 460.701040 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9261257 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276520 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.492178 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 275921 # number of replacements +system.cpu0.dcache.tagsinuse 460.698692 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9260016 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276433 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.498229 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 460.701040 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.899807 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.899807 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5781540 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5781540 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159285 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159285 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139162 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139162 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137068 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137068 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8940825 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8940825 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8940825 # number of overall hits -system.cpu0.dcache.overall_hits::total 8940825 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392645 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392645 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1583929 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1583929 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7462 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7462 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1976574 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1976574 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1976574 # number of overall misses -system.cpu0.dcache.overall_misses::total 1976574 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5479209500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5479209500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60675943869 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60675943869 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88042500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88042500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46456500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46456500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66155153369 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66155153369 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66155153369 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66155153369 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6174185 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6174185 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743214 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4743214 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147937 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147937 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144530 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144530 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10917399 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10917399 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10917399 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10917399 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063595 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063595 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333936 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333936 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059316 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059316 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051629 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051629 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.614219 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.614219 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38307.237174 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38307.237174 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.333333 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.333333 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6225.743768 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6225.743768 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33469.606182 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33469.606182 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8661 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5567 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 621 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.946860 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 67.890244 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 460.698692 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899802 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899802 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5779987 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5779987 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159663 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159663 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139233 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139233 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137076 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137076 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8939650 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8939650 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8939650 # number of overall hits +system.cpu0.dcache.overall_hits::total 8939650 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392818 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392818 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1582384 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1582384 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8769 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8769 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1975202 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1975202 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1975202 # number of overall misses +system.cpu0.dcache.overall_misses::total 1975202 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5481439500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5481439500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60566359369 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60566359369 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87760500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 87760500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46440000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46440000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66047798869 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66047798869 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66047798869 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66047798869 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172805 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6172805 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4742047 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4742047 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148002 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144540 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144540 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10914852 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10914852 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10914852 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10914852 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063637 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063637 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333692 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333692 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059249 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059249 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051640 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051640 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180965 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.180965 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180965 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.180965 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.145431 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.145431 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38275.386612 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38275.386612 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10008.039685 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10008.039685 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6221.864952 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6221.864952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33438.503439 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33438.503439 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8565 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5561 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 643 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.320373 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 68.654321 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256612 # number of writebacks -system.cpu0.dcache.writebacks::total 256612 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204222 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204222 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453551 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1453551 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657773 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657773 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657773 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657773 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188423 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188423 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130378 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130378 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8304 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8304 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7462 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7462 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318801 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318801 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318801 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318801 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378188000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378188000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4038291991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4038291991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66252500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66252500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31532500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31532500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6416479991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6416479991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6416479991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6416479991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514893000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514893000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180267878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180267878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695160878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695160878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030518 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030518 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051629 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051629 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12621.537710 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12621.537710 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30973.722492 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30973.722492 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7978.383911 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7978.383911 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4225.743768 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4225.743768 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks +system.cpu0.dcache.writebacks::total 256512 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204354 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204354 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452130 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1452130 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 476 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 476 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656484 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1656484 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656484 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1656484 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188464 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188464 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130254 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130254 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8293 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8293 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7464 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7464 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318718 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318718 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378480500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378480500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4031341491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4031341491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65938500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65938500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31512000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31512000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6409821991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6409821991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6409821991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6409821991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514864500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514864500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180302878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180302878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695167378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695167378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030531 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030531 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027468 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027468 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056033 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056033 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051640 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051640 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029200 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029200 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12620.343938 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12620.343938 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30949.847920 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30949.847920 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7951.103340 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7951.103340 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4221.864952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4221.864952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1249,38 +1249,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9071093 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7457126 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 408382 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6063336 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5242542 # Number of BTB hits +system.cpu1.branchPred.lookups 9068423 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7455270 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 408018 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6064102 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5241151 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.462997 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772870 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42976 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.429137 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772299 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42697 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42899284 # DTB read hits -system.cpu1.dtb.read_misses 36667 # DTB read misses -system.cpu1.dtb.write_hits 6823776 # DTB write hits -system.cpu1.dtb.write_misses 10740 # DTB write misses +system.cpu1.dtb.read_hits 42898238 # DTB read hits +system.cpu1.dtb.read_misses 36741 # DTB read misses +system.cpu1.dtb.write_hits 6823025 # DTB write hits +system.cpu1.dtb.write_misses 10725 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2487 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2008 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2490 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42935951 # DTB read accesses -system.cpu1.dtb.write_accesses 6834516 # DTB write accesses +system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42934979 # DTB read accesses +system.cpu1.dtb.write_accesses 6833750 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49723060 # DTB hits -system.cpu1.dtb.misses 47407 # DTB misses -system.cpu1.dtb.accesses 49770467 # DTB accesses -system.cpu1.itb.inst_hits 8396614 # ITB inst hits -system.cpu1.itb.inst_misses 5496 # ITB inst misses +system.cpu1.dtb.hits 49721263 # DTB hits +system.cpu1.dtb.misses 47466 # DTB misses +system.cpu1.dtb.accesses 49768729 # DTB accesses +system.cpu1.itb.inst_hits 8394494 # ITB inst hits +system.cpu1.itb.inst_misses 5446 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1289,114 +1289,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1535 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1530 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1557 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1510 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8402110 # ITB inst accesses -system.cpu1.itb.hits 8396614 # DTB hits -system.cpu1.itb.misses 5496 # DTB misses -system.cpu1.itb.accesses 8402110 # DTB accesses -system.cpu1.numCycles 408759365 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8399940 # ITB inst accesses +system.cpu1.itb.hits 8394494 # DTB hits +system.cpu1.itb.misses 5446 # DTB misses +system.cpu1.itb.accesses 8399940 # DTB accesses +system.cpu1.numCycles 408755802 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19792479 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66053661 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9071093 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6015412 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14141488 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3960570 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63871 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77254295 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41467 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129632 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.icacheStallCycles 19793701 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66043012 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9068423 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6013450 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14139093 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3958938 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 65451 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77253219 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41710 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129512 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8394649 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 740550 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114126730 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700802 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.045190 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 8392686 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 740378 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2825 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114124947 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700718 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.045131 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99992423 87.62% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796833 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937270 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1888150 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1516879 1.33% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570874 0.50% 92.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2130694 1.87% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410492 0.36% 94.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5883115 5.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99993030 87.62% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796567 0.70% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937489 0.82% 89.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1887963 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1516591 1.33% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 569617 0.50% 92.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2129815 1.87% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410324 0.36% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5883551 5.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114126730 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022192 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161595 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21309229 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76907002 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12785223 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523232 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2602044 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105609 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75190345 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327184 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2602044 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22692364 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31945147 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40728563 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11830258 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4328354 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69732759 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18777 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668377 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3086520 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 411 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73724172 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321062566 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321003544 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49048322 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24675850 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444626 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387642 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7869295 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13203135 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8142815 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1033166 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1534389 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63494746 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157882 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89124827 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94932 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16221194 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45699544 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277241 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114126730 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780929 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519205 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114124947 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022185 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161571 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21308374 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76909285 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12783383 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523008 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2600897 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105255 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98147 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75181804 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327202 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2600897 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22691617 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31944842 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40730815 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11827860 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4328916 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69723383 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18766 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668457 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3086605 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 426 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73713482 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321023926 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 320964994 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58932 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49048009 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24665473 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444684 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387735 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7872422 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13201823 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8142648 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1033883 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1534096 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63487985 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1158001 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89118015 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94635 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16215431 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45695453 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277388 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114124947 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780881 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519165 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83735089 73.37% 73.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8399712 7.36% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4300489 3.77% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3770900 3.30% 87.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10582685 9.27% 97.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1966579 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1024954 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 272498 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73824 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83732864 73.37% 73.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8404718 7.36% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4298594 3.77% 84.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3768314 3.30% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10582090 9.27% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1967507 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1024622 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 272364 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73874 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114126730 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114124947 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29743 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29701 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1424,13 +1424,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7545200 95.88% 96.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 293621 3.73% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7545557 95.86% 96.25% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 295033 3.75% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37614506 42.20% 42.56% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59141 0.07% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37610156 42.20% 42.55% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59163 0.07% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued @@ -1443,11 +1443,11 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued @@ -1456,363 +1456,367 @@ system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Ty system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43964242 49.33% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7171411 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43962640 49.33% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7170532 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89124827 # Type of FU issued -system.cpu1.iq.rate 0.218037 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7869560 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088298 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300373215 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80882348 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53634324 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14862 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8064 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96672574 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7816 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 343282 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89118015 # Type of FU issued +system.cpu1.iq.rate 0.218023 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7871289 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088324 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300359292 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80869896 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53629107 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8062 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6802 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96667481 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7826 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342650 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3450539 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3807 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17140 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1304937 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3449296 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3766 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17093 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1304806 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31906056 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888018 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31906048 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888017 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2602044 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24184461 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360387 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64757250 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 110652 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13203135 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8142815 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869312 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65433 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3547 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17140 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201642 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155418 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 357060 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86694604 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43269055 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2430223 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2600897 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24182074 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360611 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64750813 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 110749 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13201823 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8142648 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869251 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65576 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3534 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17093 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201242 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155476 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 356718 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86688682 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43267985 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2429333 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104622 # number of nop insts executed -system.cpu1.iew.exec_refs 50378581 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7000416 # Number of branches executed -system.cpu1.iew.exec_stores 7109526 # Number of stores executed -system.cpu1.iew.exec_rate 0.212092 # Inst execution rate -system.cpu1.iew.wb_sent 85717179 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53641131 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29911901 # num instructions producing a value -system.cpu1.iew.wb_consumers 53368558 # num instructions consuming a value +system.cpu1.iew.exec_nop 104827 # number of nop insts executed +system.cpu1.iew.exec_refs 50376799 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6999376 # Number of branches executed +system.cpu1.iew.exec_stores 7108814 # Number of stores executed +system.cpu1.iew.exec_rate 0.212079 # Inst execution rate +system.cpu1.iew.wb_sent 85711710 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53635909 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29908204 # num instructions producing a value +system.cpu1.iew.wb_consumers 53361522 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131229 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560478 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131217 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560483 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16124623 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880641 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311654 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111524686 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431704 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.400261 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16119527 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880613 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 311377 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111524050 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431703 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.400207 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94788278 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8230770 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2113389 1.89% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254382 1.12% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1243785 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 567669 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 997860 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 504120 0.45% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1824433 1.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94787660 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8229182 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2114661 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1254724 1.13% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1244333 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 567856 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 997712 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 503621 0.45% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1824301 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111524686 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38058920 # Number of instructions committed -system.cpu1.commit.committedOps 48145643 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111524050 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38058618 # Number of instructions committed +system.cpu1.commit.committedOps 48145315 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16590474 # Number of memory references committed -system.cpu1.commit.loads 9752596 # Number of loads committed -system.cpu1.commit.membars 190088 # Number of memory barriers committed -system.cpu1.commit.branches 5966646 # Number of branches committed +system.cpu1.commit.refs 16590369 # Number of memory references committed +system.cpu1.commit.loads 9752527 # Number of loads committed +system.cpu1.commit.membars 190082 # Number of memory barriers committed +system.cpu1.commit.branches 5966603 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42681359 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534484 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1824433 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42681078 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534481 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1824301 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172926580 # The number of ROB reads -system.cpu1.rob.rob_writes 131236338 # The number of ROB writes -system.cpu1.timesIdled 1408486 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294632635 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796502635 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37989281 # Number of Instructions Simulated -system.cpu1.committedOps 48076004 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37989281 # Number of Instructions Simulated -system.cpu1.cpi 10.759861 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.759861 # CPI: Total CPI of All Threads +system.cpu1.rob.rob_reads 172920681 # The number of ROB reads +system.cpu1.rob.rob_writes 131224345 # The number of ROB writes +system.cpu1.timesIdled 1408365 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294630855 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796488086 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37988979 # Number of Instructions Simulated +system.cpu1.committedOps 48075676 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37988979 # Number of Instructions Simulated +system.cpu1.cpi 10.759852 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.759852 # CPI: Total CPI of All Threads system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387915275 # number of integer regfile reads -system.cpu1.int_regfile_writes 56205449 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4899 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18464839 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405417 # number of misc regfile writes -system.cpu1.icache.replacements 596801 # number of replacements -system.cpu1.icache.tagsinuse 480.742161 # Cycle average of tags in use -system.cpu1.icache.total_refs 7752714 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 597313 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.979316 # Average number of references to valid blocks. +system.cpu1.int_regfile_reads 387889245 # number of integer regfile reads +system.cpu1.int_regfile_writes 56198451 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4879 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18462900 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405383 # number of misc regfile writes +system.cpu1.icache.replacements 596769 # number of replacements +system.cpu1.icache.tagsinuse 480.741673 # Cycle average of tags in use +system.cpu1.icache.total_refs 7750669 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 597281 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.976587 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.742161 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938950 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938950 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7752714 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7752714 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7752714 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7752714 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7752714 # number of overall hits -system.cpu1.icache.overall_hits::total 7752714 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641884 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641884 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641884 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641884 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641884 # number of overall misses -system.cpu1.icache.overall_misses::total 641884 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8651274491 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8651274491 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8651274491 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8651274491 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8651274491 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8651274491 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8394598 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8394598 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8394598 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8394598 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8394598 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8394598 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076464 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076464 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076464 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076464 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076464 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076464 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.940704 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13477.940704 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13477.940704 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13477.940704 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2229 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 480.741673 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.938949 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.938949 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7750669 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7750669 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7750669 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7750669 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7750669 # number of overall hits +system.cpu1.icache.overall_hits::total 7750669 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641966 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641966 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641966 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641966 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641966 # number of overall misses +system.cpu1.icache.overall_misses::total 641966 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8653423491 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8653423491 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8653423491 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8653423491 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8653423491 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8653423491 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8392635 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8392635 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8392635 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8392635 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8392635 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8392635 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076492 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076492 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076492 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076492 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076492 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076492 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.566661 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13479.566661 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13479.566661 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13479.566661 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2249 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 165 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.509091 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.630303 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44542 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44542 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44542 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44542 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44542 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44542 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597342 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 597342 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 597342 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 597342 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 597342 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 597342 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7075238492 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7075238492 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7075238492 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7075238492 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7075238492 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7075238492 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44655 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44655 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44655 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44655 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44655 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44655 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597311 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 597311 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 597311 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 597311 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 597311 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 597311 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076959992 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076959992 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076959992 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7076959992 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076959992 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7076959992 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071158 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071158 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071158 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.535445 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071171 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071171 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071171 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11848.032251 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 360372 # number of replacements -system.cpu1.dcache.tagsinuse 474.682760 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12670584 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 360741 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.123770 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 360267 # number of replacements +system.cpu1.dcache.tagsinuse 474.654017 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12671092 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360637 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.135308 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 474.682760 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.927115 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.927115 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8303637 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8303637 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4137955 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4137955 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97570 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97570 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94868 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94868 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12441592 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12441592 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12441592 # number of overall hits -system.cpu1.dcache.overall_hits::total 12441592 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 400129 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 400129 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1556605 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1556605 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13952 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13952 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10604 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10604 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1956734 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1956734 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1956734 # number of overall misses -system.cpu1.dcache.overall_misses::total 1956734 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6110776000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6110776000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61798994997 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61798994997 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128780500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 128780500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53871000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53871000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67909770997 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67909770997 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67909770997 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67909770997 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703766 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8703766 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694560 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5694560 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111522 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111522 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105472 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105472 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14398326 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14398326 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14398326 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14398326 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045972 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045972 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273349 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273349 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125105 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125105 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100539 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100539 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135900 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135900 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135900 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135900 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15272.014775 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15272.014775 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39701.141264 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39701.141264 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9230.253727 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9230.253727 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.252735 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.252735 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34705.673330 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34705.673330 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 24403 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 13534 # number of cycles access was blocked +system.cpu1.dcache.occ_blocks::cpu1.data 474.654017 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.927059 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.927059 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8304151 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8304151 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4137952 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4137952 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97565 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97565 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94853 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94853 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12442103 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12442103 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12442103 # number of overall hits +system.cpu1.dcache.overall_hits::total 12442103 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 399179 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 399179 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1556589 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1556589 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13972 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13972 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10605 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10605 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1955768 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1955768 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1955768 # number of overall misses +system.cpu1.dcache.overall_misses::total 1955768 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6101251500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6101251500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61874023496 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61874023496 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129109000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129109000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53792000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53792000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67975274996 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67975274996 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67975274996 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67975274996 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703330 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8703330 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5694541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111537 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111537 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105458 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105458 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14397871 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14397871 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14397871 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14397871 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045865 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045865 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273348 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273348 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100561 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100561 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135837 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135837 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135837 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135837 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15284.500187 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15284.500187 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39749.749931 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39749.749931 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9240.552534 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9240.552534 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.324375 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.324375 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34756.308006 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34756.308006 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 25344 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13325 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.328228 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 84.587500 # average number of cycles each access was blocked +system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.610811 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 84.872611 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324455 # number of writebacks -system.cpu1.dcache.writebacks::total 324455 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172117 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 172117 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395143 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1395143 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1446 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1446 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567260 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1567260 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567260 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1567260 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228012 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228012 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161462 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161462 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12506 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 324294 # number of writebacks +system.cpu1.dcache.writebacks::total 324294 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171223 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171223 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395128 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395128 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566351 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566351 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566351 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566351 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227956 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 227956 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161461 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161461 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12522 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12522 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389474 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389474 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389474 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389474 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2852988500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2852988500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131820706 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131820706 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87942500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87942500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32671000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32671000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7984809206 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7984809206 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7984809206 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7984809206 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989984000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989984000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691030962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691030962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681014962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681014962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026197 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026197 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389417 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389417 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389417 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389417 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2851782000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2851782000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5138031205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5138031205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88180500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88180500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32594000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32594000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989813205 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7989813205 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989813205 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7989813205 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990081000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990081000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691035962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691035962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681116962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681116962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026192 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026192 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112139 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112139 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100501 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100501 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.448906 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.448906 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31783.458064 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31783.458064 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7032.024628 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7032.024628 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3082.169811 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3082.169811 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112268 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112268 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100514 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100514 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027047 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027047 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12510.230044 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12510.230044 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31822.119304 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31822.119304 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7042.045999 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7042.045999 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.905660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.905660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1834,18 +1838,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540140520228 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540140520228 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540140520228 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540140520228 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540139410201 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540139410201 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540139410201 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540139410201 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41727 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 814bf6bde..faf182914 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -630,6 +630,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index 3ee89fc27..eda827fb8 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index cc635c8e8..59b881f50 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:38:19 -gem5 started Feb 13 2013 20:56:17 -gem5 executing on u200540-lin +gem5 compiled Feb 25 2013 18:24:48 +gem5 started Feb 25 2013 22:58:34 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2533147650000 because m5_exit instruction encountered +Exiting @ tick 2533144795000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 21b68a213..9b1cbcf2d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,128 +1,128 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.533144 # Number of seconds simulated -sim_ticks 2533143504000 # Number of ticks simulated -final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2533143973500 # Number of ticks simulated +final_tick 2533143973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80573 # Simulator instruction rate (inst/s) -host_op_rate 103675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3384348477 # Simulator tick rate (ticks/s) -host_mem_usage 408856 # Number of bytes of host memory used -host_seconds 748.49 # Real time elapsed on the host +host_inst_rate 64483 # Simulator instruction rate (inst/s) +host_op_rate 82972 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2708528376 # Simulator tick rate (ticks/s) +host_mem_usage 405264 # Number of bytes of host memory used +host_seconds 935.25 # Real time elapsed on the host sim_insts 60307579 # Number of instructions simulated sim_ops 77599125 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory -system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory +system.physmem.bytes_read::total 129430480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798408 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096817 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59099 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813117 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1061 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493139 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2683783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1061 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096820 # Total number of read requests seen -system.physmem.writeReqs 813121 # Total number of write requests seen -system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966196480 # Total number of bytes read from memory -system.physmem.bytesWritten 52039744 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 314474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096817 # Total number of read requests seen +system.physmem.writeReqs 813117 # Total number of write requests seen +system.physmem.cpureqs 218351 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966196288 # Total number of bytes read from memory +system.physmem.bytesWritten 52039488 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129430480 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798408 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943948 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943206 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943088 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 943622 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50900 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533142364000 # Total gap between requests +system.physmem.totGap 2533142848500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154576 # Categorize read packet sizes +system.physmem.readPktSize::6 154573 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59103 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59099 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108698 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16712 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10857 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -139,8 +139,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2634 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see @@ -160,8 +160,8 @@ system.physmem.wrQLenPdf::17 35353 # Wh system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::28 32584 # Wh system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests -system.physmem.totBusLat 75482965000 # Total cycles spent in databus access -system.physmem.totBankLat 16912788750 # Total cycles spent in bank access -system.physmem.avgQLat 26048.65 # Average queueing delay per request -system.physmem.avgBankLat 1120.31 # Average bank access latency per request +system.physmem.totQLat 393251142750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485645877750 # Sum of mem lat for all requests +system.physmem.totBusLat 75482950000 # Total cycles spent in databus access +system.physmem.totBankLat 16911785000 # Total cycles spent in bank access +system.physmem.avgQLat 26049.00 # Average queueing delay per request +system.physmem.avgBankLat 1120.24 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32168.96 # Average memory access latency +system.physmem.avgMemAccLat 32169.24 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -187,11 +187,11 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time system.physmem.avgWrQLen 9.55 # Average write queue length over time -system.physmem.readRowHits 15020273 # Number of row buffer hits during reads -system.physmem.writeRowHits 793117 # Number of row buffer hits during writes +system.physmem.readRowHits 15020272 # Number of row buffer hits during reads +system.physmem.writeRowHits 793090 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159217.58 # Average gap between requests +system.physmem.avgGap 159217.68 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -210,38 +210,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14678084 # Number of BP lookups -system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits +system.cpu.branchPred.lookups 14675749 # Number of BP lookups +system.cpu.branchPred.condPredicted 11761615 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705306 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9809113 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7951342 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 81.060765 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398937 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51401633 # DTB read hits -system.cpu.dtb.read_misses 64365 # DTB read misses -system.cpu.dtb.write_hits 11702282 # DTB write hits -system.cpu.dtb.write_misses 15903 # DTB write misses +system.cpu.dtb.read_hits 51399217 # DTB read hits +system.cpu.dtb.read_misses 64403 # DTB read misses +system.cpu.dtb.write_hits 11701345 # DTB write hits +system.cpu.dtb.write_misses 15902 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3559 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3557 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2566 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 409 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51465998 # DTB read accesses -system.cpu.dtb.write_accesses 11718185 # DTB write accesses +system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51463620 # DTB read accesses +system.cpu.dtb.write_accesses 11717247 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63103915 # DTB hits -system.cpu.dtb.misses 80268 # DTB misses -system.cpu.dtb.accesses 63184183 # DTB accesses -system.cpu.itb.inst_hits 12333169 # ITB inst hits -system.cpu.itb.inst_misses 11311 # ITB inst misses +system.cpu.dtb.hits 63100562 # DTB hits +system.cpu.dtb.misses 80305 # DTB misses +system.cpu.dtb.accesses 63180867 # DTB accesses +system.cpu.itb.inst_hits 12332677 # ITB inst hits +system.cpu.itb.inst_misses 11271 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -250,113 +250,113 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2477 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2475 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2981 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12344480 # ITB inst accesses -system.cpu.itb.hits 12333169 # DTB hits -system.cpu.itb.misses 11311 # DTB misses -system.cpu.itb.accesses 12344480 # DTB accesses -system.cpu.numCycles 471839315 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12343948 # ITB inst accesses +system.cpu.itb.hits 12332677 # DTB hits +system.cpu.itb.misses 11271 # DTB misses +system.cpu.itb.accesses 12343948 # DTB accesses +system.cpu.numCycles 471840254 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30570540 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96039987 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14675749 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9350279 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21160212 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5300332 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123049 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95587623 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87979 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195754 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12329197 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5353 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151365911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785063 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150272 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130221030 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303083 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712964 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496255 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2215475 1.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108052 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2757455 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745629 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8805968 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 151365911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203543 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32532272 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95215917 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19186051 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962874 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3468797 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957839 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171569 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112632707 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 566700 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3468797 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34474935 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36706470 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52522148 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18150584 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6042977 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106114460 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20538 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4062916 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 612 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110534596 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485505463 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485414558 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90905 # Number of floating rename lookups system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 32144721 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830610 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737120 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12168217 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20326621 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13518825 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978093 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2487494 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97939378 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983579 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124329035 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167924 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21751378 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57069924 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501194 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151365911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821381 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534880 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107121434 70.77% 70.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13552589 8.95% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7069165 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5942277 3.93% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12602111 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2786608 1.84% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1699306 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465403 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127018 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151365911 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60927 0.69% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available @@ -385,13 +385,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365559 94.64% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412870 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58631029 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93272 0.08% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued @@ -407,7 +407,7 @@ system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued @@ -419,84 +419,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52917261 42.56% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12321634 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued -system.cpu.iq.rate 0.263513 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested +system.cpu.iq.FU_type_0::total 124329035 # Type of FU issued +system.cpu.iq.rate 0.263498 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839358 # FU busy when requested system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 409088132 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121690697 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85968255 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23084 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12548 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132792486 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12241 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623354 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 4672096 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6462 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1786745 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107738 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893837 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3469224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27949054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100148718 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 201036 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20329502 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13519419 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411238 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112362 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3468797 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27950970 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433267 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100144689 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200366 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20326621 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13518825 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410950 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112625 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3575 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269150 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619996 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121555637 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52088672 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2779958 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 350763 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269062 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619825 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121548947 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52086338 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2780088 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220929 # number of nop insts executed -system.cpu.iew.exec_refs 64302587 # number of memory reference insts executed -system.cpu.iew.exec_branches 11562998 # Number of branches executed -system.cpu.iew.exec_stores 12213915 # Number of stores executed -system.cpu.iew.exec_rate 0.257621 # Inst execution rate -system.cpu.iew.wb_sent 120394624 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85985291 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47225460 # num instructions producing a value -system.cpu.iew.wb_consumers 88174567 # num instructions consuming a value +system.cpu.iew.exec_nop 221732 # number of nop insts executed +system.cpu.iew.exec_refs 64299340 # number of memory reference insts executed +system.cpu.iew.exec_branches 11561583 # Number of branches executed +system.cpu.iew.exec_stores 12213002 # Number of stores executed +system.cpu.iew.exec_rate 0.257606 # Inst execution rate +system.cpu.iew.wb_sent 120388158 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85978549 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47221894 # num instructions producing a value +system.cpu.iew.wb_consumers 88170402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182220 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535575 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21490031 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 21486542 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147900474 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.515007 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 536246 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147897114 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525700 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515001 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13317188 9.00% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2119368 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1600636 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889854 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120445936 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13320013 9.01% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3904517 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2120442 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1947230 1.32% 95.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 967442 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598856 1.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701557 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2891121 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147900474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 147897114 # Number of insts commited each cycle system.cpu.commit.committedInsts 60457960 # Number of instructions committed system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -507,261 +507,261 @@ system.cpu.commit.branches 9961316 # Nu system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. system.cpu.commit.function_calls 991257 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889854 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2891121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242401590 # The number of ROB reads -system.cpu.rob.rob_writes 202045449 # The number of ROB writes -system.cpu.timesIdled 1769758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320469617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 242393474 # The number of ROB reads +system.cpu.rob.rob_writes 202038068 # The number of ROB writes +system.cpu.timesIdled 1769308 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320474343 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 60307579 # Number of Instructions Simulated system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated -system.cpu.cpi 7.823881 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823881 # CPI: Total CPI of All Threads +system.cpu.cpi 7.823896 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823896 # CPI: Total CPI of All Threads system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550352189 # number of integer regfile reads -system.cpu.int_regfile_writes 88467762 # number of integer regfile writes -system.cpu.fp_regfile_reads 8269 # number of floating regfile reads -system.cpu.fp_regfile_writes 2928 # number of floating regfile writes -system.cpu.misc_regfile_reads 30128398 # number of misc regfile reads +system.cpu.int_regfile_reads 550318447 # number of integer regfile reads +system.cpu.int_regfile_writes 88458212 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 30125052 # number of misc regfile reads system.cpu.misc_regfile_writes 831890 # number of misc regfile writes -system.cpu.icache.replacements 979593 # number of replacements +system.cpu.icache.replacements 979629 # number of replacements system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use -system.cpu.icache.total_refs 11270072 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980105 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.498841 # Average number of references to valid blocks. +system.cpu.icache.total_refs 11269534 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980141 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.497870 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11270072 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11270072 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11270072 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11270072 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11270072 # number of overall hits -system.cpu.icache.overall_hits::total 11270072 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059286 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059286 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059286 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059286 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059286 # number of overall misses -system.cpu.icache.overall_misses::total 1059286 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13991116996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13991116996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13991116996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13991116996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13991116996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13991116996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12329358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12329358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12329358 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12329358 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12329358 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12329358 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085916 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085916 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085916 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085916 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085916 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085916 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13208.063730 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13208.063730 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13208.063730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13208.063730 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4509 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11269534 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11269534 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11269534 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11269534 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11269534 # number of overall hits +system.cpu.icache.overall_hits::total 11269534 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059538 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059538 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059538 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059538 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059538 # number of overall misses +system.cpu.icache.overall_misses::total 1059538 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993400496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13993400496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13993400496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13993400496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13993400496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13993400496 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12329072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12329072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12329072 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12329072 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12329072 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12329072 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085938 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085938 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085938 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085938 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085938 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085938 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.077515 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13207.077515 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13207.077515 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13207.077515 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4855 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 305 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.639610 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.918033 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79147 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79147 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79147 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79147 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79147 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79147 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980139 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980139 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980139 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980139 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980139 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980139 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11380145996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11380145996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11380145996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11380145996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11380145996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11380145996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79361 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79361 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79361 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79361 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79361 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79361 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980177 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980177 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980177 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980177 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980177 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980177 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11379164996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11379164996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11379164996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11379164996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11379164996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11379164996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079496 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079496 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079496 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11610.747043 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11610.747043 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11610.747043 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11610.747043 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11610.747043 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11610.747043 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079501 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079501 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079501 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11609.296072 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11609.296072 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11609.296072 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11609.296072 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11609.296072 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11609.296072 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64347 # number of replacements -system.cpu.l2cache.tagsinuse 51347.741462 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1885858 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129741 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.535559 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498197510500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36929.511487 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.548284 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 64344 # number of replacements +system.cpu.l2cache.tagsinuse 51347.743422 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1885451 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129735 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.533094 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498197459500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36929.519444 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.551079 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8159.884348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6231.796994 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8159.886035 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6231.786516 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.563500 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000405 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.124510 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.095090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.783504 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52622 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10526 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966687 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387256 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1417091 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607840 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607840 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52475 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10450 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966729 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387264 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1416918 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607832 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607832 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112895 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112895 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52622 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10526 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 966687 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500151 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529986 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52622 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10526 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 966687 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500151 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529986 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 112902 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112902 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52475 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10450 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966729 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500166 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529820 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52475 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10450 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966729 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500166 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529820 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 42 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12342 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10709 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23094 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12340 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10707 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23091 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133191 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133191 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133192 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133192 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 42 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12342 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143900 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156285 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12340 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143899 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156283 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 42 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12342 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143900 # number of overall misses -system.cpu.l2cache.overall_misses::total 156285 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2975000 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 12340 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143899 # number of overall misses +system.cpu.l2cache.overall_misses::total 156283 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3043500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 697957500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 634176999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1335227499 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 522000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 522000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6733037500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6733037500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2975000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 696478000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 634908499 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1334547999 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 523500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 523500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6738135500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6738135500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3043500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 697957500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7367214499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8068264999 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2975000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 696478000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7373043999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8072683499 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3043500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 697957500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7367214499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8068264999 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52663 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10528 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979029 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397965 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440185 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607840 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607840 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2961 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 696478000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7373043999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8072683499 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52517 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10452 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 979069 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397971 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1440009 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607832 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607832 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246086 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246086 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52663 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10528 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979029 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686271 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52663 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10528 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979029 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686271 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000779 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012606 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026909 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246094 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246094 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52517 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10452 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 979069 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 644065 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1686103 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52517 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10452 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979069 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 644065 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1686103 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000800 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012604 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026904 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.016035 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986491 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986491 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985825 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985825 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541238 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541238 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000779 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012606 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223430 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092681 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000779 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012606 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223430 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092681 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72560.975610 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541224 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541224 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000800 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012604 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223423 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092689 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000800 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012604 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223423 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092689 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72464.285714 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56551.409820 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59219.067980 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57817.073655 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 178.705923 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 178.705923 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50551.745238 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50551.745238 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72560.975610 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56440.680713 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59298.449519 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57795.158243 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 179.219445 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 179.219445 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50589.641270 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50589.641270 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72464.285714 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56551.409820 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51196.765108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51625.331919 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72560.975610 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56440.680713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51237.631943 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51654.265013 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72464.285714 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56551.409820 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51196.765108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51625.331919 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56440.680713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51237.631943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51654.265013 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,8 +770,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59103 # number of writebacks -system.cpu.l2cache.writebacks::total 59103 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59099 # number of writebacks +system.cpu.l2cache.writebacks::total 59099 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits @@ -781,98 +781,98 @@ system.cpu.l2cache.demand_mshr_hits::total 74 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 42 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12330 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10647 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23020 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10645 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23017 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133191 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133191 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133192 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133192 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 42 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12330 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143838 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156211 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143837 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156209 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 42 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12330 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143838 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156211 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2463540 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143837 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156209 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2519791 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 543887277 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 499142740 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1045586808 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 542440021 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 499891739 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1044944802 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5073016629 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5073016629 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2463540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5078126850 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5078126850 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2519791 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 543887277 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5572159369 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6118603437 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2463540 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 542440021 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578018589 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6123071652 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2519791 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 543887277 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5572159369 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6118603437 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 542440021 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578018589 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6123071652 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079330 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002492267 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007571597 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903234989 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903234989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002548267 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007627597 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903237989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903237989 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079330 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905727256 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910806586 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026754 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905786256 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910865586 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026748 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015984 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986491 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986491 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985825 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985825 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541238 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541238 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092637 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092637 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541224 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541224 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092645 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092645 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44110.890268 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46881.068846 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45420.799652 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44000.650633 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46960.238516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45398.827041 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38088.283961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38088.283961 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38126.365322 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38126.365322 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -882,161 +882,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643539 # number of replacements +system.cpu.dcache.replacements 643553 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21509590 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644051 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.397340 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21507678 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644065 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.393645 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13756144 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13756144 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259539 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259539 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243175 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243175 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13754193 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13754193 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259605 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259605 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243146 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243146 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21015683 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21015683 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21015683 # number of overall hits -system.cpu.dcache.overall_hits::total 21015683 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737609 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737609 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962812 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962812 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13513 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13513 # number of LoadLockedReq misses +system.cpu.dcache.demand_hits::cpu.data 21013798 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21013798 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21013798 # number of overall hits +system.cpu.dcache.overall_hits::total 21013798 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737832 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737832 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962746 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962746 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13508 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700421 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700421 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700421 # number of overall misses -system.cpu.dcache.overall_misses::total 3700421 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9797923500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9797923500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104330736229 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104330736229 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180578000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180578000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3700578 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700578 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700578 # number of overall misses +system.cpu.dcache.overall_misses::total 3700578 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9800700500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9800700500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104414938731 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104414938731 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180553500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180553500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114128659729 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114128659729 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114128659729 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114128659729 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14493753 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14493753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 114215639231 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114215639231 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114215639231 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114215639231 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492025 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492025 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256688 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256688 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256654 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24716104 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24716104 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24716104 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24716104 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050892 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050892 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289837 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052644 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052644 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 24714376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714376 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714376 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714376 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050913 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289830 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289830 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052631 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052631 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149717 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149717 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149717 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149717 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.356765 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.356765 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35213.417601 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35213.417601 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13363.279805 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13363.279805 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.149734 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149734 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149734 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149734 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.105775 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.105775 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35242.622463 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35242.622463 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13366.412496 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.412496 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30842.074383 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30842.074383 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29695 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17222 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2648 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30864.270185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30864.270185 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29973 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17225 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2670 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.214124 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 68.341270 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.225843 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 68.353175 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607840 # number of writebacks -system.cpu.dcache.writebacks::total 607840 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351729 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351729 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713855 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713855 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1338 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1338 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065584 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065584 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065584 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385880 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385880 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248957 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248957 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks +system.cpu.dcache.writebacks::total 607832 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351946 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351946 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713780 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713780 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1332 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1332 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065726 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065726 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065726 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065726 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385886 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385886 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248966 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248966 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12176 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12176 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634837 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634837 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634837 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634837 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4811592500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4811592500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182885914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182885914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141167000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 634852 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634852 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634852 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634852 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4812474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4812474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8188067914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8188067914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141180000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141180000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12994478414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12994478414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12994478414 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12994478414 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395775000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395775000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742499011 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742499011 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138274011 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138274011 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024354 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024354 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047431 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13000541914 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13000541914 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13000541914 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13000541914 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395833000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395833000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742502511 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742502511 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138335511 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138335511 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047441 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047441 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025685 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025685 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12469.141961 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12469.141961 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32868.671755 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32868.671755 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.825462 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025688 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025688 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12471.232437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12471.232437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32888.297655 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32888.297655 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.940867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.940867 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1058,10 +1058,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610797601 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229610797601 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index a9a41c46d..22443d9d9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -773,6 +773,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index cb0094499..d1147fb64 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,167 +1,175 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401342 # Number of seconds simulated -sim_ticks 2401342466000 # Number of ticks simulated -final_tick 2401342466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401153 # Number of seconds simulated +sim_ticks 2401153455000 # Number of ticks simulated +final_tick 2401153455000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 244723 # Simulator instruction rate (inst/s) -host_op_rate 314293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9740625246 # Simulator tick rate (ticks/s) -host_mem_usage 401684 # Number of bytes of host memory used -host_seconds 246.53 # Real time elapsed on the host -sim_insts 60331304 # Number of instructions simulated -sim_ops 77482270 # Number of ops (including micro ops) simulated +host_inst_rate 200255 # Simulator instruction rate (inst/s) +host_op_rate 257182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7970039029 # Simulator tick rate (ticks/s) +host_mem_usage 397936 # Number of bytes of host memory used +host_seconds 301.27 # Real time elapsed on the host +sim_insts 60331276 # Number of instructions simulated +sim_ops 77481997 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 501920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7085968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 502176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7085840 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 85312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 678144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 678208 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 178368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1313020 # Number of bytes read from this memory -system.physmem.bytes_read::total 124662764 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 501920 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu2.inst 177920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1312828 # Number of bytes read from this memory +system.physmem.bytes_read::total 124662252 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 502176 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 85312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 178368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 765600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3747328 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 177920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 765408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3746944 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 1490908 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory system.physmem.bytes_written::cpu2.data 1325456 # Number of bytes written to this memory -system.physmem.bytes_written::total 6763144 # Number of bytes written to this memory +system.physmem.bytes_written::total 6762760 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14045 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110752 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14049 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110750 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1333 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10596 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10597 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20530 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512442 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58552 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2780 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20527 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512434 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58546 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 372727 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory system.physmem.num_writes::cpu2.data 331364 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 812500 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47818298 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 209016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2950836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 209139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2951015 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282451 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 74278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 546786 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51913780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209016 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 74278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560514 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83059 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 551965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2816401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 74098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 546749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51917653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 74098 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318767 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620913 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83065 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 552008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2816463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47818298 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3571700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3571928 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 365461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 365516 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 74278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1098750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54730181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12618170 # Total number of read requests seen -system.physmem.writeReqs 398699 # Total number of write requests seen -system.physmem.cpureqs 55066 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807562880 # Total number of bytes read from memory -system.physmem.bytesWritten 25516736 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102918908 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2643116 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2351 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 789127 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788875 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 789205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 789031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788756 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788906 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 788958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 788649 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 788041 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 788042 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 788299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788136 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788749 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 24964 # Track writes on a per bank basis +system.physmem.bw_total::cpu2.inst 74098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1098757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54734116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12597264 # Total number of read requests seen +system.physmem.writeReqs 398689 # Total number of write requests seen +system.physmem.cpureqs 55044 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 806224896 # Total number of bytes read from memory +system.physmem.bytesWritten 25516096 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102751100 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2642476 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 787593 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 787339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 787599 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 787924 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 787752 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 787476 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 787626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 787678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 787361 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 786762 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 786761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 787020 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 787004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 786857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 787043 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 787469 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 24965 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 24827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24766 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25058 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25057 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24837 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 24655 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 24742 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 25296 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25174 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 24743 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25297 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24838 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 24777 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 24716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24890 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24963 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24891 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24965 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25223 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 780903 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400307249500 # Total gap between requests +system.physmem.totGap 2400118241500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 15 # Categorize read packet sizes -system.physmem.readPktSize::3 12582912 # Categorize read packet sizes +system.physmem.readPktSize::3 12562016 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35243 # Categorize read packet sizes +system.physmem.readPktSize::6 35233 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 381227 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17472 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 816053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 797750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2260822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2261142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17462 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 814730 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 790825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 796437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2993221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2257059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2257380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2245823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,29 +186,29 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 2982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3011 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 17344 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 17332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 17331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 17319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17312 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 17309 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17299 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 17293 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 17291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14405 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 14382 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 14357 # What write queue length does an incoming req see @@ -209,320 +217,294 @@ system.physmem.wrQLenPdf::28 14353 # Wh system.physmem.wrQLenPdf::29 14351 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 14349 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 14347 # What write queue length does an incoming req see -system.physmem.totQLat 277225501500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 353051170250 # Sum of mem lat for all requests -system.physmem.totBusLat 63090845000 # Total cycles spent in databus access -system.physmem.totBankLat 12734823750 # Total cycles spent in bank access -system.physmem.avgQLat 21970.34 # Average queueing delay per request +system.physmem.totQLat 276742406750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 352442416750 # Sum of mem lat for all requests +system.physmem.totBusLat 62986320000 # Total cycles spent in databus access +system.physmem.totBankLat 12713690000 # Total cycles spent in bank access +system.physmem.avgQLat 21968.45 # Average queueing delay per request system.physmem.avgBankLat 1009.24 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27979.59 # Average memory access latency -system.physmem.avgRdBW 336.30 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27977.70 # Average memory access latency +system.physmem.avgRdBW 335.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.79 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.71 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12563520 # Number of row buffer hits during reads -system.physmem.writeRowHits 392353 # Number of row buffer hits during writes +system.physmem.readRowHits 12542718 # Number of row buffer hits during reads +system.physmem.writeRowHits 392355 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 184399.74 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 63278 # number of replacements -system.l2c.tagsinuse 50361.338948 # Cycle average of tags in use -system.l2c.total_refs 1750374 # Total number of references to valid blocks. -system.l2c.sampled_refs 128673 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.603273 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374434052500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36832.479753 # Average occupied blocks per requestor +system.physmem.avgGap 184681.97 # Average gap between requests +system.l2c.replacements 63270 # number of replacements +system.l2c.tagsinuse 50360.149873 # Cycle average of tags in use +system.l2c.total_refs 1749953 # Total number of references to valid blocks. +system.l2c.sampled_refs 128663 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.601059 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374435295000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36831.103707 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5142.503015 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3774.307963 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5142.534834 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3774.448687 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 800.237683 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 747.699491 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 9.796874 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.itb.walker 0.004225 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1464.578885 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1588.737598 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.562019 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu1.inst 800.238422 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 747.714108 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 9.797174 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1464.546789 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1588.772692 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.561998 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078468 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057591 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.078469 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057594 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.012211 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.011409 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.dtb.walker 0.000149 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.022348 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.024242 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768453 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9023 # number of ReadReq hits +system.l2c.occ_percent::cpu2.inst 0.022347 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.024243 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.768435 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9031 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3354 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 461813 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1136 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 133321 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 66093 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18237 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4298 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 284840 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 138220 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1292045 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597703 # number of Writeback hits -system.l2c.Writeback_hits::total 597703 # number of Writeback hits +system.l2c.ReadReq_hits::cpu0.inst 461816 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 169436 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2567 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1134 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 133590 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 65938 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18164 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4274 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 284408 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 137993 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291705 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597677 # number of Writeback hits +system.l2c.Writeback_hits::total 597677 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60564 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19513 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33544 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113621 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9023 # number of demand (read+write) hits +system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 60640 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 19583 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33391 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113614 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9031 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3354 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 461813 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 229693 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1136 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 133321 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 85606 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18237 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4298 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 284840 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 171764 # number of demand (read+write) hits -system.l2c.demand_hits::total 1405666 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9023 # number of overall hits +system.l2c.demand_hits::cpu0.inst 461816 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 230076 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2567 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1134 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 133590 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 85521 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18164 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4274 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 284408 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 171384 # number of demand (read+write) hits +system.l2c.demand_hits::total 1405319 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9031 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3354 # number of overall hits -system.l2c.overall_hits::cpu0.inst 461813 # number of overall hits -system.l2c.overall_hits::cpu0.data 229693 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2581 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1136 # number of overall hits -system.l2c.overall_hits::cpu1.inst 133321 # number of overall hits -system.l2c.overall_hits::cpu1.data 85606 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18237 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4298 # number of overall hits -system.l2c.overall_hits::cpu2.inst 284840 # number of overall hits -system.l2c.overall_hits::cpu2.data 171764 # number of overall hits -system.l2c.overall_hits::total 1405666 # number of overall hits +system.l2c.overall_hits::cpu0.inst 461816 # number of overall hits +system.l2c.overall_hits::cpu0.data 230076 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2567 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1134 # number of overall hits +system.l2c.overall_hits::cpu1.inst 133590 # number of overall hits +system.l2c.overall_hits::cpu1.data 85521 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18164 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4274 # number of overall hits +system.l2c.overall_hits::cpu2.inst 284408 # number of overall hits +system.l2c.overall_hits::cpu2.data 171384 # number of overall hits +system.l2c.overall_hits::total 1405319 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7429 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7433 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 6366 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 1333 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 1201 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.dtb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2787 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2568 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21699 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1417 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu2.inst 2780 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2564 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21691 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1419 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 511 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 974 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2902 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 105147 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9666 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 18550 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133363 # number of ReadExReq misses +system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 105149 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9669 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 18547 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133365 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7429 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 111513 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7433 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 111515 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 1333 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10867 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10870 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.dtb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2787 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 21118 # number of demand (read+write) misses -system.l2c.demand_misses::total 155062 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2780 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 21111 # number of demand (read+write) misses +system.l2c.demand_misses::total 155056 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7429 # number of overall misses -system.l2c.overall_misses::cpu0.data 111513 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7433 # number of overall misses +system.l2c.overall_misses::cpu0.data 111515 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu1.inst 1333 # number of overall misses -system.l2c.overall_misses::cpu1.data 10867 # number of overall misses +system.l2c.overall_misses::cpu1.data 10870 # number of overall misses system.l2c.overall_misses::cpu2.dtb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2787 # number of overall misses -system.l2c.overall_misses::cpu2.data 21118 # number of overall misses -system.l2c.overall_misses::total 155062 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2780 # number of overall misses +system.l2c.overall_misses::cpu2.data 21111 # number of overall misses +system.l2c.overall_misses::total 155056 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 75830000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 69208000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 75831000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 69197000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 884500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 178915500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 156399500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 481375000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 173677500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 153775000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 473434000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 137000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2.data 92000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 229000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 434051500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 982435000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1416486500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 434064000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 982245000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1416309000 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 75830000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 503259500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 75831000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 503261000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.dtb.walker 884500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 68500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 178915500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1138834500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1897861500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 173677500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1136020000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 1889743000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 75830000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 503259500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 75831000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 503261000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.dtb.walker 884500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 68500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 178915500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1138834500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1897861500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9024 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu2.inst 173677500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1136020000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 1889743000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9032 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3356 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 469242 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 175495 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2582 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1136 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 134654 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 67294 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 18247 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4299 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 287627 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 140788 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1313744 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597703 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597703 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1430 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 469249 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 175802 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2568 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1134 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 134923 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 67139 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 18174 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4274 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 287188 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 140557 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1313396 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597677 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597677 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1432 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 515 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 988 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 165711 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 29179 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 52094 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246984 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9024 # number of demand (read+write) accesses +system.l2c.UpgradeReq_accesses::cpu2.data 989 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2936 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 165789 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 29252 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 51938 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246979 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9032 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 3356 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 469242 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 341206 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2582 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1136 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 134654 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 96473 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 18247 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4299 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 287627 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 192882 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1560728 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9024 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 469249 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 341591 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2568 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1134 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 134923 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 96391 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 18174 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4274 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 287188 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 192495 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1560375 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9032 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 3356 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 469242 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 341206 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2582 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1136 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 134654 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 96473 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 18247 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4299 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 287627 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 192882 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1560728 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 469249 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 341591 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2568 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1134 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 134923 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 96391 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 18174 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4274 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 287188 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 192495 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1560375 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000111 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000596 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015832 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036275 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009899 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.017847 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000548 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000233 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.009690 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018240 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016517 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990909 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015840 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036211 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009880 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017888 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000550 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.009680 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018242 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016515 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990922 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992233 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.985830 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989431 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.634520 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.331266 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.356087 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539966 # miss rate for ReadExReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.984833 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989101 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.634234 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.330542 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.357099 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539985 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000111 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000596 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015832 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.326820 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009899 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.112643 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000548 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.000233 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.009690 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.109487 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099352 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015840 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.326458 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009880 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.112770 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000550 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.009680 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.109670 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099371 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000111 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000596 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015832 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.326820 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009899 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.112643 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000548 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.000233 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.009690 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.109487 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099352 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015840 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.326458 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009880 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.112770 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000550 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.009680 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.109670 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099371 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 56886.721680 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 57625.312240 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 56887.471868 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 57616.153206 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 88450 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 64196.447793 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 60903.232087 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 22184.202037 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 62473.920863 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 59974.648986 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 21826.287400 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 268.101761 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 94.455852 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 78.911096 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44904.976205 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52961.455526 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 10621.285514 # average ReadExReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 78.856749 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44892.336333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52959.777862 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 10619.795299 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 56886.721680 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46310.803350 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 56887.471868 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46298.160074 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 88450 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 68500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 64196.447793 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 53927.194810 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 12239.371993 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 62473.920863 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 53811.756904 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12187.487101 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 56886.721680 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46310.803350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 56887.471868 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46298.160074 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 88450 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 68500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 64196.447793 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 53927.194810 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 12239.371993 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 62473.920863 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 53811.756904 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12187.487101 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,8 +513,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58552 # number of writebacks -system.l2c.writebacks::total 58552 # number of writebacks +system.l2c.writebacks::writebacks 58546 # number of writebacks +system.l2c.writebacks::total 58546 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.data 8 # number of demand (read+write) MSHR hits @@ -543,131 +525,119 @@ system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 system.l2c.ReadReq_mshr_misses::cpu1.inst 1333 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 1201 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 10 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2787 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2560 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7893 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2780 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2556 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7881 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 511 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu2.data 974 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 1485 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9666 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 18550 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9669 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 18547 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 28216 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 1333 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10867 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10870 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.dtb.walker 10 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2787 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 21110 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 36109 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2780 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 21103 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 36097 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 1333 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10867 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10870 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.dtb.walker 10 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2787 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 21110 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 36109 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2780 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 21103 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 36097 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59113583 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54211451 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59114583 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54201951 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 759510 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 144190451 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 124139149 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 382526646 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5151985 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 139044199 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 121569649 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 374746143 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5152487 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9740974 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14892959 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 313700656 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 751148342 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1064848998 # number of ReadExReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14893461 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 313671410 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 751003559 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1064674969 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 59113583 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 367912107 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 59114583 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 367873361 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 759510 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 144190451 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 875287491 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1447375644 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 139044199 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 872573208 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1439421112 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 59113583 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 367912107 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 59114583 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 367873361 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 759510 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 144190451 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 875287491 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1447375644 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25246497500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26552444012 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51798941512 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 646821363 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9787797859 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 10434619222 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25893318863 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36340241871 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 62233560734 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009899 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017847 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000548 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009690 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018183 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.006008 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::cpu2.inst 139044199 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 872573208 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1439421112 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25246007500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26571413012 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51817420512 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647804863 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9786959359 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 10434764222 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25893812363 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36358372371 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 62252184734 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009880 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000550 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009680 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018185 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006000 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992233 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985830 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.506308 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.331266 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.356087 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.114242 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009899 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.112643 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000548 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009690 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.109445 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023136 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009899 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.112643 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000548 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009690 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.109445 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023136 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.984833 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.505790 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330542 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.357099 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.114245 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009880 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.112770 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009680 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.109629 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023134 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009880 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.112770 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009680 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.109629 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023134 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44346.273818 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45138.593672 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45130.683597 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 51736.796197 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48491.855078 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 48464.037248 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.162427 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 47562.460485 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 47550.582794 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10083.144814 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.928620 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32454.030209 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40493.172075 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37739.190459 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.266667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32440.935981 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40491.915620 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37733.022718 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44346.273818 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33855.903837 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33842.995492 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51736.796197 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41463.168688 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40083.515024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41348.301568 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39876.474832 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44346.273818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33855.903837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33842.995492 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51736.796197 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41463.168688 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40083.515024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41348.301568 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39876.474832 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -686,27 +656,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8066281 # DTB read hits -system.cpu0.dtb.read_misses 6214 # DTB read misses -system.cpu0.dtb.write_hits 6622863 # DTB write hits -system.cpu0.dtb.write_misses 2042 # DTB write misses +system.cpu0.dtb.read_hits 8076292 # DTB read hits +system.cpu0.dtb.read_misses 6232 # DTB read misses +system.cpu0.dtb.write_hits 6627548 # DTB write hits +system.cpu0.dtb.write_misses 2039 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5688 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5689 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 124 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 126 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8072495 # DTB read accesses -system.cpu0.dtb.write_accesses 6624905 # DTB write accesses +system.cpu0.dtb.read_accesses 8082524 # DTB read accesses +system.cpu0.dtb.write_accesses 6629587 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14689144 # DTB hits -system.cpu0.dtb.misses 8256 # DTB misses -system.cpu0.dtb.accesses 14697400 # DTB accesses -system.cpu0.itb.inst_hits 32699803 # ITB inst hits -system.cpu0.itb.inst_misses 3478 # ITB inst misses +system.cpu0.dtb.hits 14703840 # DTB hits +system.cpu0.dtb.misses 8271 # DTB misses +system.cpu0.dtb.accesses 14712111 # DTB accesses +system.cpu0.itb.inst_hits 32739442 # ITB inst hits +system.cpu0.itb.inst_misses 3479 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -722,400 +692,400 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32703281 # ITB inst accesses -system.cpu0.itb.hits 32699803 # DTB hits -system.cpu0.itb.misses 3478 # DTB misses -system.cpu0.itb.accesses 32703281 # DTB accesses -system.cpu0.numCycles 113984620 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32742921 # ITB inst accesses +system.cpu0.itb.hits 32739442 # DTB hits +system.cpu0.itb.misses 3479 # DTB misses +system.cpu0.itb.accesses 32742921 # DTB accesses +system.cpu0.numCycles 113988971 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32203473 # Number of instructions committed -system.cpu0.committedOps 42387015 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37536520 # Number of integer alu accesses +system.cpu0.committedInsts 32238592 # Number of instructions committed +system.cpu0.committedOps 42426848 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37569901 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5136 # Number of float alu accesses -system.cpu0.num_func_calls 1187911 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4237941 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37536520 # number of integer instructions +system.cpu0.num_func_calls 1188707 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4243711 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37569901 # number of integer instructions system.cpu0.num_fp_insts 5136 # number of float instructions -system.cpu0.num_int_register_reads 191230728 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39632670 # number of times the integer registers were written +system.cpu0.num_int_register_reads 191405612 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39677066 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu0.num_mem_refs 15352482 # number of memory refs -system.cpu0.num_load_insts 8433499 # Number of load instructions -system.cpu0.num_store_insts 6918983 # Number of store instructions -system.cpu0.num_idle_cycles 13416591638.099268 # Number of idle cycles -system.cpu0.num_busy_cycles -13302607018.099268 # Number of busy cycles -system.cpu0.not_idle_fraction -116.705280 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.705280 # Percentage of idle cycles +system.cpu0.num_mem_refs 15367259 # number of memory refs +system.cpu0.num_load_insts 8443691 # Number of load instructions +system.cpu0.num_store_insts 6923568 # Number of store instructions +system.cpu0.num_idle_cycles 13415307720.919615 # Number of idle cycles +system.cpu0.num_busy_cycles -13301318749.919615 # Number of busy cycles +system.cpu0.not_idle_fraction -116.689524 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.689524 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 892430 # number of replacements -system.cpu0.icache.tagsinuse 511.604238 # Cycle average of tags in use -system.cpu0.icache.total_refs 44287726 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 892942 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.597539 # Average number of references to valid blocks. +system.cpu0.icache.replacements 892272 # number of replacements +system.cpu0.icache.tagsinuse 511.604135 # Cycle average of tags in use +system.cpu0.icache.total_refs 44302234 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 892784 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 49.622567 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 8108819000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 477.620118 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.749624 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 16.234496 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.932852 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.034667 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.031708 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 477.646185 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 17.780881 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 16.177069 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.932903 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.034728 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.031596 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32232511 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8306544 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3748671 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44287726 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32232511 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8306544 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3748671 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44287726 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32232511 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8306544 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3748671 # number of overall hits -system.cpu0.icache.overall_hits::total 44287726 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 469964 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 134928 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 311926 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916818 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 469964 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 134928 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 311926 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916818 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 469964 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 134928 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 311926 # number of overall misses -system.cpu0.icache.overall_misses::total 916818 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820105000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4164885486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5984990486 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1820105000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4164885486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5984990486 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1820105000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4164885486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5984990486 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32702475 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8441472 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4060597 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 45204544 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32702475 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8441472 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4060597 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 45204544 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32702475 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8441472 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4060597 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 45204544 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014371 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015984 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076818 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020282 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014371 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015984 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076818 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020282 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014371 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015984 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076818 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020282 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13489.453635 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13352.158800 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6528.002816 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13489.453635 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13352.158800 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6528.002816 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13489.453635 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13352.158800 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6528.002816 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3429 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 32272136 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8284220 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3745878 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 44302234 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32272136 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8284220 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3745878 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 44302234 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32272136 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8284220 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3745878 # number of overall hits +system.cpu0.icache.overall_hits::total 44302234 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 469978 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 135194 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 311533 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916705 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 469978 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 135194 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 311533 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916705 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 469978 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 135194 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 311533 # number of overall misses +system.cpu0.icache.overall_misses::total 916705 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1823611000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4151773488 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5975384488 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1823611000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4151773488 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5975384488 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1823611000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4151773488 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5975384488 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32742114 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8419414 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4057411 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 45218939 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32742114 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8419414 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4057411 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 45218939 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32742114 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8419414 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4057411 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 45218939 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014354 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016057 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076781 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020273 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014354 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016057 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076781 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020273 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014354 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016057 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076781 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020273 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13488.845659 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13326.913964 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6518.328675 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13488.845659 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13326.913964 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6518.328675 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13488.845659 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13326.913964 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6518.328675 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2346 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 208 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 187 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.485577 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.545455 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23868 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23868 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23868 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23868 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23868 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23868 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 134928 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 288058 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 422986 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 134928 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 288058 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 422986 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 134928 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 288058 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 422986 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1550249000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3396275986 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4946524986 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1550249000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3396275986 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4946524986 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1550249000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3396275986 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4946524986 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015984 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070940 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009357 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015984 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070940 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009357 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015984 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070940 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009357 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11489.453635 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11790.250526 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11694.299542 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11489.453635 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11790.250526 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11694.299542 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11489.453635 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11790.250526 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11694.299542 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23911 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23911 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23911 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23911 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23911 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23911 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 135194 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287622 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 422816 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 135194 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 287622 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 422816 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 135194 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 287622 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 422816 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1553223000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3386037488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4939260488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1553223000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3386037488 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4939260488 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1553223000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3386037488 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4939260488 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016057 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070888 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009350 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016057 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070888 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009350 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016057 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070888 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009350 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.845659 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11772.526052 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11681.820196 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.845659 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11772.526052 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11681.820196 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.845659 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11772.526052 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11681.820196 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 630049 # number of replacements +system.cpu0.dcache.replacements 629965 # number of replacements system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23214638 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630561 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.815848 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 23216121 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630477 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.823105 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.732545 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 9.762803 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.501768 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.968228 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.019068 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012699 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 495.769504 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 9.745655 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.481956 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.968300 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.019034 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012660 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6947999 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1896291 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4462491 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13306781 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5945013 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1350334 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2123860 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9419207 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131148 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34213 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72919 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238280 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137519 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35934 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73941 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247394 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12893012 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3246625 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6586351 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22725988 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12893012 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3246625 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6586351 # number of overall hits -system.cpu0.dcache.overall_hits::total 22725988 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 169124 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 65573 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 283564 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 518261 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167141 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29694 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 600320 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 797155 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6371 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1721 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3875 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11967 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 336265 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 95267 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 883884 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1315416 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 336265 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 95267 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 883884 # number of overall misses -system.cpu0.dcache.overall_misses::total 1315416 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 913976500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4087103500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5001080000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 729946000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18483212402 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19213158402 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22529500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52387500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74917000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1643922500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 22570315902 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 24214238402 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1643922500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 22570315902 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 24214238402 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7117123 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1961864 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4746055 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13825042 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6112154 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1380028 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2724180 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits::cpu0.data 6957822 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1890811 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4457613 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13306246 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5949587 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1349737 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2121933 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9421257 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131174 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34256 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72800 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238230 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137548 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35976 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73869 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247393 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12907409 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3240548 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6579546 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22727503 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12907409 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3240548 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6579546 # number of overall hits +system.cpu0.dcache.overall_hits::total 22727503 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 169428 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 65419 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 282959 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 517806 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167221 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 29767 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 598117 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 795105 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6374 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1720 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3877 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11971 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 336649 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 95186 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 881076 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1312911 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 336649 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 95186 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 881076 # number of overall misses +system.cpu0.dcache.overall_misses::total 1312911 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 911962500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4076352000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4988314500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 730880500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18449241407 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19180121907 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22516000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52369500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 74885500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 39000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1642843000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 22525593407 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 24168436407 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1642843000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 22525593407 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 24168436407 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7127250 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1956230 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4740572 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13824052 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6116808 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1379504 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2720050 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 10216362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137519 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35934 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76794 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250247 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35934 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73943 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137548 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35976 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76677 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250201 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137548 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35976 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73872 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247396 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13229277 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3341892 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7470235 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24041404 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13229277 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3341892 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7470235 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24041404 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023763 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033424 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059747 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037487 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027346 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021517 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220367 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078027 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046328 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047893 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050460 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047821 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025418 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028507 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118321 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054715 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025418 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028507 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118321 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054715 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13938.305400 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14413.337024 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9649.732471 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24582.272513 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30788.933239 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24102.161314 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.935503 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13519.354839 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6260.299156 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 13244058 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3335734 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7460622 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24040414 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13244058 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3335734 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7460622 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24040414 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023772 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033441 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059689 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037457 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027338 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021578 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.219892 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.077827 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046340 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047810 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050563 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047846 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000041 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025419 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028535 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118097 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054613 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025419 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028535 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118097 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054613 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13940.330791 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14406.157783 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9633.558707 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24553.381261 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30845.539262 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 24122.753482 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.697674 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13507.737942 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6255.575975 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17255.949069 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25535.382360 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18408.046125 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17255.949069 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25535.382360 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18408.046125 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9020 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1069 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1100 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 51 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.200000 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20.960784 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17259.292333 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25566.004984 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18408.282364 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17259.292333 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25566.004984 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18408.282364 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9007 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1035 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1102 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 47 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.173321 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 22.021277 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597703 # number of writebacks -system.cpu0.dcache.writebacks::total 597703 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146204 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 146204 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 547277 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 547277 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 408 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 408 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 693481 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 693481 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 693481 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 693481 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65573 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137360 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 202933 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29694 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53043 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82737 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1721 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3467 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5188 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 95267 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 190403 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 285670 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 95267 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 190403 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 285670 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 782830500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1785427500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2568258000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 670558000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1431904990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2102462990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19087500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40642000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59729500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1453388500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3217332490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4670720990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1453388500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3217332490 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4670720990 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27581235500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28989086000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56570321500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1280021500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14116548125 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15396569625 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28861257000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43105634125 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71966891125 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028942 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021517 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019471 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008098 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047893 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045147 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020732 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028507 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025488 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011882 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028507 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025488 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011882 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.305400 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12998.161765 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12655.694244 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22582.272513 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26995.173538 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25411.399857 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.935503 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11722.526680 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11513.010794 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597677 # number of writebacks +system.cpu0.dcache.writebacks::total 597677 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145837 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 145837 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 545226 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 545226 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 406 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 406 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 691063 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 691063 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 691063 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 691063 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65419 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137122 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 202541 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29767 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52891 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82658 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1720 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3471 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5191 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 95186 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 190013 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 285199 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 95186 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 190013 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 285199 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 781124500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1779796500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2560921000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 671346500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1430416990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2101763490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19076000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40648000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59724000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1452471000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3210213490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4662684490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1452471000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3210213490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4662684490 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27580693500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29009829000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56590522500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281089000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14115638625 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15396727625 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28861782500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43125467625 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71987250125 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033441 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028925 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014651 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021578 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019445 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008091 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047810 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045268 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020747 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000041 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028535 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025469 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011863 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028535 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025469 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011863 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11940.330791 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.656802 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12643.963444 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22553.381261 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27044.619879 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25427.224104 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.697674 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11710.746183 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11505.297631 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15255.949069 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16897.488432 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16350.057724 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15255.949069 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16897.488432 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16350.057724 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15259.292333 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16894.704520 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16348.880922 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15259.292333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16894.704520 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16348.880922 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1128,27 +1098,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2177390 # DTB read hits -system.cpu1.dtb.read_misses 2104 # DTB read misses -system.cpu1.dtb.write_hits 1466734 # DTB write hits -system.cpu1.dtb.write_misses 391 # DTB write misses +system.cpu1.dtb.read_hits 2171794 # DTB read hits +system.cpu1.dtb.read_misses 2101 # DTB read misses +system.cpu1.dtb.write_hits 1466259 # DTB write hits +system.cpu1.dtb.write_misses 389 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1716 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 40 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 36 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 80 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2179494 # DTB read accesses -system.cpu1.dtb.write_accesses 1467125 # DTB write accesses +system.cpu1.dtb.read_accesses 2173895 # DTB read accesses +system.cpu1.dtb.write_accesses 1466648 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3644124 # DTB hits -system.cpu1.dtb.misses 2495 # DTB misses -system.cpu1.dtb.accesses 3646619 # DTB accesses -system.cpu1.itb.inst_hits 8441472 # ITB inst hits -system.cpu1.itb.inst_misses 1131 # ITB inst misses +system.cpu1.dtb.hits 3638053 # DTB hits +system.cpu1.dtb.misses 2490 # DTB misses +system.cpu1.dtb.accesses 3640543 # DTB accesses +system.cpu1.itb.inst_hits 8419414 # ITB inst hits +system.cpu1.itb.inst_misses 1129 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1157,73 +1127,73 @@ system.cpu1.itb.flush_tlb 277 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 829 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 827 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8442603 # ITB inst accesses -system.cpu1.itb.hits 8441472 # DTB hits -system.cpu1.itb.misses 1131 # DTB misses -system.cpu1.itb.accesses 8442603 # DTB accesses -system.cpu1.numCycles 574629535 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8420543 # ITB inst accesses +system.cpu1.itb.hits 8419414 # DTB hits +system.cpu1.itb.misses 1129 # DTB misses +system.cpu1.itb.accesses 8420543 # DTB accesses +system.cpu1.numCycles 574251142 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8231527 # Number of instructions committed -system.cpu1.committedOps 10483049 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9384758 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses -system.cpu1.num_func_calls 317840 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1148947 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9384758 # number of integer instructions -system.cpu1.num_fp_insts 1998 # number of float instructions -system.cpu1.num_int_register_reads 54113079 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10168310 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read +system.cpu1.committedInsts 8213191 # Number of instructions committed +system.cpu1.committedOps 10466435 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9372254 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses +system.cpu1.num_func_calls 317964 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1146067 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9372254 # number of integer instructions +system.cpu1.num_fp_insts 2062 # number of float instructions +system.cpu1.num_int_register_reads 54024867 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10146423 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3817736 # number of memory refs -system.cpu1.num_load_insts 2273251 # Number of load instructions -system.cpu1.num_store_insts 1544485 # Number of store instructions -system.cpu1.num_idle_cycles 533738024.963358 # Number of idle cycles -system.cpu1.num_busy_cycles 40891510.036642 # Number of busy cycles -system.cpu1.not_idle_fraction 0.071162 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.928838 # Percentage of idle cycles +system.cpu1.num_mem_refs 3811897 # number of memory refs +system.cpu1.num_load_insts 2267853 # Number of load instructions +system.cpu1.num_store_insts 1544044 # Number of store instructions +system.cpu1.num_idle_cycles 537580210.089888 # Number of idle cycles +system.cpu1.num_busy_cycles 36670931.910112 # Number of busy cycles +system.cpu1.not_idle_fraction 0.063859 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.936141 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4718167 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3836083 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 222496 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3137475 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2530778 # Number of BTB hits +system.cpu2.branchPred.lookups 4709991 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3829375 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 221875 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3139297 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2527298 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.662890 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 410861 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21436 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.505221 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 410694 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21534 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10866526 # DTB read hits -system.cpu2.dtb.read_misses 22717 # DTB read misses -system.cpu2.dtb.write_hits 3271799 # DTB write hits -system.cpu2.dtb.write_misses 5746 # DTB write misses +system.cpu2.dtb.read_hits 10865348 # DTB read hits +system.cpu2.dtb.read_misses 22611 # DTB read misses +system.cpu2.dtb.write_hits 3267482 # DTB write hits +system.cpu2.dtb.write_misses 5780 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2317 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 908 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 162 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 877 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 154 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 438 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10889243 # DTB read accesses -system.cpu2.dtb.write_accesses 3277545 # DTB write accesses +system.cpu2.dtb.perms_faults 449 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10887959 # DTB read accesses +system.cpu2.dtb.write_accesses 3273262 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14138325 # DTB hits -system.cpu2.dtb.misses 28463 # DTB misses -system.cpu2.dtb.accesses 14166788 # DTB accesses -system.cpu2.itb.inst_hits 4062010 # ITB inst hits -system.cpu2.itb.inst_misses 4544 # ITB inst misses +system.cpu2.dtb.hits 14132830 # DTB hits +system.cpu2.dtb.misses 28391 # DTB misses +system.cpu2.dtb.accesses 14161221 # DTB accesses +system.cpu2.itb.inst_hits 4058794 # ITB inst hits +system.cpu2.itb.inst_misses 4496 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1232,114 +1202,114 @@ system.cpu2.itb.flush_tlb 276 # Nu system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1567 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 990 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1061 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4066554 # ITB inst accesses -system.cpu2.itb.hits 4062010 # DTB hits -system.cpu2.itb.misses 4544 # DTB misses -system.cpu2.itb.accesses 4066554 # DTB accesses -system.cpu2.numCycles 88259424 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4063290 # ITB inst accesses +system.cpu2.itb.hits 4058794 # DTB hits +system.cpu2.itb.misses 4496 # DTB misses +system.cpu2.itb.accesses 4063290 # DTB accesses +system.cpu2.numCycles 88265633 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9446644 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32376030 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4718167 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2941639 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6823560 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1815993 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51150 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19328654 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 980 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33196 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 57154 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 380 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4060600 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 310025 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2087 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36989038 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.050362 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.436921 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9438008 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32342862 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4709991 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2937992 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6815885 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1813158 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 52200 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19319240 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 990 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33528 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 57014 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 272 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4057414 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 309972 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1938 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36961797 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.050032 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.436638 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30170666 81.57% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 382975 1.04% 82.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 509806 1.38% 83.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 812610 2.20% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 650446 1.76% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344174 0.93% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1009971 2.73% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 238143 0.64% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2870247 7.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30150982 81.57% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 382433 1.03% 82.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 508858 1.38% 83.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 812110 2.20% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 648973 1.76% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344473 0.93% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1008779 2.73% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 237853 0.64% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2867336 7.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36989038 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053458 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.366828 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10060365 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19264823 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6175765 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 293250 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1193736 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 611236 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 54016 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36687044 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 183513 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1193736 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10634106 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6560148 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11167231 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5875066 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1557700 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34442910 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2428 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 416233 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 878364 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 86 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 36942900 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 157448988 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 157420907 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 28081 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25732227 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11210672 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231165 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207502 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3338949 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6517311 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3844285 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 533485 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 782358 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31699556 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 512260 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34239526 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54408 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7411685 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19905699 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 155950 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36989038 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.925667 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.579936 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36961797 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053362 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.366426 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10050266 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19257143 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6169060 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 292369 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1191852 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 610072 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53860 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36648451 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 182697 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1191852 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10623039 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6559507 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11162234 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5869128 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1554979 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34406679 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2425 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 416595 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 876326 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 106 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 36902595 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 157291448 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 157264010 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27438 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25708511 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11194083 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 230845 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207258 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3329183 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6509687 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3839458 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 526321 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 767723 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31666176 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511259 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34215654 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 53951 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7402351 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19875920 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 155450 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36961797 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.925703 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.580463 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24424083 66.03% 66.03% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3914413 10.58% 76.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2344925 6.34% 82.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1979398 5.35% 88.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2782245 7.52% 95.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 897303 2.43% 98.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 479565 1.30% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 132664 0.36% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34442 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24411546 66.05% 66.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3907285 10.57% 76.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2341872 6.34% 82.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1974558 5.34% 88.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2782177 7.53% 95.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 896473 2.43% 98.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 480042 1.30% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 133126 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34718 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36989038 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36961797 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16741 1.09% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16658 1.09% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available @@ -1368,148 +1338,148 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1406719 91.75% 92.84% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109821 7.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1407260 91.71% 92.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110601 7.21% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61341 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19346638 56.50% 56.68% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 25970 0.08% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11366450 33.20% 89.96% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3438720 10.04% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61295 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19329502 56.49% 56.67% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25951 0.08% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 9 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 376 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11364260 33.21% 89.96% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3434245 10.04% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34239526 # Type of FU issued -system.cpu2.iq.rate 0.387942 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1533281 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044781 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 107077115 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39628603 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27373114 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7012 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3867 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3171 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35707743 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3723 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 207144 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34215654 # Type of FU issued +system.cpu2.iq.rate 0.387644 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1534519 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044848 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 107003021 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39584963 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27346219 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6827 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3771 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3100 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35685269 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3609 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 207108 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1578939 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1781 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9287 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 581487 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1576105 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1884 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9268 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 580803 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5366547 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352710 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5370889 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352686 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1193736 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4865575 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 91265 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32289220 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60072 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6517311 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3844285 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 370110 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31382 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2364 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9287 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105801 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88656 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 194457 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33253955 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11078248 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 985571 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1191852 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4868557 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 91379 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32255245 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 59750 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6509687 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3839458 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 369212 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31393 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2360 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9268 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105822 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88057 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193879 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33230591 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11076582 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 985063 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 77404 # number of nop insts executed -system.cpu2.iew.exec_refs 14484069 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3693959 # Number of branches executed -system.cpu2.iew.exec_stores 3405821 # Number of stores executed -system.cpu2.iew.exec_rate 0.376775 # Inst execution rate -system.cpu2.iew.wb_sent 32835376 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27376285 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15639881 # num instructions producing a value -system.cpu2.iew.wb_consumers 28443914 # num instructions consuming a value +system.cpu2.iew.exec_nop 77810 # number of nop insts executed +system.cpu2.iew.exec_refs 14478078 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3688656 # Number of branches executed +system.cpu2.iew.exec_stores 3401496 # Number of stores executed +system.cpu2.iew.exec_rate 0.376484 # Inst execution rate +system.cpu2.iew.wb_sent 32812407 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27349319 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15625261 # num instructions producing a value +system.cpu2.iew.wb_consumers 28412503 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.310180 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549850 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.309852 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549943 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7353370 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356310 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 169242 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35795177 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.689030 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.716377 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7344146 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 355809 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 168786 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35769820 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.688862 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.716544 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27161144 75.88% 75.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4182796 11.69% 87.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1257934 3.51% 91.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 650072 1.82% 92.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 572405 1.60% 94.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 318145 0.89% 95.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 398611 1.11% 96.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 289517 0.81% 97.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 964553 2.69% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27147085 75.89% 75.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4176329 11.68% 87.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1256730 3.51% 91.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 649005 1.81% 92.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 570906 1.60% 94.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 316592 0.89% 95.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 399111 1.12% 96.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 290067 0.81% 97.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 963995 2.69% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35795177 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19948032 # Number of instructions committed -system.cpu2.commit.committedOps 24663934 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35769820 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19931262 # Number of instructions committed +system.cpu2.commit.committedOps 24640483 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8201170 # Number of memory references committed -system.cpu2.commit.loads 4938372 # Number of loads committed -system.cpu2.commit.membars 94284 # Number of memory barriers committed -system.cpu2.commit.branches 3159330 # Number of branches committed -system.cpu2.commit.fp_insts 3119 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21896584 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294432 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 964553 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8192237 # Number of memory references committed +system.cpu2.commit.loads 4933582 # Number of loads committed +system.cpu2.commit.membars 94126 # Number of memory barriers committed +system.cpu2.commit.branches 3155533 # Number of branches committed +system.cpu2.commit.fp_insts 3055 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21875712 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294009 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 963995 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66322359 # The number of ROB reads -system.cpu2.rob.rob_writes 65269716 # The number of ROB writes -system.cpu2.timesIdled 360610 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51270386 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567282777 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19896304 # Number of Instructions Simulated -system.cpu2.committedOps 24612206 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19896304 # Number of Instructions Simulated -system.cpu2.cpi 4.435971 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.435971 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.225430 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.225430 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153619479 # number of integer regfile reads -system.cpu2.int_regfile_writes 29201382 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22411 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20842 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9012056 # number of misc regfile reads -system.cpu2.misc_regfile_writes 240747 # number of misc regfile writes +system.cpu2.rob.rob_reads 66266303 # The number of ROB reads +system.cpu2.rob.rob_writes 65202475 # The number of ROB writes +system.cpu2.timesIdled 360564 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51303836 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567277023 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19879493 # Number of Instructions Simulated +system.cpu2.committedOps 24588714 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19879493 # Number of Instructions Simulated +system.cpu2.cpi 4.440034 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.440034 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.225223 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.225223 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153509449 # number of integer regfile reads +system.cpu2.int_regfile_writes 29174173 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22340 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20840 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9001304 # number of misc regfile reads +system.cpu2.misc_regfile_writes 240409 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1524,10 +1494,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981147786186 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 981147786186 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981147786186 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 981147786186 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 979501914046 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 979501914046 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 979501914046 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 979501914046 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 9fab0b34a..4166fc5d7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1029,6 +1029,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 73a40b4c9..8c9cf8058 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,148 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.541289 # Number of seconds simulated -sim_ticks 2541288973500 # Number of ticks simulated -final_tick 2541288973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.541288 # Number of seconds simulated +sim_ticks 2541288206500 # Number of ticks simulated +final_tick 2541288206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61532 # Simulator instruction rate (inst/s) -host_op_rate 79175 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2592785663 # Simulator tick rate (ticks/s) -host_mem_usage 411940 # Number of bytes of host memory used -host_seconds 980.14 # Real time elapsed on the host -sim_insts 60309889 # Number of instructions simulated -sim_ops 77602313 # Number of ops (including micro ops) simulated +host_inst_rate 64704 # Simulator instruction rate (inst/s) +host_op_rate 83256 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2726411009 # Simulator tick rate (ticks/s) +host_mem_usage 408332 # Number of bytes of host memory used +host_seconds 932.10 # Real time elapsed on the host +sim_insts 60310239 # Number of instructions simulated +sim_ops 77602695 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 501184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4156432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 298496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4937244 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006380 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 501184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 298496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784960 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1345340 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1670772 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801072 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 503232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4160720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 298048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4933980 # Number of bytes read from this memory +system.physmem.bytes_read::total 131009132 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 503232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 298048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 801280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1345260 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1670852 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802288 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7831 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 64978 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4664 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77151 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293479 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59140 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336335 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417693 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813168 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47657126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 197216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1635561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 117459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1942811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51551154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 197216 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 117459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314675 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489386 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 657451 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676229 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47657126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 197216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2164953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 117459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2600262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54227384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293479 # Total number of read requests seen -system.physmem.writeReqs 813168 # Total number of write requests seen -system.physmem.cpureqs 218447 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978782656 # Total number of bytes read from memory -system.physmem.bytesWritten 52042752 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131006380 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801072 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956167 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956037 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955427 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955317 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50411 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50432 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50857 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50806 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51249 # Track writes on a per bank basis +system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7863 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 65045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4657 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77100 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293522 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336315 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417713 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813187 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47657140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 198022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1637248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 117282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1941527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51552253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 198022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 117282 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315305 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489865 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529361 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 657482 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676709 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47657140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 198022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2166610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 117282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2599009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54228961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293522 # Total number of read requests seen +system.physmem.writeReqs 813187 # Total number of write requests seen +system.physmem.cpureqs 218489 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978785408 # Total number of bytes read from memory +system.physmem.bytesWritten 52043968 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131009132 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6802288 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4667 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955614 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955982 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50414 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50430 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50633 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1856346 # Number of times wr buffer was full causing retry -system.physmem.totGap 2541287786000 # Total gap between requests +system.physmem.numWrRetry 1856598 # Number of times wr buffer was full causing retry +system.physmem.totGap 2541287063000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154620 # Categorize read packet sizes +system.physmem.readPktSize::6 154663 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754028 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59140 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 992061 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2698984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59159 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 992041 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2698919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -156,46 +168,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2910 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35346 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35291 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32476 # What write queue length does an incoming req see -system.physmem.totQLat 346721486500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439895947750 # Sum of mem lat for all requests -system.physmem.totBusLat 76467345000 # Total cycles spent in databus access -system.physmem.totBankLat 16707116250 # Total cycles spent in bank access -system.physmem.avgQLat 22671.21 # Average queueing delay per request +system.physmem.wrQLenPdf::18 35258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32483 # What write queue length does an incoming req see +system.physmem.totQLat 346675714750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439850413500 # Sum of mem lat for all requests +system.physmem.totBusLat 76467555000 # Total cycles spent in databus access +system.physmem.totBankLat 16707143750 # Total cycles spent in bank access +system.physmem.avgQLat 22668.16 # Average queueing delay per request system.physmem.avgBankLat 1092.43 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28763.65 # Average memory access latency +system.physmem.avgMemAccLat 28760.59 # Average memory access latency system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s @@ -203,243 +215,235 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.13 # Average write queue length over time -system.physmem.readRowHits 15218362 # Number of row buffer hits during reads -system.physmem.writeRowHits 794635 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.14 # Average write queue length over time +system.physmem.readRowHits 15218363 # Number of row buffer hits during reads +system.physmem.writeRowHits 794663 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes -system.physmem.avgGap 157778.82 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64388 # number of replacements -system.l2c.tagsinuse 51386.157207 # Cycle average of tags in use -system.l2c.total_refs 1906213 # Total number of references to valid blocks. -system.l2c.sampled_refs 129781 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.687920 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2505304860500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36943.345859 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 11.980136 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5122.722111 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3272.415541 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 10.482410 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3080.689127 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2944.521672 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563711 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000183 # Average percentage of cache occupancy +system.physmem.avgGap 157778.17 # Average gap between requests +system.l2c.replacements 64431 # number of replacements +system.l2c.tagsinuse 51403.772051 # Cycle average of tags in use +system.l2c.total_refs 1904252 # Total number of references to valid blocks. +system.l2c.sampled_refs 129822 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.668176 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2505297860000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36947.477101 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 17.181776 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.004228 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5147.781121 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3278.488158 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 8.683561 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3058.770363 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2945.385742 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563774 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000262 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078167 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.049933 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000160 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.047008 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044930 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784091 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32856 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 491369 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 213716 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30962 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7078 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 479886 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 173939 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1437367 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits -system.l2c.Writeback_hits::total 608382 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits +system.l2c.occ_percent::cpu0.inst 0.078549 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.050026 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000133 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.046673 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.044943 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784359 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32227 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7171 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 490580 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 213578 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30476 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6774 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 480341 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 174067 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435214 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608440 # number of Writeback hits +system.l2c.Writeback_hits::total 608440 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57851 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55061 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112912 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32856 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7561 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 491369 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 271567 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30962 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7078 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 479886 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 229000 # number of demand (read+write) hits -system.l2c.demand_hits::total 1550279 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32856 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7561 # number of overall hits -system.l2c.overall_hits::cpu0.inst 491369 # number of overall hits -system.l2c.overall_hits::cpu0.data 271567 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30962 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7078 # number of overall hits -system.l2c.overall_hits::cpu1.inst 479886 # number of overall hits -system.l2c.overall_hits::cpu1.data 229000 # number of overall hits -system.l2c.overall_hits::total 1550279 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 25 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7722 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6085 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4670 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4619 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1541 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1365 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 59871 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 73351 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133222 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7722 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 65956 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4670 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 77970 # number of demand (read+write) misses -system.l2c.demand_misses::total 156357 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7722 # number of overall misses -system.l2c.overall_misses::cpu0.data 65956 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4670 # number of overall misses -system.l2c.overall_misses::cpu1.data 77970 # number of overall misses -system.l2c.overall_misses::total 156357 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1696500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 425410000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 344277000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 826500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 270381000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 269029500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1311738500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 205000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 205500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 410500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3130049500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3648768000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6778817500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1696500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 425410000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3474326500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 826500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 270381000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3917797500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8090556000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1696500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 425410000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3474326500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 826500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 270381000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3917797500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8090556000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 32881 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7563 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 499091 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 219801 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30974 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7078 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 484556 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 178558 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1460502 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608382 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608382 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1561 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1383 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 117722 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 128412 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246134 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 32881 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7563 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 499091 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337523 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30974 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7078 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 484556 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 306970 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1706636 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 32881 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7563 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 499091 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337523 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30974 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7078 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 484556 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 306970 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1706636 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000760 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000264 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015472 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.027684 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009638 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.025868 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987188 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.986985 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.987092 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.508580 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.571216 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541258 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000760 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015472 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.195412 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009638 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.253999 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091617 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000760 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015472 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.195412 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009638 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.253999 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091617 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 67860 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55090.650091 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 56577.978636 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68875 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57897.430407 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 58244.100455 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 56699.308407 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 133.030500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 150.549451 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 141.259463 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52279.893438 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49743.943505 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 50883.619072 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 67860 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55090.650091 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52676.428225 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 57897.430407 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 50247.499038 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51744.124024 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 67860 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55090.650091 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52676.428225 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 57897.430407 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 50247.499038 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51744.124024 # average overall miss latency +system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57838 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55045 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112883 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32227 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7171 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 490580 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 271416 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30476 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6774 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 480341 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 229112 # number of demand (read+write) hits +system.l2c.demand_hits::total 1548097 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32227 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7171 # number of overall hits +system.l2c.overall_hits::cpu0.inst 490580 # number of overall hits +system.l2c.overall_hits::cpu0.data 271416 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30476 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6774 # number of overall hits +system.l2c.overall_hits::cpu1.inst 480341 # number of overall hits +system.l2c.overall_hits::cpu1.data 229112 # number of overall hits +system.l2c.overall_hits::total 1548097 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7754 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6099 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4662 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4629 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23185 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1530 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1369 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2899 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 59920 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 73280 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133200 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7754 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 66019 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4662 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 77909 # number of demand (read+write) misses +system.l2c.demand_misses::total 156385 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7754 # number of overall misses +system.l2c.overall_misses::cpu0.data 66019 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4662 # number of overall misses +system.l2c.overall_misses::cpu1.data 77909 # number of overall misses +system.l2c.overall_misses::total 156385 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1843000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 186500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 426974500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 345172998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1040500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 269759500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 270421498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1315398496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 183000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 204000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 387000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3134918000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3645169500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6780087500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1843000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 186500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 426974500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3480090998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1040500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 269759500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3915590998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8095485996 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1843000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 186500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 426974500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3480090998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1040500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 269759500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3915590998 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8095485996 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 32254 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7174 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 498334 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 219677 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30487 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6774 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 485003 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 178696 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1458399 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 608440 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 608440 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1548 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1385 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 6 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 117758 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 128325 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246083 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 32254 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7174 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 498334 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 337435 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30487 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6774 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 485003 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 307021 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1704482 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 32254 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7174 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 498334 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 337435 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30487 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6774 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 485003 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 307021 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1704482 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000837 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000418 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015560 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.027763 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000361 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009612 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.025904 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015898 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988372 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.988448 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.988408 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.166667 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.083333 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.508840 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.571050 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541281 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000837 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000418 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015560 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.195650 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000361 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009612 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.253758 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091749 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000837 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000418 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015560 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.195650 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000361 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009612 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.253758 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091749 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 68259.259259 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 62166.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55065.063193 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 56595.015248 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 94590.909091 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57863.470613 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 58418.988550 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 56734.893077 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 119.607843 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 149.013879 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 133.494308 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52318.391188 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49743.033570 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 50901.557808 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 68259.259259 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 62166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55065.063193 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52713.476393 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 94590.909091 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 57863.470613 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 50258.519529 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51766.384218 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 68259.259259 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 62166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55065.063193 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52713.476393 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 94590.909091 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 57863.470613 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 50258.519529 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51766.384218 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,158 +452,166 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59140 # number of writebacks -system.l2c.writebacks::total 59140 # number of writebacks +system.l2c.writebacks::writebacks 59159 # number of writebacks +system.l2c.writebacks::total 59159 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 20 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7712 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6046 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4664 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4599 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23060 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1541 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1365 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2906 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 59871 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 73351 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133222 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7712 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 65917 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4664 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 77950 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156282 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7712 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 65917 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4664 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 77950 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156282 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1386024 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 329024705 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 267448944 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 675012 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 211941612 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 210372572 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1020942120 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15411541 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13749804 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29161345 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2383249825 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2735103931 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5118353756 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1386024 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 329024705 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2650698769 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 675012 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 211941612 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2945476503 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6139295876 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1386024 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 329024705 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2650698769 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 675012 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 211941612 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2945476503 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6139295876 # number of overall MSHR miss cycles +system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7744 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6061 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4657 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4608 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23111 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1530 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1369 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2899 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 59920 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 73280 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133200 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7744 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 65981 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4657 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 77888 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156311 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 7744 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 65981 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4657 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 77888 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156311 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1507275 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 149502 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 330180239 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 268243202 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 901261 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 211476104 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 212129075 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1024586658 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15301530 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13761322 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29062852 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2387584034 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2732413305 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5119997339 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1507275 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 149502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 330180239 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2655827236 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 901261 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 211476104 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2944542380 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6144583997 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1507275 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 149502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 330180239 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2655827236 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 901261 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 211476104 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2944542380 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6144583997 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5050830 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84200622267 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82767168504 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166972841601 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10453604329 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13166783666 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 23620387995 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84192707267 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82774865254 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166972623351 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10456103308 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13163812667 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 23619915975 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5050830 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94654226596 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95933952170 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 190593229596 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025756 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015789 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987188 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986985 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.987092 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508580 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571216 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541258 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091573 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091573 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44235.683758 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45743.111981 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44273.292281 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94648810575 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95938677921 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190592539326 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025787 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015847 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988372 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988448 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988408 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508840 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571050 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541281 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091706 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091706 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44257.251609 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46034.955512 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44333.289689 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10073.116484 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.874398 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39806.414207 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.888795 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38419.733648 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10052.097882 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.130045 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39846.195494 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.299468 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38438.418461 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -622,155 +634,155 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7614306 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6072650 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 380012 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4955572 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4051897 # Number of BTB hits +system.cpu0.branchPred.lookups 7613725 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6072642 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 379429 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4956500 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4052223 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.764466 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 730604 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39458 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.755735 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 731018 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26054511 # DTB read hits -system.cpu0.dtb.read_misses 40169 # DTB read misses -system.cpu0.dtb.write_hits 5887052 # DTB write hits -system.cpu0.dtb.write_misses 9355 # DTB write misses +system.cpu0.dtb.read_hits 26054269 # DTB read hits +system.cpu0.dtb.read_misses 40148 # DTB read misses +system.cpu0.dtb.write_hits 5888543 # DTB write hits +system.cpu0.dtb.write_misses 9328 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5627 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1395 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1467 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 272 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26094680 # DTB read accesses -system.cpu0.dtb.write_accesses 5896407 # DTB write accesses +system.cpu0.dtb.perms_faults 635 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26094417 # DTB read accesses +system.cpu0.dtb.write_accesses 5897871 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31941563 # DTB hits -system.cpu0.dtb.misses 49524 # DTB misses -system.cpu0.dtb.accesses 31991087 # DTB accesses -system.cpu0.itb.inst_hits 6108612 # ITB inst hits -system.cpu0.itb.inst_misses 7590 # ITB inst misses +system.cpu0.dtb.hits 31942812 # DTB hits +system.cpu0.dtb.misses 49476 # DTB misses +system.cpu0.dtb.accesses 31992288 # DTB accesses +system.cpu0.itb.inst_hits 6107608 # ITB inst hits +system.cpu0.itb.inst_misses 7459 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2620 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1574 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1567 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6116202 # ITB inst accesses -system.cpu0.itb.hits 6108612 # DTB hits -system.cpu0.itb.misses 7590 # DTB misses -system.cpu0.itb.accesses 6116202 # DTB accesses -system.cpu0.numCycles 239083473 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6115067 # ITB inst accesses +system.cpu0.itb.hits 6107608 # DTB hits +system.cpu0.itb.misses 7459 # DTB misses +system.cpu0.itb.accesses 6115067 # DTB accesses +system.cpu0.numCycles 239065725 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15485568 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47808985 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7614306 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4782501 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10601732 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2558486 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 88790 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49524477 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1650 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 49879 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101149 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 238 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6106475 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 397023 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3536 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77625046 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.761902 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119269 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15475182 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47810378 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7613725 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4783241 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10599303 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2556412 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 92588 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49524214 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1680 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 51259 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101215 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6105640 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 396425 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3088 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77615764 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.762044 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119690 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67030834 86.35% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 688188 0.89% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 885369 1.14% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1227712 1.58% 89.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1142460 1.47% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 576598 0.74% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1323002 1.70% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 397300 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4353583 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67024086 86.35% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 687549 0.89% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 884780 1.14% 88.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1227446 1.58% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1139052 1.47% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 576391 0.74% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1322616 1.70% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 397461 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4356383 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77625046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 77615764 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.199968 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16533020 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49254882 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9604301 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 549145 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1681530 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1023916 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90477 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56278023 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 301850 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1681530 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17466172 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18987810 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27019642 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9149380 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3318436 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53462165 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13485 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 622165 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2153440 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 547 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55626962 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243359254 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243311426 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47828 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40393377 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15233585 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429285 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381212 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6745205 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10341737 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6773194 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1063883 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1311451 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49606690 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1043899 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63171257 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 95885 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10502922 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26495317 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 267486 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77625046 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.813800 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519198 # Number of insts issued each cycle +system.cpu0.fetch.rate 0.199988 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16521961 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49260251 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9602479 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 548826 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1680126 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1023427 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90450 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56271590 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 301516 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1680126 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17454704 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18993172 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27018669 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9147780 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3319243 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53454491 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13507 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 621630 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2155035 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 566 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55623215 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243327513 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243280007 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47506 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40387894 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15235321 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429274 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381163 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6745844 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10343403 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6774259 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1062911 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1310407 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49609262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1043693 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63170275 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 95774 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10510467 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26507766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 267313 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77615764 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.813885 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519252 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54791410 70.58% 70.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7205110 9.28% 79.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3690427 4.75% 84.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3148985 4.06% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6276259 8.09% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1405987 1.81% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 810578 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 230421 0.30% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65869 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54780189 70.58% 70.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7210578 9.29% 79.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3685843 4.75% 84.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3149398 4.06% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6278761 8.09% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1404530 1.81% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 809241 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 231115 0.30% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 66109 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77625046 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77615764 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29841 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29823 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available @@ -798,13 +810,13 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4229016 94.75% 95.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 204408 4.58% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4228133 94.76% 95.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 204148 4.58% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195533 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29939610 47.39% 47.70% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46892 0.07% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195616 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29937335 47.39% 47.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46928 0.07% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued @@ -817,485 +829,485 @@ system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Ty system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1207 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1205 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26772486 42.38% 90.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6215505 9.84% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26771956 42.38% 90.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6217218 9.84% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63171257 # Type of FU issued -system.cpu0.iq.rate 0.264223 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4463267 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070653 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208563844 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61162491 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44139446 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12207 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6555 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5480 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67432539 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6452 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 322060 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63170275 # Type of FU issued +system.cpu0.iq.rate 0.264238 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4462107 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070636 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208551330 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61172484 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44142185 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12154 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6481 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5464 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67430354 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6412 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 323195 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2267012 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3473 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16117 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 886206 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2268860 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3534 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16121 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 886667 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17168110 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367587 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17166750 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367684 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1681530 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14225625 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 233605 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50767973 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 106118 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10341737 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6773194 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 742853 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56514 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3354 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16117 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186814 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 146956 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 333770 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62000418 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26414197 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1170839 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1680126 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14230285 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 233349 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50770143 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105944 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10343403 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6774259 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 742754 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56167 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3335 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16121 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186307 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 146952 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 333259 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62002420 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26414016 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1167855 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117384 # number of nop insts executed -system.cpu0.iew.exec_refs 32572588 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6026978 # Number of branches executed -system.cpu0.iew.exec_stores 6158391 # Number of stores executed -system.cpu0.iew.exec_rate 0.259325 # Inst execution rate -system.cpu0.iew.wb_sent 61472286 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44144926 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24307807 # num instructions producing a value -system.cpu0.iew.wb_consumers 44674584 # num instructions consuming a value +system.cpu0.iew.exec_nop 117188 # number of nop insts executed +system.cpu0.iew.exec_refs 32573974 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6027717 # Number of branches executed +system.cpu0.iew.exec_stores 6159958 # Number of stores executed +system.cpu0.iew.exec_rate 0.259353 # Inst execution rate +system.cpu0.iew.wb_sent 61473665 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44147649 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24301400 # num instructions producing a value +system.cpu0.iew.wb_consumers 44653762 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184642 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544108 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184667 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544218 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10350620 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 776413 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 290797 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75943516 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.525572 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.508217 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10356873 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 776380 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 290234 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75935638 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.525589 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.508198 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61731521 81.29% 81.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6903711 9.09% 90.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2039504 2.69% 93.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1132941 1.49% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1032773 1.36% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 549051 0.72% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 702703 0.93% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 370837 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1480475 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61722766 81.28% 81.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6904437 9.09% 90.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2039889 2.69% 93.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1134781 1.49% 94.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1032872 1.36% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 547307 0.72% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 702356 0.92% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 369637 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1481593 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75943516 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31268406 # Number of instructions committed -system.cpu0.commit.committedOps 39913766 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75935638 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31265183 # Number of instructions committed +system.cpu0.commit.committedOps 39910920 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13961713 # Number of memory references committed -system.cpu0.commit.loads 8074725 # Number of loads committed -system.cpu0.commit.membars 212370 # Number of memory barriers committed -system.cpu0.commit.branches 5203416 # Number of branches committed +system.cpu0.commit.refs 13962135 # Number of memory references committed +system.cpu0.commit.loads 8074543 # Number of loads committed +system.cpu0.commit.membars 212305 # Number of memory barriers committed +system.cpu0.commit.branches 5202337 # Number of branches committed system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35263906 # Number of committed integer instructions. -system.cpu0.commit.function_calls 513958 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1480475 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 35261936 # Number of committed integer instructions. +system.cpu0.commit.function_calls 513908 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1481593 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123750130 # The number of ROB reads -system.cpu0.rob.rob_writes 102252787 # The number of ROB writes -system.cpu0.timesIdled 884124 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161458427 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289647904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31189179 # Number of Instructions Simulated -system.cpu0.committedOps 39834539 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31189179 # Number of Instructions Simulated -system.cpu0.cpi 7.665590 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.665590 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130453 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130453 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280633966 # number of integer regfile reads -system.cpu0.int_regfile_writes 45420954 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22760 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19830 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15480243 # number of misc regfile reads -system.cpu0.misc_regfile_writes 429707 # number of misc regfile writes -system.cpu0.icache.replacements 984233 # number of replacements -system.cpu0.icache.tagsinuse 511.604349 # Cycle average of tags in use -system.cpu0.icache.total_refs 11036411 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984745 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.207380 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123744681 # The number of ROB reads +system.cpu0.rob.rob_writes 102258102 # The number of ROB writes +system.cpu0.timesIdled 883709 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161449961 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289675923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31185911 # Number of Instructions Simulated +system.cpu0.committedOps 39831648 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31185911 # Number of Instructions Simulated +system.cpu0.cpi 7.665825 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.665825 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130449 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130449 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 280645626 # number of integer regfile reads +system.cpu0.int_regfile_writes 45419186 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22697 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15480369 # number of misc regfile reads +system.cpu0.misc_regfile_writes 429671 # number of misc regfile writes +system.cpu0.icache.replacements 983987 # number of replacements +system.cpu0.icache.tagsinuse 511.561827 # Cycle average of tags in use +system.cpu0.icache.total_refs 11034736 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984499 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.208479 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.507188 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 155.097161 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.696303 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.302924 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5565457 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5470954 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11036411 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5565457 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5470954 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11036411 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5565457 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5470954 # number of overall hits -system.cpu0.icache.overall_hits::total 11036411 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 540893 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 524443 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065336 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 540893 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 524443 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065336 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 540893 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 524443 # number of overall misses -system.cpu0.icache.overall_misses::total 1065336 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7322738992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6974356493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14297095485 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7322738992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6974356493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14297095485 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7322738992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6974356493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14297095485 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6106350 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995397 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12101747 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6106350 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5995397 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12101747 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6106350 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5995397 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12101747 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088579 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087474 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.088032 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088579 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087474 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.088032 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088579 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087474 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.088032 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13538.239526 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13298.597737 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13420.268803 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13420.268803 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13420.268803 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4718 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 357.606132 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 153.955695 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.698449 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.300695 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5565566 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5469170 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11034736 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5565566 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5469170 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11034736 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5565566 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5469170 # number of overall hits +system.cpu0.icache.overall_hits::total 11034736 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 539949 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 524997 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1064946 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 539949 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 524997 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1064946 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 539949 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 524997 # number of overall misses +system.cpu0.icache.overall_misses::total 1064946 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7306962994 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6971237994 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14278200988 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7306962994 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6971237994 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14278200988 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7306962994 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6971237994 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14278200988 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6105515 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5994167 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12099682 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6105515 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5994167 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12099682 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6105515 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5994167 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12099682 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088436 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087585 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.088014 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088436 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087585 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.088014 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088436 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087585 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.088014 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13532.691039 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13278.624438 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13407.441305 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13407.441305 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13407.441305 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4578 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 353 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 340 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.365439 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.464706 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41212 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39352 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80564 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41212 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39352 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80564 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41212 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39352 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80564 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 499681 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485091 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984772 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 499681 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 485091 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984772 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 499681 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 485091 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5972321992 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5682978994 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11655300986 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5972321992 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5682978994 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11655300986 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5972321992 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5682978994 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11655300986 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41021 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39404 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 80425 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41021 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39404 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80425 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41021 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39404 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 80425 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 498928 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485593 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984521 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 498928 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 485593 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984521 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 498928 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 485593 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984521 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5964947994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5687451995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11652399989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5964947994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5687451995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11652399989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5964947994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5687451995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11652399989 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081374 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.081374 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.081374 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.532475 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081368 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081368 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.081368 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.603292 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.603292 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.603292 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643981 # number of replacements +system.cpu0.dcache.replacements 643944 # number of replacements system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21533340 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644493 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.411286 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 21531615 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 644456 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.410528 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 320.784691 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 191.208024 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.626533 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.373453 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 318.816885 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 193.175830 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.622689 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.377297 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7106515 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6670987 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13777502 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3768669 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3492995 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261664 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125802 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117658 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243460 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127804 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119816 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247620 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10875184 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10163982 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21039166 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10875184 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10163982 # number of overall hits -system.cpu0.dcache.overall_hits::total 21039166 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 435450 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 315528 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 750978 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1386539 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1574618 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2961157 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6834 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6765 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1821989 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1890146 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3712135 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1821989 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1890146 # number of overall misses -system.cpu0.dcache.overall_misses::total 3712135 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6465601500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4868577500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11334179000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52482898858 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 61975315789 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114458214647 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92223500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94082500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 186306000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 65000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 117000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 58948500358 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66843893289 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125792393647 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 58948500358 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66843893289 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125792393647 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7541965 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6986515 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14528480 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5155208 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5067613 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222821 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132636 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124423 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257059 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127809 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119820 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247629 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12697173 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12054128 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24751301 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12697173 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12054128 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24751301 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057737 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045162 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051690 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.268959 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310722 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289661 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051524 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054371 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052902 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000039 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000033 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000036 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143496 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156805 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149977 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143496 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156805 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149977 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14848.091629 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15429.938072 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.557971 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37851.729276 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39358.952958 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38653.207056 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13494.805385 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13907.243163 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13699.977940 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_hits::cpu0.data 7106399 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6669591 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13775990 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3768165 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3493394 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261559 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125825 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117550 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243375 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127797 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119821 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247618 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10874564 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10162985 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21037549 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10874564 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10162985 # number of overall hits +system.cpu0.dcache.overall_hits::total 21037549 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 435409 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 315775 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 751184 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1387586 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1573694 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2961280 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6805 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6784 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13589 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1822995 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1889469 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3712464 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1822995 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1889469 # number of overall misses +system.cpu0.dcache.overall_misses::total 3712464 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6464424000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4870396500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11334820500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52533360348 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 61938473792 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114471834140 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92175500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94175500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 186351000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 168000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 58997784348 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 66808870292 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 125806654640 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 58997784348 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 66808870292 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 125806654640 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7541808 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6985366 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14527174 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5155751 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5067088 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10222839 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132630 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124334 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256964 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127803 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119827 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247630 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12697559 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12052454 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24750013 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12697559 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12052454 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24750013 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057733 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045205 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051709 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269134 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310572 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289673 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051308 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054563 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052883 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000047 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000050 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143571 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156770 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149998 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143571 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156770 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149998 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14846.785436 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15423.629166 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15089.273068 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37859.534723 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39358.651550 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38656.200744 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13545.260838 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13882.001769 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13713.371109 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32353.927690 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35364.407453 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33886.804668 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32353.927690 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35364.407453 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33886.804668 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 35336 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 15995 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3561 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 266 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.923055 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 60.131579 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32363.108153 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35358.542687 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33887.642989 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32363.108153 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35358.542687 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33887.642989 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 35225 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 16625 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3569 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 263 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.869711 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 63.212928 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608382 # number of writebacks -system.cpu0.dcache.writebacks::total 608382 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 221746 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 143011 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 364757 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1267305 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1444859 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2712164 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 688 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 688 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1376 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1489051 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1587870 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3076921 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1489051 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1587870 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3076921 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213704 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172517 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386221 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119234 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129759 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248993 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6146 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6077 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12223 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 332938 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 302276 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635214 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 332938 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 302276 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635214 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2899504500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2321074000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5220578500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3969032491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4493255436 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8462287927 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71687000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73644500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145331500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 55000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 99000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6868536991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6814329436 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13682866427 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6868536991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6814329436 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13682866427 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91958825500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90402409000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361234500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14888911816 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18625662995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33514574811 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 608440 # number of writebacks +system.cpu0.dcache.writebacks::total 608440 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 221787 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 143125 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 364912 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1268338 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1444026 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2712364 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 692 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 696 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1388 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1490125 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1587151 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3077276 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1490125 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1587151 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3077276 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213622 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172650 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386272 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119248 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129668 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248916 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6113 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6088 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12201 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 332870 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 302318 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635188 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 332870 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 302318 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635188 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2899035000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2323789000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5222824000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3973939486 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4489804935 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8463744421 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71655500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73661500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 144000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6872974486 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6813593935 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13686568421 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6872974486 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6813593935 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13686568421 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91950216500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90410818500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361035000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14891141407 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18622831131 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33513972538 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106847737316 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109028071995 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875809311 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028335 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024693 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026584 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106841357907 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109033649631 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875007538 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028325 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024716 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026590 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025606 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046337 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048841 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047549 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000033 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000036 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for demand accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025590 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046091 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047481 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000047 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.025664 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.025664 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13567.853199 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13454.175531 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13517.075716 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33287.757611 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34627.697778 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33986.047507 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.009112 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12118.561790 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.002454 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13570.863488 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13459.536635 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.104300 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33324.999044 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34625.388955 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.412143 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11721.822346 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12099.457950 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.253258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1310,154 +1322,154 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7038093 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5643597 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 344397 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4629014 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3810883 # Number of BTB hits +system.cpu1.branchPred.lookups 7039242 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5645782 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 344121 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4649860 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3812908 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 82.326020 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 671158 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34749 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 82.000490 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 671568 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34742 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25308103 # DTB read hits -system.cpu1.dtb.read_misses 36468 # DTB read misses -system.cpu1.dtb.write_hits 5825949 # DTB write hits -system.cpu1.dtb.write_misses 9352 # DTB write misses +system.cpu1.dtb.read_hits 25307959 # DTB read hits +system.cpu1.dtb.read_misses 36376 # DTB read misses +system.cpu1.dtb.write_hits 5825723 # DTB write hits +system.cpu1.dtb.write_misses 9311 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1257 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5515 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1387 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 652 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25344571 # DTB read accesses -system.cpu1.dtb.write_accesses 5835301 # DTB write accesses +system.cpu1.dtb.perms_faults 651 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25344335 # DTB read accesses +system.cpu1.dtb.write_accesses 5835034 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31134052 # DTB hits -system.cpu1.dtb.misses 45820 # DTB misses -system.cpu1.dtb.accesses 31179872 # DTB accesses -system.cpu1.itb.inst_hits 5997509 # ITB inst hits -system.cpu1.itb.inst_misses 6989 # ITB inst misses +system.cpu1.dtb.hits 31133682 # DTB hits +system.cpu1.dtb.misses 45687 # DTB misses +system.cpu1.dtb.accesses 31179369 # DTB accesses +system.cpu1.itb.inst_hits 5996114 # ITB inst hits +system.cpu1.itb.inst_misses 6834 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2597 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2600 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1435 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6004498 # ITB inst accesses -system.cpu1.itb.hits 5997509 # DTB hits -system.cpu1.itb.misses 6989 # DTB misses -system.cpu1.itb.accesses 6004498 # DTB accesses -system.cpu1.numCycles 234155519 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6002948 # ITB inst accesses +system.cpu1.itb.hits 5996114 # DTB hits +system.cpu1.itb.misses 6834 # DTB misses +system.cpu1.itb.accesses 6002948 # DTB accesses +system.cpu1.numCycles 234172204 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15142136 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46597306 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7038093 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4482041 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10279188 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2613913 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 81086 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47501023 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2061 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 42896 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94668 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 141 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5995399 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 442650 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3270 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74933804 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773237 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.138568 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15150430 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46599302 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7039242 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4484476 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10276938 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2612454 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82512 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47518747 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2108 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42921 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94711 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 94 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5994168 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 443200 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2937 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74957939 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.773072 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.138667 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64662280 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 620375 0.83% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 831799 1.11% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1204715 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1045196 1.39% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 534648 0.71% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1368616 1.83% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351624 0.47% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4314551 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64688840 86.30% 86.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 619651 0.83% 87.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 831575 1.11% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1205005 1.61% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1040099 1.39% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 534718 0.71% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1368218 1.83% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 351871 0.47% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4317962 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74933804 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030057 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199002 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16155094 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47289878 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9321974 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 458622 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1706108 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 946431 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86032 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54867135 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286067 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1706108 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17091509 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18549403 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25716073 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8765190 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3103459 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51703267 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7138 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 482463 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2122538 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 91 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53752733 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237374868 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237332026 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42842 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37999603 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15753129 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 403463 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 357307 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6254395 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9847442 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6700780 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 890369 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1126759 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47663057 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 942444 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60816475 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81421 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10551432 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27971257 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236318 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74933804 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811603 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521433 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74957939 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030060 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.198996 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16159118 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47313522 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9319419 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 458702 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1705045 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 945660 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85957 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54861176 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 287371 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1705045 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17094797 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18547389 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25741637 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8764339 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3102678 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51699813 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7117 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 482642 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2122595 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 48 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53761457 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237355866 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237312988 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42878 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38005573 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15755883 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 403501 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 357316 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6247551 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9846699 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6699378 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 894839 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1124277 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47671789 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 942558 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60820762 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80974 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10554667 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27991193 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236389 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74957939 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.811399 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521506 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53188932 70.98% 70.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6663266 8.89% 79.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3530113 4.71% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2889463 3.86% 88.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6218055 8.30% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1440706 1.92% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 733706 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 209896 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59667 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53217841 71.00% 71.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6660852 8.89% 79.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3522155 4.70% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2891310 3.86% 88.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6221103 8.30% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1440067 1.92% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 734950 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210065 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59596 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74933804 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74957939 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24001 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24217 0.55% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available @@ -1486,13 +1498,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4142238 94.88% 95.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 199692 4.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4143294 94.86% 95.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200406 4.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 168133 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28440656 46.76% 47.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46730 0.08% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 168050 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28446121 46.77% 47.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46643 0.08% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued @@ -1505,129 +1517,129 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 904 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 906 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26040768 42.82% 89.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6119264 10.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26040786 42.82% 89.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6118237 10.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60816475 # Type of FU issued +system.cpu1.iq.FU_type_0::total 60820762 # Type of FU issued system.cpu1.iq.rate 0.259727 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4365932 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071789 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201049061 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59165079 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41785793 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10680 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5951 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65008639 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5635 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 303573 # Number of loads that had data forwarded from stores +system.cpu1.iq.fu_busy_cnt 4367918 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071816 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201083162 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59177242 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41793523 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10683 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5961 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4808 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65014989 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5641 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 303389 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2266828 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3041 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14605 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 855166 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2265840 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3135 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14672 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 854347 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16935844 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 457097 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16937147 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 456872 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1706108 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13962333 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229984 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48711452 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98533 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9847442 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6700780 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 669329 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49837 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3707 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14605 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 166001 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133612 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 299613 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59448141 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25635797 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1368334 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1705045 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13964953 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 229910 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48720174 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98231 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9846699 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6699378 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 669323 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49676 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3736 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14672 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 165888 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133425 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 299313 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59456626 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25635805 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1364136 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105951 # number of nop insts executed -system.cpu1.iew.exec_refs 31702689 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5524822 # Number of branches executed -system.cpu1.iew.exec_stores 6066892 # Number of stores executed -system.cpu1.iew.exec_rate 0.253883 # Inst execution rate -system.cpu1.iew.wb_sent 58868959 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41790607 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22765083 # num instructions producing a value -system.cpu1.iew.wb_consumers 41748877 # num instructions consuming a value +system.cpu1.iew.exec_nop 105827 # number of nop insts executed +system.cpu1.iew.exec_refs 31702395 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5527346 # Number of branches executed +system.cpu1.iew.exec_stores 6066590 # Number of stores executed +system.cpu1.iew.exec_rate 0.253901 # Inst execution rate +system.cpu1.iew.wb_sent 58878116 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41798331 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22764679 # num instructions producing a value +system.cpu1.iew.wb_consumers 41753721 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178474 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545286 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178494 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545213 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10475750 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 706126 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 259614 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73227696 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516730 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.497193 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10481198 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 706169 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 259373 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73252894 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.516596 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.497283 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59700930 81.53% 81.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6668134 9.11% 90.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1908648 2.61% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1011673 1.38% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 958934 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 524760 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 701730 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 374533 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1378354 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59734394 81.55% 81.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6658117 9.09% 90.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1908666 2.61% 93.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1009766 1.38% 94.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 959602 1.31% 95.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 525640 0.72% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 705032 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 372807 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1378870 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73227696 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29191864 # Number of instructions committed -system.cpu1.commit.committedOps 37838928 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73252894 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29195437 # Number of instructions committed +system.cpu1.commit.committedOps 37842156 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13426228 # Number of memory references committed -system.cpu1.commit.loads 7580614 # Number of loads committed -system.cpu1.commit.membars 191280 # Number of memory barriers committed -system.cpu1.commit.branches 4758264 # Number of branches committed +system.cpu1.commit.refs 13425890 # Number of memory references committed +system.cpu1.commit.loads 7580859 # Number of loads committed +system.cpu1.commit.membars 191347 # Number of memory barriers committed +system.cpu1.commit.branches 4759387 # Number of branches committed system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33593707 # Number of committed integer instructions. -system.cpu1.commit.function_calls 477362 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1378354 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 33596023 # Number of committed integer instructions. +system.cpu1.commit.function_calls 477418 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1378870 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119292034 # The number of ROB reads -system.cpu1.rob.rob_writes 98387822 # The number of ROB writes -system.cpu1.timesIdled 873010 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159221715 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285865988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29120710 # Number of Instructions Simulated -system.cpu1.committedOps 37767774 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29120710 # Number of Instructions Simulated -system.cpu1.cpi 8.040859 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.040859 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124365 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124365 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269346342 # number of integer regfile reads -system.cpu1.int_regfile_writes 42878504 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22102 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14810651 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402789 # number of misc regfile writes +system.cpu1.rob.rob_reads 119325211 # The number of ROB reads +system.cpu1.rob.rob_writes 98404070 # The number of ROB writes +system.cpu1.timesIdled 873125 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159214265 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285839594 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29124328 # Number of Instructions Simulated +system.cpu1.committedOps 37771047 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29124328 # Number of Instructions Simulated +system.cpu1.cpi 8.040433 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.040433 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124371 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124371 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 269378788 # number of integer regfile reads +system.cpu1.int_regfile_writes 42887039 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22080 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19702 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14812812 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402828 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1642,17 +1654,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192717579972 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192717579972 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192668399444 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192668399444 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83049 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83052 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 7f424ed80..33629e29f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -16,7 +16,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -516,7 +516,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -1275,7 +1275,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1295,7 +1295,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1463,6 +1463,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 04e937e47..bf52a9da4 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:25:23 -gem5 started Feb 13 2013 18:24:23 -gem5 executing on u200540-lin +gem5 compiled Mar 3 2013 21:19:51 +gem5 started Mar 4 2013 00:22:16 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5140860798000 because m5_exit instruction encountered +Exiting @ tick 5132857897000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 171e4af9f..5db5edca0 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.136865 # Number of seconds simulated -sim_ticks 5136864535500 # Number of ticks simulated -final_tick 5136864535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.132858 # Number of seconds simulated +sim_ticks 5132857897000 # Number of ticks simulated +final_tick 5132857897000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199949 # Simulator instruction rate (inst/s) -host_op_rate 395248 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2517891877 # Simulator tick rate (ticks/s) -host_mem_usage 755196 # Number of bytes of host memory used -host_seconds 2040.15 # Real time elapsed on the host -sim_insts 407925588 # Number of instructions simulated -sim_ops 806363480 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2498048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory +host_inst_rate 156379 # Simulator instruction rate (inst/s) +host_op_rate 309121 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1967786651 # Simulator tick rate (ticks/s) +host_mem_usage 752412 # Number of bytes of host memory used +host_seconds 2608.44 # Real time elapsed on the host +sim_insts 407905700 # Number of instructions simulated +sim_ops 806325509 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2501312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1077760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10804608 # Number of bytes read from this memory -system.physmem.bytes_read::total 14383936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1077760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1077760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9566528 # Number of bytes written to this memory -system.physmem.bytes_written::total 9566528 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 39032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1078144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10788736 # Number of bytes read from this memory +system.physmem.bytes_read::total 14371776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1078144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1078144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9560192 # Number of bytes written to this memory +system.physmem.bytes_written::total 9560192 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 39083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 50 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16840 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168822 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224749 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149477 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149477 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 486298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168574 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224559 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149378 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149378 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 487314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 623 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 209809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2103347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2800139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 209809 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 209809 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1862328 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1862328 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1862328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 486298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2101896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2799956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210048 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210048 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1862548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1862548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1862548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 487314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 209809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2103347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4662468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 224749 # Total number of read requests seen -system.physmem.writeReqs 149477 # Total number of write requests seen -system.physmem.cpureqs 378758 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14383936 # Total number of bytes read from memory -system.physmem.bytesWritten 9566528 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14383936 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9566528 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3970 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13038 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13174 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13158 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13285 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12660 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15923 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9005 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8432 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8529 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8903 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11692 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 9007 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8684 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8693 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 11170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8382 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8108 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8695 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 11192 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 210048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2101896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4662504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 224559 # Total number of read requests seen +system.physmem.writeReqs 149378 # Total number of write requests seen +system.physmem.cpureqs 379116 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14371776 # Total number of bytes read from memory +system.physmem.bytesWritten 9560192 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14371776 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9560192 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 86 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3988 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12988 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13113 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16256 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16230 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13981 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13311 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13328 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 15635 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13184 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12667 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13446 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15958 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9012 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8453 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8452 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 11545 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8811 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8570 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8847 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 11675 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 9048 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8676 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8758 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 11176 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8087 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8705 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 11209 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 562 # Number of times wr buffer was full causing retry -system.physmem.totGap 5136864483000 # Total gap between requests +system.physmem.numWrRetry 1191 # Number of times wr buffer was full causing retry +system.physmem.totGap 5132857844500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 224749 # Categorize read packet sizes +system.physmem.readPktSize::6 224559 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 149477 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 173174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 19685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1773 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149378 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 172944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 19784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3483 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3003 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1768 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 386 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -136,46 +136,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.totQLat 4764271250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9277483750 # Sum of mem lat for all requests -system.physmem.totBusLat 1123260000 # Total cycles spent in databus access -system.physmem.totBankLat 3389952500 # Total cycles spent in bank access -system.physmem.avgQLat 21207.34 # Average queueing delay per request -system.physmem.avgBankLat 15089.79 # Average bank access latency per request +system.physmem.wrQLenPdf::0 5358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.totQLat 4795272000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9305637000 # Sum of mem lat for all requests +system.physmem.totBusLat 1122365000 # Total cycles spent in databus access +system.physmem.totBankLat 3388000000 # Total cycles spent in bank access +system.physmem.avgQLat 21362.36 # Average queueing delay per request +system.physmem.avgBankLat 15093.13 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41297.13 # Average memory access latency +system.physmem.avgMemAccLat 41455.48 # Average memory access latency system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s @@ -183,21 +183,21 @@ system.physmem.avgConsumedWrBW 1.86 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.02 # Average write queue length over time -system.physmem.readRowHits 193727 # Number of row buffer hits during reads -system.physmem.writeRowHits 105780 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes -system.physmem.avgGap 13726637.07 # Average gap between requests +system.physmem.avgWrQLen 11.03 # Average write queue length over time +system.physmem.readRowHits 193515 # Number of row buffer hits during reads +system.physmem.writeRowHits 105640 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.72 # Row buffer hit rate for writes +system.physmem.avgGap 13726531.06 # Average gap between requests system.iocache.replacements 47576 # number of replacements -system.iocache.tagsinuse 0.116322 # Cycle average of tags in use +system.iocache.tagsinuse 0.103924 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.116322 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy +system.iocache.occ_blocks::pc.south_bridge.ide 0.103924 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006495 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006495 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -206,14 +206,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47631 system.iocache.demand_misses::total 47631 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151593932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 151593932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10023192160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10023192160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10174786092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10174786092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10174786092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10174786092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146639932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 146639932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10056560160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10056560160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10203200092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10203200092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10203200092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10203200092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -230,19 +230,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166403.877058 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 166403.877058 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214537.503425 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 214537.503425 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 213616.890093 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 213616.890093 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 136470 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160965.896817 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160965.896817 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215251.715753 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 215251.715753 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214213.434360 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 214213.434360 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214213.434360 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 214213.434360 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 137627 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12410 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12509 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.996777 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.002238 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -256,14 +256,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104200712 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104200712 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7592410619 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7592410619 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7696611331 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7696611331 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99246962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 99246962 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7625786368 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7625786368 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7725033330 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7725033330 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7725033330 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7725033330 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114380.583974 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 114380.583974 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162508.788934 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 162508.788934 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108942.878156 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 108942.878156 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163223.167123 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 163223.167123 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162184.991497 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 162184.991497 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162184.991497 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 162184.991497 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -293,142 +293,142 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 86198193 # Number of BP lookups -system.cpu.branchPred.condPredicted 86198193 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1106234 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81290548 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79213904 # Number of BTB hits +system.cpu.branchPred.lookups 86194611 # Number of BP lookups +system.cpu.branchPred.condPredicted 86194611 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1105724 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 81284951 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79210874 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.445405 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 97.448387 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.numCycles 448153841 # number of cpu cycles simulated +system.cpu.numCycles 448157181 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27415171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 425937394 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86198193 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79213904 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163576958 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4698498 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 117961 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63103393 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 51299 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9010068 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 483485 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3126 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257855511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.261045 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418033 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27411589 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 425916361 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86194611 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79210874 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163569758 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4698258 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 127091 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63100705 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36134 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 51634 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 488 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9006921 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 482292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2784 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257851520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.260962 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418035 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94705411 36.73% 36.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1566235 0.61% 37.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71918028 27.89% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 935930 0.36% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1598963 0.62% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2419267 0.94% 67.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1070398 0.42% 67.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1376464 0.53% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82264815 31.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94708741 36.73% 36.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1565189 0.61% 37.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71915500 27.89% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 936812 0.36% 65.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1597915 0.62% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2418163 0.94% 67.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1071060 0.42% 67.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1376608 0.53% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82261532 31.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257855511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192341 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.950427 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31132857 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60536501 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159370274 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3261936 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3553943 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 837748670 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 951 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3553943 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33869883 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37385632 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11021591 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159568277 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12456185 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834115262 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19668 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5867494 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4754545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8312 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 995635482 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1810665967 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1810665163 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 804 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964341342 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31294133 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 459159 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 467055 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28798095 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17056943 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10123506 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1248285 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 987203 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 827998215 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1251183 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823066756 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 148002 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21984557 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33441202 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 198541 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257855511 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.191969 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.384014 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257851520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192331 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.950373 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31130056 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60542452 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159362996 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3261895 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3554121 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 837710983 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 948 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3554121 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33866246 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37401594 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11010183 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159560886 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12458490 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834077749 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19680 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5867270 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4756403 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8649 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 995584301 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1810575684 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1810574876 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 808 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964290633 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31293661 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 458949 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 466891 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28798932 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17055930 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10122177 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1247187 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 990912 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 827964566 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1250540 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823033686 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 148209 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21990342 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33439565 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 197993 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257851520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.191890 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.384052 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71390186 27.69% 27.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15517919 6.02% 33.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10294138 3.99% 37.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7464826 2.89% 40.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75904474 29.44% 70.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3838948 1.49% 71.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72513480 28.12% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 779753 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 151787 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71392246 27.69% 27.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15523930 6.02% 33.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10289230 3.99% 37.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7461063 2.89% 40.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75902807 29.44% 70.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3840005 1.49% 71.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72510870 28.12% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 779318 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152051 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257855511 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257851520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 363612 34.06% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553162 51.82% 85.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150741 14.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 361997 33.96% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553138 51.89% 85.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150897 14.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 311137 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795540449 96.66% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 310952 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795510781 96.66% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued @@ -457,246 +457,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17836742 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9378428 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17835089 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9376864 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823066756 # Type of FU issued -system.cpu.iq.rate 1.836572 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1067515 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905334904 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851243829 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818598323 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 260 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 368 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 823823020 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 114 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1639481 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823033686 # Type of FU issued +system.cpu.iq.rate 1.836484 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1066032 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001295 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905263509 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851215281 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818564848 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 272 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 382 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 823788636 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 130 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1638773 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3079539 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22701 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11520 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1710580 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3081166 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22705 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11479 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1710957 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932434 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12204 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932446 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12217 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3553943 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26124965 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2116869 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829249398 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 321104 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17056943 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10123506 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 718931 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1615774 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10404 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11520 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 649169 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 592997 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1242166 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821195112 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17426068 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1871643 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3554121 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26141117 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2116575 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829215106 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 320591 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17055930 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10122177 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 718653 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1615740 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10506 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11479 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 648838 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 592977 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1241815 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821161230 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17423630 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1872455 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26572625 # number of memory reference insts executed -system.cpu.iew.exec_branches 83197450 # Number of branches executed -system.cpu.iew.exec_stores 9146557 # Number of stores executed -system.cpu.iew.exec_rate 1.832396 # Inst execution rate -system.cpu.iew.wb_sent 820733466 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818598386 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639795417 # num instructions producing a value -system.cpu.iew.wb_consumers 1045555736 # num instructions consuming a value +system.cpu.iew.exec_refs 26568531 # number of memory reference insts executed +system.cpu.iew.exec_branches 83193011 # Number of branches executed +system.cpu.iew.exec_stores 9144901 # Number of stores executed +system.cpu.iew.exec_rate 1.832306 # Inst execution rate +system.cpu.iew.wb_sent 820700229 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818564922 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639778882 # num instructions producing a value +system.cpu.iew.wb_consumers 1045529467 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.826601 # insts written-back per cycle +system.cpu.iew.wb_rate 1.826513 # insts written-back per cycle system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22777543 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052640 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1110740 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254301568 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.170895 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.853974 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22781132 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052545 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1110334 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254297399 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.170797 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.853937 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82529406 32.45% 32.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11802979 4.64% 37.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3912644 1.54% 38.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74944166 29.47% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2437687 0.96% 69.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1481720 0.58% 69.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 940520 0.37% 70.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70919321 27.89% 97.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5333125 2.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82526547 32.45% 32.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11810769 4.64% 37.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3910269 1.54% 38.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74942576 29.47% 68.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2436425 0.96% 69.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1481605 0.58% 69.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 941054 0.37% 70.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70918807 27.89% 97.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5329347 2.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254301568 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407925588 # Number of instructions committed -system.cpu.commit.committedOps 806363480 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254297399 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407905700 # Number of instructions committed +system.cpu.commit.committedOps 806325509 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22390327 # Number of memory references committed -system.cpu.commit.loads 13977401 # Number of loads committed +system.cpu.commit.refs 22385981 # Number of memory references committed +system.cpu.commit.loads 13974761 # Number of loads committed system.cpu.commit.membars 473457 # Number of memory barriers committed -system.cpu.commit.branches 82191015 # Number of branches committed +system.cpu.commit.branches 82185695 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735304742 # Number of committed integer instructions. +system.cpu.commit.int_insts 735267209 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5333125 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5329347 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1078031216 # The number of ROB reads -system.cpu.rob.rob_writes 1661854677 # The number of ROB writes -system.cpu.timesIdled 1219790 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190298330 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9825572650 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407925588 # Number of Instructions Simulated -system.cpu.committedOps 806363480 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407925588 # Number of Instructions Simulated -system.cpu.cpi 1.098617 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.098617 # CPI: Total CPI of All Threads -system.cpu.ipc 0.910236 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.910236 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1506687590 # number of integer regfile reads -system.cpu.int_regfile_writes 976781809 # number of integer regfile writes -system.cpu.fp_regfile_reads 63 # number of floating regfile reads -system.cpu.misc_regfile_reads 264621583 # number of misc regfile reads -system.cpu.misc_regfile_writes 402234 # number of misc regfile writes -system.cpu.icache.replacements 1045798 # number of replacements -system.cpu.icache.tagsinuse 510.125014 # Cycle average of tags in use -system.cpu.icache.total_refs 7900747 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1046310 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.551058 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1077996488 # The number of ROB reads +system.cpu.rob.rob_writes 1661786087 # The number of ROB writes +system.cpu.timesIdled 1219722 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190305661 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9817556036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407905700 # Number of Instructions Simulated +system.cpu.committedOps 806325509 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407905700 # Number of Instructions Simulated +system.cpu.cpi 1.098678 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.098678 # CPI: Total CPI of All Threads +system.cpu.ipc 0.910184 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.910184 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1506617542 # number of integer regfile reads +system.cpu.int_regfile_writes 976738350 # number of integer regfile writes +system.cpu.fp_regfile_reads 74 # number of floating regfile reads +system.cpu.misc_regfile_reads 264608213 # number of misc regfile reads +system.cpu.misc_regfile_writes 402112 # number of misc regfile writes +system.cpu.icache.replacements 1045620 # number of replacements +system.cpu.icache.tagsinuse 510.123573 # Cycle average of tags in use +system.cpu.icache.total_refs 7898000 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1046132 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.549716 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.125014 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996338 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996338 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7900747 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7900747 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7900747 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7900747 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7900747 # number of overall hits -system.cpu.icache.overall_hits::total 7900747 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1109320 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1109320 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1109320 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1109320 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1109320 # number of overall misses -system.cpu.icache.overall_misses::total 1109320 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15268069493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15268069493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15268069493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15268069493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15268069493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15268069493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9010067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9010067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9010067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9010067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9010067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9010067 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123120 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123120 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123120 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123120 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123120 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123120 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13763.449224 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13763.449224 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13763.449224 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13763.449224 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 12508 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.123573 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996335 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996335 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7898000 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7898000 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7898000 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7898000 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7898000 # number of overall hits +system.cpu.icache.overall_hits::total 7898000 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1108918 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1108918 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1108918 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1108918 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1108918 # number of overall misses +system.cpu.icache.overall_misses::total 1108918 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15254848492 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15254848492 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15254848492 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15254848492 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15254848492 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15254848492 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9006918 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9006918 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9006918 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9006918 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9006918 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9006918 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123118 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123118 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123118 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123118 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123118 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123118 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13756.516255 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13756.516255 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13756.516255 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13756.516255 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13756.516255 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13756.516255 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 9824 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 293 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 296 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.689420 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.189189 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60685 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60685 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60685 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60685 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60685 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60685 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048635 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1048635 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1048635 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1048635 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1048635 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1048635 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12573562493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12573562493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12573562493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12573562493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12573562493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12573562493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116385 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116385 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116385 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11990.408954 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11990.408954 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60463 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60463 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60463 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60463 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60463 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60463 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048455 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1048455 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1048455 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1048455 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1048455 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1048455 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12565081992 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12565081992 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12565081992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12565081992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12565081992 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12565081992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116406 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116406 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116406 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11984.378912 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11984.378912 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11984.378912 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11984.378912 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11984.378912 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11984.378912 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9600 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.016014 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25681 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9614 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.671209 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5103990045500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.016014 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376001 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376001 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25689 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25689 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9450 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.008249 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 25808 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9463 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.727254 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5103990002500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.008249 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375516 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375516 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25828 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25828 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25691 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25691 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25691 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25691 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10488 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10488 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10488 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10488 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10488 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10488 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116654500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116654500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116654500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 116654500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116654500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 116654500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36177 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 36177 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25830 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25830 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25830 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25830 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10341 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10341 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10341 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10341 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10341 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10341 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 115658000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 115658000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 115658000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 115658000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 115658000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 115658000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36169 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 36169 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36179 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 36179 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36179 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 36179 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.289908 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.289908 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.289892 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.289892 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.289892 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.289892 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11122.663997 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11122.663997 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11122.663997 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11122.663997 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36171 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 36171 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36171 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 36171 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285908 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285908 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285892 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.285892 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285892 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.285892 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11184.411566 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11184.411566 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11184.411566 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11184.411566 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11184.411566 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11184.411566 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -705,78 +705,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1936 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1936 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10488 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10488 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10488 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10488 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10488 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10488 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 95678500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 95678500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 95678500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 95678500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 95678500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 95678500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.289908 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.289908 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.289892 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.289892 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9122.663997 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1982 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1982 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10341 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10341 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10341 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10341 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10341 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10341 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94976000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94976000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94976000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94976000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94976000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94976000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285908 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285908 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285892 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285892 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285892 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285892 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9184.411566 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9184.411566 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9184.411566 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 108181 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.959012 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 134869 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 108196 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.246525 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.replacements 109668 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.956689 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 133742 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109682 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.219361 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959012 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809938 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.809938 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134886 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 134886 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134886 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 134886 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134886 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 134886 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109218 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 109218 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109218 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 109218 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109218 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 109218 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1375116000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1375116000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1375116000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1375116000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1375116000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1375116000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244104 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 244104 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244104 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 244104 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244104 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 244104 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447424 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447424 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447424 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447424 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447424 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447424 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12590.561995 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12590.561995 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12590.561995 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12590.561995 # average overall miss latency +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.956689 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809793 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.809793 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 133765 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 133765 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 133765 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 133765 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 133765 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 133765 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110693 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110693 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110693 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110693 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110693 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110693 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1390562000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1390562000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1390562000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1390562000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1390562000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1390562000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244458 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 244458 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244458 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 244458 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244458 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 244458 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.452810 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.452810 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.452810 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.452810 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.452810 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.452810 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12562.330048 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12562.330048 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12562.330048 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12562.330048 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12562.330048 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12562.330048 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -785,146 +785,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35252 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35252 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109218 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109218 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109218 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 109218 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109218 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 109218 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1156680000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1156680000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1156680000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447424 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447424 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447424 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10590.561995 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35480 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35480 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110693 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110693 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110693 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110693 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110693 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110693 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1169176000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1169176000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1169176000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.452810 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.452810 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.452810 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.330048 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10562.330048 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10562.330048 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1660118 # number of replacements -system.cpu.dcache.tagsinuse 511.992206 # Cycle average of tags in use -system.cpu.dcache.total_refs 19078637 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1660630 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.488795 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1659150 # number of replacements +system.cpu.dcache.tagsinuse 511.992464 # Cycle average of tags in use +system.cpu.dcache.total_refs 19077771 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1659662 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.494974 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.992206 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.992464 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10987895 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10987895 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8085738 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8085738 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19073633 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19073633 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19073633 # number of overall hits -system.cpu.dcache.overall_hits::total 19073633 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2236252 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2236252 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317957 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317957 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2554209 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2554209 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2554209 # number of overall misses -system.cpu.dcache.overall_misses::total 2554209 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32134007500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32134007500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9664278994 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9664278994 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41798286494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41798286494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41798286494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41798286494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13224147 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13224147 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8403695 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8403695 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21627842 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21627842 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21627842 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21627842 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169104 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169104 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037835 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037835 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118098 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118098 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118098 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118098 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14369.582453 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14369.582453 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30394.924452 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30394.924452 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16364.473892 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16364.473892 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 400642 # number of cycles access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 10988579 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10988579 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8084208 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8084208 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19072787 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19072787 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19072787 # number of overall hits +system.cpu.dcache.overall_hits::total 19072787 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2233798 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2233798 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317777 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317777 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2551575 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2551575 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2551575 # number of overall misses +system.cpu.dcache.overall_misses::total 2551575 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32133763000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32133763000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9654013491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9654013491 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41787776491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41787776491 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41787776491 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41787776491 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13222377 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13222377 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8401985 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8401985 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21624362 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21624362 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21624362 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21624362 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168941 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.168941 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037822 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037822 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117995 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117995 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117995 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117995 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14385.259097 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14385.259097 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30379.837090 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30379.837090 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16377.247971 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16377.247971 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16377.247971 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16377.247971 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 403205 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42486 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42533 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.429977 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.479816 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1561388 # number of writebacks -system.cpu.dcache.writebacks::total 1561388 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864027 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 864027 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25006 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25006 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 889033 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 889033 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 889033 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 889033 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1372225 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1372225 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292951 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 292951 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1665176 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1665176 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1665176 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1665176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17481793000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17481793000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8820305494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8820305494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26302098494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26302098494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26302098494 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26302098494 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296698500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296698500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470686500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470686500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767385000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767385000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103767 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103767 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034860 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034860 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076992 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076992 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076992 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12739.742389 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12739.742389 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30108.466925 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30108.466925 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15795.386490 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15795.386490 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15795.386490 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15795.386490 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1560680 # number of writebacks +system.cpu.dcache.writebacks::total 1560680 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862352 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 862352 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25015 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25015 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 887367 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 887367 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 887367 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 887367 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371446 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1371446 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292762 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 292762 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1664208 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1664208 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1664208 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1664208 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17485386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17485386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8810445491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8810445491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26295831991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26295831991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26295831991 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26295831991 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296686000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296686000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470456500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470456500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767142500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767142500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103722 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103722 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076960 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076960 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076960 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076960 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12749.598963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12749.598963 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30094.224971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30094.224971 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15800.808547 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15800.808547 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15800.808547 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15800.808547 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -932,141 +932,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 113561 # number of replacements -system.cpu.l2cache.tagsinuse 64842.483679 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3930962 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 177626 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.130555 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 113397 # number of replacements +system.cpu.l2cache.tagsinuse 64842.962658 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3927368 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 177482 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.128261 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50033.446344 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.888296 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133449 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3280.677554 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11517.338036 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.763450 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 50042.897281 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.875640 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.131992 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3274.977227 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11514.080519 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.763594 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.050059 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.175741 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989418 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102246 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8058 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1029420 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1334149 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2473873 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1598576 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1598576 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 345 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 345 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 156103 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 156103 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 102246 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 8058 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1029420 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1490252 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2629976 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 102246 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 8058 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1029420 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1490252 # number of overall hits -system.cpu.l2cache.overall_hits::total 2629976 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 49 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.049972 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.175691 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989425 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 103288 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8019 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1029235 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1333401 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2473943 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1598142 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1598142 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 335 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 335 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 156168 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 156168 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 103288 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 8019 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1029235 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1489569 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2630111 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 103288 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 8019 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1029235 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1489569 # number of overall hits +system.cpu.l2cache.overall_hits::total 2630111 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 50 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16841 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 36881 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 53777 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3693 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3693 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 132888 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 132888 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 49 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16847 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 36871 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 53774 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3714 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3714 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 132646 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 132646 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 50 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16841 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169769 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 186665 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 49 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 16847 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169517 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 186420 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 50 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16841 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169769 # number of overall misses -system.cpu.l2cache.overall_misses::total 186665 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6312000 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 16847 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169517 # number of overall misses +system.cpu.l2cache.overall_misses::total 186420 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6252000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1177562500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2538376499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3722640499 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16930000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16930000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6874050999 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6874050999 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6312000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1171120500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2550395499 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3728157499 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17029000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 17029000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6863407500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6863407500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6252000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1177562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9412427498 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10596691498 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6312000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1171120500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9413802999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10591564999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6252000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1177562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9412427498 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10596691498 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 102295 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8064 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1046261 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1371030 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2527650 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1598576 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1598576 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4038 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4038 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288991 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288991 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 102295 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 8064 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1046261 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1660021 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2816641 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 102295 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 8064 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1046261 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1660021 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2816641 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000479 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000744 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016096 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026900 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021275 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.914562 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.914562 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459834 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.459834 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000479 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000744 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016096 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102269 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.066272 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000479 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000744 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016096 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102269 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.066272 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 128816.326531 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 1171120500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9413802999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10591564999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103338 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8025 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1046082 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1370272 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2527717 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1598142 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1598142 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4049 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4049 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 288814 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 288814 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103338 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 8025 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1046082 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1659086 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2816531 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103338 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 8025 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1046082 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1659086 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2816531 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000748 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016105 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026908 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021274 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.917264 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.917264 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459278 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.459278 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000748 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016105 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102175 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.066188 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000748 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016105 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102175 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.066188 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 125040 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69922.362093 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68826.129959 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69223.655076 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4584.348768 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4584.348768 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51728.154529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51728.154529 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 128816.326531 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69515.076868 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69170.771040 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69330.113047 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4585.083468 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4585.083468 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51742.287743 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51742.287743 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 125040 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69922.362093 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55442.557228 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56768.497029 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 128816.326531 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69515.076868 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55533.091071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56815.604544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 125040 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69922.362093 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55442.557228 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56768.497029 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69515.076868 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55533.091071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56815.604544 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1075,8 +1075,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102810 # number of writebacks -system.cpu.l2cache.writebacks::total 102810 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 102711 # number of writebacks +system.cpu.l2cache.writebacks::total 102711 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits @@ -1086,88 +1086,88 @@ system.cpu.l2cache.demand_mshr_hits::total 2 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 50 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16840 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36880 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 53775 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3693 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3693 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132888 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 132888 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 49 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16846 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36870 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 53772 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3714 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3714 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132646 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 132646 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 50 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16840 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169768 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 186663 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 49 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16846 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169516 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 186418 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 50 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16840 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169768 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 186663 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5701045 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16846 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169516 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 186418 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5629796 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 968087231 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2080048452 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3054150983 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37901173 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37901173 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235111902 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235111902 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5701045 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 961575741 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2092180467 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3059700259 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 38132194 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 38132194 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5227507665 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5227507665 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5629796 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 968087231 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7315160354 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8289262885 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5701045 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 961575741 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7319688132 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8287207924 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5629796 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 968087231 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7315160354 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8289262885 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187415500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187415500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308505000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308505000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495920500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495920500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026899 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021275 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.914562 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.914562 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459834 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459834 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.066271 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.066271 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 961575741 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7319688132 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8287207924 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187404000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187404000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308295000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308295000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495699000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495699000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000748 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016104 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026907 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021273 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.917264 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.917264 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459278 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459278 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016104 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102174 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.066187 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016104 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102174 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.066187 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57487.365261 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56400.446095 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56794.997359 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.976713 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.976713 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39394.918292 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39394.918292 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57080.359789 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56744.791619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56901.366120 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10267.149704 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10267.149704 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39409.463271 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39409.463271 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57080.359789 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43179.924798 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44454.977116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57080.359789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43179.924798 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44454.977116 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index 1fcee5057..ed2841d64 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=200000 type=SparcSystem children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000 boot_osflags=a +clock=2 hypervisor_addr=1099243257856 hypervisor_bin=/dist/m5/system/binaries/q_new.bin hypervisor_desc=system.hypervisor_desc @@ -19,7 +20,8 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic -memories=system.partition_desc system.rom system.hypervisor_desc system.nvram system.physmem system.physmem2 +mem_ranges=1048576:68157439 2147483648:2415919103 +memories=system.partition_desc system.physmem system.rom system.hypervisor_desc system.physmem2 system.nvram num_work_ids=16 nvram=system.nvram nvram_addr=133429198848 @@ -45,22 +47,21 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=2 delay=100 -nack_delay=8 ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[2] [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts itb tracer +children=dtb interrupts isa itb tracer +branchPred=Null checker=Null -clock=1 +clock=2 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -69,17 +70,18 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu.tracer width=1 @@ -94,6 +96,9 @@ size=64 [system.cpu.interrupts] type=SparcInterrupts +[system.cpu.isa] +type=SparcISA + [system.cpu.itb] type=SparcTLB size=64 @@ -104,9 +109,10 @@ type=ExeTracer [system.disk0] type=MmDisk children=image +clock=2 image=system.disk0.image pio_addr=134217728000 -pio_latency=2 +pio_latency=200 system=system pio=system.iobus.master[14] @@ -125,8 +131,9 @@ read_only=true [system.hypervisor_desc] type=SimpleMemory +bandwidth=0.000000 +clock=2 conf_table_reported=false -file= in_addr_map=true latency=60 latency_var=0 @@ -145,7 +152,7 @@ block_size=64 clock=2 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio slave=system.bridge.master @@ -155,17 +162,19 @@ children=badaddr_responder block_size=64 clock=2 header_cycles=1 +system=system use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio -master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] +master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port system.physmem2.port system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.membus.badaddr_responder] type=IsaFake +clock=2 fake_mem=false pio_addr=0 -pio_latency=2 +pio_latency=200 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -179,8 +188,9 @@ pio=system.membus.default [system.nvram] type=SimpleMemory +bandwidth=0.000000 +clock=2 conf_table_reported=false -file= in_addr_map=true latency=60 latency_var=0 @@ -191,8 +201,9 @@ port=system.membus.master[6] [system.partition_desc] type=SimpleMemory +bandwidth=0.000000 +clock=2 conf_table_reported=false -file= in_addr_map=true latency=60 latency_var=0 @@ -202,33 +213,68 @@ zero=false port=system.membus.master[8] [system.physmem] -type=SimpleMemory +type=SimpleDRAM +activation_limit=4 +addr_mapping=openmap +banks_per_rank=8 +channels=1 +clock=2 conf_table_reported=false -file= in_addr_map=true -latency=60 -latency_var=0 +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false +page_policy=open range=1048576:68157439 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=10 +tCL=28 +tRCD=28 +tREFI=15600 +tRFC=600 +tRP=28 +tWTR=15 +tXAW=80 +write_buffer_size=32 +write_thresh_perc=70 zero=true port=system.membus.master[3] [system.physmem2] -type=SimpleMemory +type=SimpleDRAM +activation_limit=4 +addr_mapping=openmap +banks_per_rank=8 +channels=1 +clock=2 conf_table_reported=false -file= in_addr_map=true -latency=60 -latency_var=0 +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false +page_policy=open range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=10 +tCL=28 +tRCD=28 +tREFI=15600 +tRFC=600 +tRP=28 +tWTR=15 +tXAW=80 +write_buffer_size=32 +write_thresh_perc=70 zero=true port=system.membus.master[4] [system.rom] type=SimpleMemory +bandwidth=0.000000 +clock=2 conf_table_reported=false -file= in_addr_map=true latency=60 latency_var=0 @@ -245,9 +291,10 @@ system=system [system.t1000.fake_clk] type=IsaFake +clock=2 fake_mem=false pio_addr=644245094400 -pio_latency=2 +pio_latency=200 pio_size=4294967296 ret_bad_addr=false ret_data16=65535 @@ -261,9 +308,10 @@ pio=system.iobus.master[0] [system.t1000.fake_jbi] type=IsaFake +clock=2 fake_mem=false pio_addr=549755813888 -pio_latency=2 +pio_latency=200 pio_size=4294967296 ret_bad_addr=false ret_data16=65535 @@ -277,9 +325,10 @@ pio=system.iobus.master[11] [system.t1000.fake_l2_1] type=IsaFake +clock=2 fake_mem=false pio_addr=725849473024 -pio_latency=2 +pio_latency=200 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -293,9 +342,10 @@ pio=system.iobus.master[2] [system.t1000.fake_l2_2] type=IsaFake +clock=2 fake_mem=false pio_addr=725849473088 -pio_latency=2 +pio_latency=200 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -309,9 +359,10 @@ pio=system.iobus.master[3] [system.t1000.fake_l2_3] type=IsaFake +clock=2 fake_mem=false pio_addr=725849473152 -pio_latency=2 +pio_latency=200 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -325,9 +376,10 @@ pio=system.iobus.master[4] [system.t1000.fake_l2_4] type=IsaFake +clock=2 fake_mem=false pio_addr=725849473216 -pio_latency=2 +pio_latency=200 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -341,9 +393,10 @@ pio=system.iobus.master[5] [system.t1000.fake_l2esr_1] type=IsaFake +clock=2 fake_mem=false pio_addr=734439407616 -pio_latency=2 +pio_latency=200 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -357,9 +410,10 @@ pio=system.iobus.master[6] [system.t1000.fake_l2esr_2] type=IsaFake +clock=2 fake_mem=false pio_addr=734439407680 -pio_latency=2 +pio_latency=200 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -373,9 +427,10 @@ pio=system.iobus.master[7] [system.t1000.fake_l2esr_3] type=IsaFake +clock=2 fake_mem=false pio_addr=734439407744 -pio_latency=2 +pio_latency=200 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -389,9 +444,10 @@ pio=system.iobus.master[8] [system.t1000.fake_l2esr_4] type=IsaFake +clock=2 fake_mem=false pio_addr=734439407808 -pio_latency=2 +pio_latency=200 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -405,9 +461,10 @@ pio=system.iobus.master[9] [system.t1000.fake_membnks] type=IsaFake +clock=2 fake_mem=false pio_addr=648540061696 -pio_latency=2 +pio_latency=200 pio_size=16384 ret_bad_addr=false ret_data16=65535 @@ -421,9 +478,10 @@ pio=system.iobus.master[1] [system.t1000.fake_ssi] type=IsaFake +clock=2 fake_mem=false pio_addr=1095216660480 -pio_latency=2 +pio_latency=200 pio_size=268435456 ret_bad_addr=false ret_data16=65535 @@ -444,16 +502,18 @@ port=3456 [system.t1000.htod] type=DumbTOD +clock=2 pio_addr=1099255906296 -pio_latency=2 +pio_latency=200 system=system time=Thu Jan 1 00:00:00 2009 pio=system.membus.master[1] [system.t1000.hvuart] type=Uart8250 +clock=2 pio_addr=1099255955456 -pio_latency=2 +pio_latency=200 platform=system.t1000 system=system terminal=system.t1000.hterm @@ -461,6 +521,7 @@ pio=system.iobus.master[13] [system.t1000.iob] type=Iob +clock=2 pio_latency=2 platform=system.t1000 system=system @@ -475,8 +536,9 @@ port=3456 [system.t1000.puart0] type=Uart8250 +clock=2 pio_addr=133412421632 -pio_latency=2 +pio_latency=200 platform=system.t1000 system=system terminal=system.t1000.pterm diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr index 61ba0c5bc..49566b7e3 100755 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr @@ -1,3 +1,19 @@ +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 +warn: rounding error > tolerance + 0.145519 rounded to 0 warn: Sockets disabled, not accepting terminal connections warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index 483f7795e..e5c65571f 100755 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -1,16 +1,16 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 15:02:47 +gem5 compiled Mar 3 2013 21:18:30 +gem5 started Mar 3 2013 22:32:14 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second -info: No kernel set for full system simulation. Assuming you know what you're doing if not SPARC ISA +info: No kernel set for full system simulation. Assuming you know what you're doing 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.t1000.htod: Real-time clock set to 1230768000 info: Entering event queue @ 0. Starting simulation... info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter -Exiting @ tick 2233777512 because m5_exit instruction encountered +Exiting @ tick 4467555024 because m5_exit instruction encountered diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index d3e0ccb5c..91425a88c 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.233778 # Nu sim_ticks 4467555024 # Number of ticks simulated final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 2957774 # Simulator instruction rate (inst/s) -host_op_rate 2958936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5930129 # Simulator tick rate (ticks/s) -host_mem_usage 530032 # Number of bytes of host memory used -host_seconds 753.37 # Real time elapsed on the host +host_inst_rate 3081772 # Simulator instruction rate (inst/s) +host_op_rate 3082983 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6178737 # Simulator tick rate (ticks/s) +host_mem_usage 519228 # Number of bytes of host memory used +host_seconds 723.05 # Real time elapsed on the host sim_insts 2228284650 # Number of instructions simulated sim_ops 2229160714 # Number of ops (including micro ops) simulated system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory @@ -19,20 +19,6 @@ system.hypervisor_desc.bw_read::cpu.data 7517 # To system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s) system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s) system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory -system.nvram.bytes_read::total 284 # Number of bytes read from this memory -system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory -system.nvram.bytes_written::total 92 # Number of bytes written to this memory -system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory -system.nvram.num_reads::total 284 # Number of read requests responded to by this memory -system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory -system.nvram.num_writes::total 92 # Number of write requests responded to by this memory -system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s) system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory @@ -41,204 +27,6 @@ system.partition_desc.bw_read::cpu.data 2169 # To system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s) system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s) system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory -system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory -system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory -system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory -system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory -system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory -system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory -system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory -system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory -system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory -system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory -system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory -system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory -system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory -system.physmem2.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.readReqs 0 # Total number of read requests seen -system.physmem2.writeReqs 0 # Total number of write requests seen -system.physmem2.cpureqs 0 # Reqs generatd by CPU via cache - shady -system.physmem2.bytesRead 0 # Total number of bytes read from memory -system.physmem2.bytesWritten 0 # Total number of bytes written to memory -system.physmem2.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() -system.physmem2.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem2.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem2.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem2.perBankRdReqs::0 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::2 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::3 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::4 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::5 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::6 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::7 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::8 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::9 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::10 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::12 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::13 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem2.perBankRdReqs::15 0 # Track reads on a per bank basis -system.physmem2.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem2.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem2.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem2.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem2.totGap 0 # Total gap between requests -system.physmem2.readPktSize::0 0 # Categorize read packet sizes -system.physmem2.readPktSize::1 0 # Categorize read packet sizes -system.physmem2.readPktSize::2 0 # Categorize read packet sizes -system.physmem2.readPktSize::3 0 # Categorize read packet sizes -system.physmem2.readPktSize::4 0 # Categorize read packet sizes -system.physmem2.readPktSize::5 0 # Categorize read packet sizes -system.physmem2.readPktSize::6 0 # Categorize read packet sizes -system.physmem2.readPktSize::7 0 # Categorize read packet sizes -system.physmem2.readPktSize::8 0 # Categorize read packet sizes -system.physmem2.writePktSize::0 0 # categorize write packet sizes -system.physmem2.writePktSize::1 0 # categorize write packet sizes -system.physmem2.writePktSize::2 0 # categorize write packet sizes -system.physmem2.writePktSize::3 0 # categorize write packet sizes -system.physmem2.writePktSize::4 0 # categorize write packet sizes -system.physmem2.writePktSize::5 0 # categorize write packet sizes -system.physmem2.writePktSize::6 0 # categorize write packet sizes -system.physmem2.writePktSize::7 0 # categorize write packet sizes -system.physmem2.writePktSize::8 0 # categorize write packet sizes -system.physmem2.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem2.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem2.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem2.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem2.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem2.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem2.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem2.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem2.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem2.rdQLenPdf::0 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem2.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem2.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem2.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem2.totQLat 0 # Total cycles spent in queuing delays -system.physmem2.totMemAccLat 0 # Sum of mem lat for all requests -system.physmem2.totBusLat 0 # Total cycles spent in databus access -system.physmem2.totBankLat 0 # Total cycles spent in bank access -system.physmem2.avgQLat nan # Average queueing delay per request -system.physmem2.avgBankLat nan # Average bank access latency per request -system.physmem2.avgBusLat nan # Average bus latency per request -system.physmem2.avgMemAccLat nan # Average memory access latency -system.physmem2.avgRdBW 0.00 # Average achieved read bandwidth in MB/s -system.physmem2.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem2.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s -system.physmem2.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem2.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem2.busUtil 0.00 # Data bus utilization in percentage -system.physmem2.avgRdQLen 0.00 # Average read queue length over time -system.physmem2.avgWrQLen 0.00 # Average write queue length over time -system.physmem2.readRowHits 0 # Number of row buffer hits during reads -system.physmem2.writeRowHits 0 # Number of row buffer hits during writes -system.physmem2.readRowHitRate nan # Row buffer hit rate for reads -system.physmem2.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem2.avgGap nan # Average gap between requests -system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory -system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory -system.rom.bytes_read::total 1128688 # Number of bytes read from this memory -system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory -system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory -system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory -system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory -system.rom.num_reads::total 195123 # Number of read requests responded to by this memory -system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory @@ -314,26 +102,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -366,7 +141,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -399,7 +173,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -421,6 +194,203 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests +system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory +system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory +system.rom.bytes_read::total 1128688 # Number of bytes read from this memory +system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory +system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory +system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory +system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory +system.rom.num_reads::total 195123 # Number of read requests responded to by this memory +system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory +system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory +system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory +system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory +system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory +system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory +system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory +system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory +system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory +system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory +system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory +system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory +system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory +system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory +system.physmem2.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem2.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem2.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s) +system.physmem2.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s) +system.physmem2.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.readReqs 0 # Total number of read requests seen +system.physmem2.writeReqs 0 # Total number of write requests seen +system.physmem2.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem2.bytesRead 0 # Total number of bytes read from memory +system.physmem2.bytesWritten 0 # Total number of bytes written to memory +system.physmem2.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +system.physmem2.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem2.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem2.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem2.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::10 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::15 0 # Track reads on a per bank basis +system.physmem2.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem2.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem2.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem2.totGap 0 # Total gap between requests +system.physmem2.readPktSize::0 0 # Categorize read packet sizes +system.physmem2.readPktSize::1 0 # Categorize read packet sizes +system.physmem2.readPktSize::2 0 # Categorize read packet sizes +system.physmem2.readPktSize::3 0 # Categorize read packet sizes +system.physmem2.readPktSize::4 0 # Categorize read packet sizes +system.physmem2.readPktSize::5 0 # Categorize read packet sizes +system.physmem2.readPktSize::6 0 # Categorize read packet sizes +system.physmem2.writePktSize::0 0 # Categorize write packet sizes +system.physmem2.writePktSize::1 0 # Categorize write packet sizes +system.physmem2.writePktSize::2 0 # Categorize write packet sizes +system.physmem2.writePktSize::3 0 # Categorize write packet sizes +system.physmem2.writePktSize::4 0 # Categorize write packet sizes +system.physmem2.writePktSize::5 0 # Categorize write packet sizes +system.physmem2.writePktSize::6 0 # Categorize write packet sizes +system.physmem2.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem2.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem2.totQLat 0 # Total cycles spent in queuing delays +system.physmem2.totMemAccLat 0 # Sum of mem lat for all requests +system.physmem2.totBusLat 0 # Total cycles spent in databus access +system.physmem2.totBankLat 0 # Total cycles spent in bank access +system.physmem2.avgQLat nan # Average queueing delay per request +system.physmem2.avgBankLat nan # Average bank access latency per request +system.physmem2.avgBusLat nan # Average bus latency per request +system.physmem2.avgMemAccLat nan # Average memory access latency +system.physmem2.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +system.physmem2.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem2.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +system.physmem2.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem2.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem2.busUtil 0.00 # Data bus utilization in percentage +system.physmem2.avgRdQLen 0.00 # Average read queue length over time +system.physmem2.avgWrQLen 0.00 # Average write queue length over time +system.physmem2.readRowHits 0 # Number of row buffer hits during reads +system.physmem2.writeRowHits 0 # Number of row buffer hits during writes +system.physmem2.readRowHitRate nan # Row buffer hit rate for reads +system.physmem2.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem2.avgGap nan # Average gap between requests +system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory +system.nvram.bytes_read::total 284 # Number of bytes read from this memory +system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory +system.nvram.bytes_written::total 92 # Number of bytes written to this memory +system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory +system.nvram.num_reads::total 284 # Number of read requests responded to by this memory +system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory +system.nvram.num_writes::total 92 # Number of write requests responded to by this memory +system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s) system.cpu.numCycles 2233777513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 7a8202b52..ed4236d5d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -528,9 +528,9 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -555,6 +555,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 5400b92b5..78db76e29 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:38:19 -gem5 started Feb 13 2013 19:20:32 -gem5 executing on u200540-lin +gem5 compiled Mar 3 2013 21:21:53 +gem5 started Mar 4 2013 00:58:30 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 199938942500 because target called exit() +Exiting @ tick 199930442500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 4facf02db..83f6a1bd8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,116 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.199960 # Number of seconds simulated -sim_ticks 199959919500 # Number of ticks simulated -final_tick 199959919500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.199930 # Number of seconds simulated +sim_ticks 199930442500 # Number of ticks simulated +final_tick 199930442500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126038 # Simulator instruction rate (inst/s) -host_op_rate 142101 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49882714 # Simulator tick rate (ticks/s) -host_mem_usage 278340 # Number of bytes of host memory used -host_seconds 4008.60 # Real time elapsed on the host +host_inst_rate 127290 # Simulator instruction rate (inst/s) +host_op_rate 143512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50370674 # Simulator tick rate (ticks/s) +host_mem_usage 265580 # Number of bytes of host memory used +host_seconds 3969.18 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9260800 # Number of bytes read from this memory -system.physmem.bytes_read::total 9477568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6246592 # Number of bytes written to this memory -system.physmem.bytes_written::total 6246592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144700 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148087 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97603 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97603 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1084057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46313281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47397339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1084057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1084057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31239220 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31239220 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31239220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1084057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46313281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78636559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148088 # Total number of read requests seen -system.physmem.writeReqs 97603 # Total number of write requests seen -system.physmem.cpureqs 247534 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9477568 # Total number of bytes read from memory -system.physmem.bytesWritten 6246592 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9477568 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6246592 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 77 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 6 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9156 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9186 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9528 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9506 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9094 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9054 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 9284 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9051 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9201 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5987 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6274 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6476 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6228 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6222 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6039 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 216192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9265152 # Number of bytes read from this memory +system.physmem.bytes_read::total 9481344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6247552 # Number of bytes written to this memory +system.physmem.bytes_written::total 6247552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144768 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97618 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97618 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1081336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46341877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47423213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1081336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1081336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31248628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31248628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31248628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1081336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46341877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 78671841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148147 # Total number of read requests seen +system.physmem.writeReqs 97618 # Total number of write requests seen +system.physmem.cpureqs 247832 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9481344 # Total number of bytes read from memory +system.physmem.bytesWritten 6247552 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9481344 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6247552 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9166 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9182 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9622 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 9866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9514 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9403 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9092 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9052 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 9254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8851 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9034 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9025 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9210 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5950 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5982 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6482 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6170 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6032 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 5973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6195 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5980 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6048 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6101 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5908 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6109 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5940 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6062 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6095 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1837 # Number of times wr buffer was full causing retry -system.physmem.totGap 199959894000 # Total gap between requests +system.physmem.numWrRetry 2058 # Number of times wr buffer was full causing retry +system.physmem.totGap 199930425500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148088 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 99440 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 6 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 138077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.readPktSize::6 148147 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 97618 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 137980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -137,70 +124,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4234 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1699469983 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4970281233 # Sum of mem lat for all requests -system.physmem.totBusLat 740055000 # Total cycles spent in databus access -system.physmem.totBankLat 2530756250 # Total cycles spent in bank access -system.physmem.avgQLat 11482.05 # Average queueing delay per request -system.physmem.avgBankLat 17098.43 # Average bank access latency per request +system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.totQLat 1712037750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4981606500 # Sum of mem lat for all requests +system.physmem.totBusLat 740435000 # Total cycles spent in databus access +system.physmem.totBankLat 2529133750 # Total cycles spent in bank access +system.physmem.avgQLat 11561.03 # Average queueing delay per request +system.physmem.avgBankLat 17078.70 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33580.49 # Average memory access latency -system.physmem.avgRdBW 47.40 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 31.24 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.40 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 31.24 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 33639.73 # Average memory access latency +system.physmem.avgRdBW 47.42 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.42 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.80 # Average write queue length over time -system.physmem.readRowHits 125322 # Number of row buffer hits during reads -system.physmem.writeRowHits 52822 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.12 # Row buffer hit rate for writes -system.physmem.avgGap 813867.39 # Average gap between requests -system.cpu.branchPred.lookups 182791909 # Number of BP lookups -system.cpu.branchPred.condPredicted 143104920 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7263448 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93100856 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87211306 # Number of BTB hits +system.physmem.avgWrQLen 8.71 # Average write queue length over time +system.physmem.readRowHits 125393 # Number of row buffer hits during reads +system.physmem.writeRowHits 52794 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 54.08 # Row buffer hit rate for writes +system.physmem.avgGap 813502.43 # Average gap between requests +system.cpu.branchPred.lookups 182807672 # Number of BP lookups +system.cpu.branchPred.condPredicted 143119940 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265200 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 92612738 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87226650 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.674011 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12676660 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116192 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.184290 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12677704 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116304 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,136 +229,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 399919840 # number of cpu cycles simulated +system.cpu.numCycles 399860886 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119359242 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761526244 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182791909 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99887966 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170136962 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35675847 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75471629 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 650 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114518172 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2437097 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 392580882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.175648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.990337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119358222 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761608008 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182807672 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99904354 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170147877 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35680811 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75396284 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 468 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 45 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114514342 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2439022 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 392517505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.176152 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.990501 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222456572 56.67% 56.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14184957 3.61% 60.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22893267 5.83% 66.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22743461 5.79% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20901253 5.32% 77.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11599327 2.95% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13055185 3.33% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11991563 3.05% 86.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52755297 13.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222382247 56.66% 56.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14190044 3.62% 60.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22888927 5.83% 66.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22740218 5.79% 71.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20908888 5.33% 77.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11594217 2.95% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13063164 3.33% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11994936 3.06% 86.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52754864 13.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 392580882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.457071 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.904197 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129017942 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 70989640 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158833179 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6202041 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27538080 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26128135 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 77010 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825507648 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 295471 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27538080 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135602175 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9653631 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46459749 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158272352 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15054895 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800579867 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1059 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3045560 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8808243 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 238 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954266949 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500439750 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500438390 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 392517505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457178 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.904682 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129005298 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 70927026 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158858538 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6186097 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27540546 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26127343 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76683 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825553021 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 296390 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27540546 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135586345 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9628782 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46469860 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158285767 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15006205 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800628342 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1130 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3045894 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8758928 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 294 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954382842 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500628672 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500627387 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1285 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288014658 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292979 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292975 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41576680 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170252258 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73485876 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28570132 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15813364 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755065776 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775319 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665331498 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1369025 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187382058 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479835806 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797687 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 392580882 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.694763 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735550 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288130551 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292970 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41448640 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170247105 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73473871 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28488219 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15923707 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755060750 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775315 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665323167 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1373619 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187375419 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479909972 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797683 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 392517505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.695015 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735938 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 137175345 34.94% 34.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69848009 17.79% 52.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71421264 18.19% 70.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53409606 13.60% 84.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31213744 7.95% 92.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16052398 4.09% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8748856 2.23% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2891239 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1820421 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 137188203 34.95% 34.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69757763 17.77% 52.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71444239 18.20% 70.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53382766 13.60% 84.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31199092 7.95% 92.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16084863 4.10% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8731670 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2913347 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1815562 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 392580882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 392517505 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 477908 5.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6514153 68.18% 73.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2562402 26.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 478854 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6518035 68.44% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2526744 26.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447790588 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383397 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447790300 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383235 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 96 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -399,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153366793 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63790621 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153391187 23.06% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63758352 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665331498 # Type of FU issued -system.cpu.iq.rate 1.663662 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9554463 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014360 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1734167139 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947029128 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646060992 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665323167 # Type of FU issued +system.cpu.iq.rate 1.663887 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9523633 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014314 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1734060876 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947018314 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646045006 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674885846 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 115 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8559648 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674846691 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8570702 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44222703 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810061 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16625399 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44217550 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42225 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810789 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16613394 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19536 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4374 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19530 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4440 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27538080 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5027706 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 374233 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760399793 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1113000 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170252258 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73485876 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286777 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 218846 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12338 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810061 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4335774 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4000856 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8336630 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655910156 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150087379 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9421342 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27540546 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5027645 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 374127 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760395240 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1110246 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170247105 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73473871 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286773 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 218357 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11618 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810789 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4336068 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4004006 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8340074 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655902697 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150107572 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9420470 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558698 # number of nop insts executed -system.cpu.iew.exec_refs 212584480 # number of memory reference insts executed -system.cpu.iew.exec_branches 138500041 # Number of branches executed -system.cpu.iew.exec_stores 62497101 # Number of stores executed -system.cpu.iew.exec_rate 1.640104 # Inst execution rate -system.cpu.iew.wb_sent 651032473 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646061008 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374768785 # num instructions producing a value -system.cpu.iew.wb_consumers 646479955 # num instructions consuming a value +system.cpu.iew.exec_nop 1559175 # number of nop insts executed +system.cpu.iew.exec_refs 212574642 # number of memory reference insts executed +system.cpu.iew.exec_branches 138502057 # Number of branches executed +system.cpu.iew.exec_stores 62467070 # Number of stores executed +system.cpu.iew.exec_rate 1.640327 # Inst execution rate +system.cpu.iew.wb_sent 651021062 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646045022 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374765758 # num instructions producing a value +system.cpu.iew.wb_consumers 646459860 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615476 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579707 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615674 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579720 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189458167 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189453742 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7189194 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 365042802 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.564113 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233409 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7191165 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 364976959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.564395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233817 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 157342257 43.10% 43.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98505195 26.98% 70.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33835922 9.27% 79.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18767828 5.14% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16196095 4.44% 88.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7449740 2.04% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6969572 1.91% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3172412 0.87% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22803781 6.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 157310366 43.10% 43.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98490082 26.99% 70.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33805907 9.26% 79.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18787402 5.15% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16180614 4.43% 88.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7431287 2.04% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6987633 1.91% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3169968 0.87% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22813700 6.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 365042802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 364976959 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,199 +472,199 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22803781 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22813700 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1102658217 # The number of ROB reads -system.cpu.rob.rob_writes 1548511592 # The number of ROB writes -system.cpu.timesIdled 308911 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7338958 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1102578030 # The number of ROB reads +system.cpu.rob.rob_writes 1548505178 # The number of ROB writes +system.cpu.timesIdled 308567 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7343381 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.791548 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.791548 # CPI: Total CPI of All Threads -system.cpu.ipc 1.263347 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.263347 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058721385 # number of integer regfile reads -system.cpu.int_regfile_writes 752002162 # number of integer regfile writes +system.cpu.cpi 0.791431 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.791431 # CPI: Total CPI of All Threads +system.cpu.ipc 1.263534 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.263534 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058706465 # number of integer regfile reads +system.cpu.int_regfile_writes 752037507 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210835812 # number of misc regfile reads +system.cpu.misc_regfile_reads 210820275 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.icache.replacements 15017 # number of replacements -system.cpu.icache.tagsinuse 1100.275071 # Cycle average of tags in use -system.cpu.icache.total_refs 114497128 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16875 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6785.014993 # Average number of references to valid blocks. +system.cpu.icache.replacements 15019 # number of replacements +system.cpu.icache.tagsinuse 1100.569602 # Cycle average of tags in use +system.cpu.icache.total_refs 114493231 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16877 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6783.980032 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1100.275071 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537244 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537244 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114497128 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114497128 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114497128 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114497128 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114497128 # number of overall hits -system.cpu.icache.overall_hits::total 114497128 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21044 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21044 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21044 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21044 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21044 # number of overall misses -system.cpu.icache.overall_misses::total 21044 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 498168000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 498168000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 498168000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 498168000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 498168000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 498168000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114518172 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114518172 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114518172 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114518172 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114518172 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114518172 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1100.569602 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537388 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537388 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114493231 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114493231 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114493231 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114493231 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114493231 # number of overall hits +system.cpu.icache.overall_hits::total 114493231 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21111 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21111 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21111 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21111 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21111 # number of overall misses +system.cpu.icache.overall_misses::total 21111 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 514757500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 514757500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 514757500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 514757500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 514757500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 514757500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114514342 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114514342 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114514342 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114514342 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114514342 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114514342 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23672.685801 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23672.685801 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23672.685801 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23672.685801 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 381 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24383.378334 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24383.378334 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24383.378334 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24383.378334 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1152 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.100000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 88.615385 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4078 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4078 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4078 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4078 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4078 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4078 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16966 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16966 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16966 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16966 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16966 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16966 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 370390500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 370390500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 370390500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 370390500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 370390500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 370390500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4153 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4153 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4153 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4153 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4153 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4153 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16958 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16958 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16958 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16958 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16958 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16958 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375680500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 375680500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375680500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 375680500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375680500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 375680500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21831.339149 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21831.339149 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21831.339149 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21831.339149 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21831.339149 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21831.339149 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22153.585328 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22153.585328 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22153.585328 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22153.585328 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22153.585328 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22153.585328 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115340 # number of replacements -system.cpu.l2cache.tagsinuse 27103.357438 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1781605 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 146589 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 12.153743 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 100678479000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23035.141201 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 363.560333 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3704.655904 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.702977 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.011095 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.113057 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.827129 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13475 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804570 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 818045 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1111113 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1111113 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 86 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 86 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247517 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247517 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13475 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1052087 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065562 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 13475 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1052087 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065562 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3393 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43422 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 46815 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101299 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101299 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3393 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144721 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148114 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144721 # number of overall misses -system.cpu.l2cache.overall_misses::total 148114 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 218124500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2897532500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3115657000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5229658000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5229658000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 218124500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8127190500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8345315000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 218124500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8127190500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8345315000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16868 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 847992 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 864860 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1111113 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1111113 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 92 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 348816 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 348816 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 16868 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1196808 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1213676 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16868 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1196808 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1213676 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.201150 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051206 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.054130 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.065217 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.065217 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290408 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.290408 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.201150 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.120922 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.122038 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.201150 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.120922 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.122038 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64286.619511 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66729.595597 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66552.536580 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51625.958795 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51625.958795 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64286.619511 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56157.644709 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56343.863511 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64286.619511 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56157.644709 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56343.863511 # average overall miss latency +system.cpu.l2cache.replacements 115398 # number of replacements +system.cpu.l2cache.tagsinuse 27101.777399 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1781753 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 146655 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 12.149282 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 100667210000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 23032.613766 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 362.003835 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3707.159797 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.702900 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.011047 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.113134 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.827081 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13488 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 804399 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 817887 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1110977 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1110977 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 73 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 73 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 247537 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 247537 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13488 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1051936 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065424 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13488 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1051936 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065424 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3382 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 43478 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 46860 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101314 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101314 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 144792 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 148174 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 144792 # number of overall misses +system.cpu.l2cache.overall_misses::total 148174 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223286000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2917634500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3140920500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5217385000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5217385000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 223286000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8135019500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8358305500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 223286000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8135019500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8358305500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16870 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 847877 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 864747 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1110977 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1110977 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 82 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 348851 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 348851 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 16870 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1196728 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1213598 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 16870 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1196728 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1213598 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200474 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051279 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.054189 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.109756 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.109756 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290422 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.290422 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200474 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.120990 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.122095 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200474 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.120990 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.122095 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66021.880544 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67105.996136 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67027.752881 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51497.177093 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51497.177093 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66021.880544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56184.177993 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56408.718804 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66021.880544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56184.177993 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56408.718804 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -688,195 +673,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97603 # number of writebacks -system.cpu.l2cache.writebacks::total 97603 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3388 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43401 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 46789 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101299 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101299 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3388 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144700 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148088 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3388 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144700 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148088 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175595014 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2357208396 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2532803410 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 60006 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 60006 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3964657000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3964657000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175595014 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6321865396 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6497460410 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175595014 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6321865396 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6497460410 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051181 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054100 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.065217 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.065217 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290408 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290408 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120905 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122016 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120905 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122016 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51828.516529 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54312.306076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54132.454423 # average ReadReq mshr miss latency +system.cpu.l2cache.writebacks::writebacks 97618 # number of writebacks +system.cpu.l2cache.writebacks::total 97618 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43455 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46833 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101314 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101314 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3378 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144769 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148147 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3378 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144769 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148147 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180723170 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2376770410 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2557493580 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3952267092 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3952267092 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180723170 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6329037502 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6509760672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180723170 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6329037502 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6509760672 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051252 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.109756 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.109756 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290422 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290422 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122073 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122073 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53500.050326 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54694.981245 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.792518 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39138.165234 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39138.165234 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51828.516529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43689.463690 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43875.671290 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51828.516529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43689.463690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43875.671290 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39010.078489 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39010.078489 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192712 # number of replacements -system.cpu.dcache.tagsinuse 4058.214665 # Cycle average of tags in use -system.cpu.dcache.total_refs 190183804 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196808 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.909202 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1192631 # number of replacements +system.cpu.dcache.tagsinuse 4058.209057 # Cycle average of tags in use +system.cpu.dcache.total_refs 190187917 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196727 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 158.923394 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.214665 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990775 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990775 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136214217 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136214217 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50991947 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50991947 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488812 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488812 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 4058.209057 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990774 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990774 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136218647 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136218647 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50991635 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50991635 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488827 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488827 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187206164 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187206164 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187206164 # number of overall hits -system.cpu.dcache.overall_hits::total 187206164 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1696297 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1696297 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3247359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3247359 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 187210282 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187210282 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187210282 # number of overall hits +system.cpu.dcache.overall_hits::total 187210282 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1699163 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1699163 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3247671 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3247671 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4943656 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4943656 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4943656 # number of overall misses -system.cpu.dcache.overall_misses::total 4943656 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26545297500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26545297500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57237294950 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57237294950 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 659000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 659000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83782592450 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83782592450 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83782592450 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83782592450 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137910514 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137910514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4946834 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4946834 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4946834 # number of overall misses +system.cpu.dcache.overall_misses::total 4946834 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26685574500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26685574500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57046648448 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57046648448 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 615500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 615500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83732222948 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83732222948 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83732222948 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83732222948 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137917810 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137917810 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488853 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488853 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488868 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488868 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192149820 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192149820 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192149820 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192149820 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012300 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012300 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059871 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059871 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 192157116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192157116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192157116 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192157116 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012320 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012320 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15648.968017 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15648.968017 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17625.798364 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17625.798364 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16073.170732 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16073.170732 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16947.496438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16947.496438 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18139 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17902 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1666 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 610 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.887755 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 29.347541 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15705.129231 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15705.129231 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17565.402545 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17565.402545 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15012.195122 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15012.195122 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16926.426670 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16926.426670 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18054 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15751 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1658 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 601 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.889023 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26.207987 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111113 # number of writebacks -system.cpu.dcache.writebacks::total 1111113 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847762 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 847762 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898994 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2898994 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1110977 # number of writebacks +system.cpu.dcache.writebacks::total 1110977 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850754 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 850754 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2899270 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3746756 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3746756 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3746756 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3746756 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848535 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848535 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348365 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348365 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196900 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196900 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196900 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196900 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11831456500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11831456500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8103165495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8103165495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19934621995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19934621995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19934621995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19934621995 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006153 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 3750024 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3750024 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3750024 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3750024 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848409 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848409 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348401 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348401 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196810 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196810 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196810 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196810 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11849237000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11849237000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8091181496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8091181496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19940418496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19940418496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19940418496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19940418496 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.392435 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.392435 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23260.561466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23260.561466 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13966.420677 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13966.420677 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23223.760827 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23223.760827 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 4cd0f21e4..fc49f2d63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -527,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr index bf930ad43..e8096c4c9 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[15], opc1[7], crm[4], opc2[6] getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 6de8db104..30ec371c4 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 20:14:28 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Mar 3 2013 21:21:53 +gem5 started Mar 4 2013 01:05:57 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -15,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.060000 -Exiting @ tick 68071881000 because target called exit() +Exiting @ tick 68244180000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 3aa47fab4..60dc6772d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068358 # Number of seconds simulated -sim_ticks 68358106500 # Number of ticks simulated -final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068244 # Number of seconds simulated +sim_ticks 68244180000 # Number of ticks simulated +final_tick 68244180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161957 # Simulator instruction rate (inst/s) -host_op_rate 207054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40547923 # Simulator tick rate (ticks/s) -host_mem_usage 250356 # Number of bytes of host memory used -host_seconds 1685.86 # Real time elapsed on the host +host_inst_rate 137663 # Simulator instruction rate (inst/s) +host_op_rate 175996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34408261 # Simulator tick rate (ticks/s) +host_mem_usage 247964 # Number of bytes of host memory used +host_seconds 1983.37 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory -system.physmem.bytes_read::total 465728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193152 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3018 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7277 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2825590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3987471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6813062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2825590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2825590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2825590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3987471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6813062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7278 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 194624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272640 # Number of bytes read from this memory +system.physmem.bytes_read::total 467264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194624 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3041 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4260 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7301 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2851877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3995066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6846943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2851877 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2851877 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2851877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3995066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6846943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7301 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7280 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 465728 # Total number of bytes read from memory +system.physmem.cpureqs 7303 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 467264 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 465728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 467264 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 413 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 411 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 478 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 504 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 546 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 585 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 400 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 480 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 506 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 490 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 545 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 589 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 454 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 381 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 451 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 454 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 414 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68358086000 # Total gap between requests +system.physmem.totGap 68243977000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7278 # Categorize read packet sizes +system.physmem.readPktSize::6 7301 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 46720000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 192175000 # Sum of mem lat for all requests -system.physmem.totBusLat 36390000 # Total cycles spent in databus access -system.physmem.totBankLat 109065000 # Total cycles spent in bank access -system.physmem.avgQLat 6419.35 # Average queueing delay per request -system.physmem.avgBankLat 14985.57 # Average bank access latency per request +system.physmem.totQLat 46265250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 192440250 # Sum of mem lat for all requests +system.physmem.totBusLat 36505000 # Total cycles spent in databus access +system.physmem.totBankLat 109670000 # Total cycles spent in bank access +system.physmem.avgQLat 6336.84 # Average queueing delay per request +system.physmem.avgBankLat 15021.23 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26404.92 # Average memory access latency -system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26358.07 # Average memory access latency +system.physmem.avgRdBW 6.85 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.85 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6070 # Number of row buffer hits during reads +system.physmem.readRowHits 6086 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9392427.32 # Average gap between requests -system.cpu.branchPred.lookups 41732744 # Number of BP lookups -system.cpu.branchPred.condPredicted 21038238 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1652729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26040996 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16764116 # Number of BTB hits +system.physmem.avgGap 9347209.56 # Average gap between requests +system.cpu.branchPred.lookups 35347226 # Number of BP lookups +system.cpu.branchPred.condPredicted 21179372 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1632309 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18774732 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16740348 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.375863 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6744035 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 7274 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.164245 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6786825 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8584 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -222,100 +222,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136716214 # number of cpu cycles simulated +system.cpu.numCycles 136488361 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38933938 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317883912 # Number of instructions fetch has processed -system.cpu.fetch.Branches 41732744 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23508151 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70884226 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6817030 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21520624 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1371 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37551869 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 523991 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136493185 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.988959 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.456313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 38874281 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317253074 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35347226 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23527173 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70748427 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6762105 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21521098 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1748 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37491442 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 499448 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136264051 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.985356 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66238954 48.53% 48.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6780831 4.97% 53.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5636861 4.13% 57.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6036296 4.42% 62.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4884969 3.58% 65.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4157247 3.05% 68.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3216539 2.36% 71.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4148137 3.04% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35393351 25.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66141604 48.54% 48.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6763728 4.96% 53.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5687382 4.17% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6073172 4.46% 62.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4900819 3.60% 65.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4081259 3.00% 68.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3178170 2.33% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4143187 3.04% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35294730 25.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136493185 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305251 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325137 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45460656 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16697353 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66694244 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2556726 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5084206 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7272433 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69135 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401643990 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 218444 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5084206 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50968262 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1914523 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 308341 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63676495 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14541358 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393775984 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1667283 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10312278 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1126 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432122953 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2331950900 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1259654779 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1072296121 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136264051 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258976 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.324397 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45367973 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16681900 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66615179 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2549386 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5049613 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7322660 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69153 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 400837616 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 209818 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5049613 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50901379 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1945385 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 310174 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63573069 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14484431 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393292714 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1657143 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10217675 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 990 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 431691317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2328660715 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1256261052 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072399663 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47556760 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11781 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11780 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36361756 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103536184 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91503384 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4302647 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5369286 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384225176 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22747 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374106691 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1237893 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34434852 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 85933398 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 627 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136493185 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.740845 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.023746 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47125124 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11983 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11982 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36474755 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103439968 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91241620 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4261673 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5285781 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383905556 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22939 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373879260 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1212222 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34116216 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 85509152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 819 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136264051 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.743785 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.022773 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24947846 18.28% 18.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19979954 14.64% 32.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20599928 15.09% 48.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18110176 13.27% 61.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 23967090 17.56% 78.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15779150 11.56% 90.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8840932 6.48% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3358221 2.46% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 909888 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24800729 18.20% 18.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19931248 14.63% 32.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20555324 15.08% 47.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18170547 13.33% 61.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24015276 17.62% 78.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15694879 11.52% 90.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8802527 6.46% 96.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3373106 2.48% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 920415 0.68% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136493185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136264051 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8903 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8942 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4698 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -334,329 +334,329 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46069 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 45953 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7541 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 384 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 189821 1.07% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 6023 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241770 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7540 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 377 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190605 1.08% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 3637 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241259 1.36% 2.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9327128 52.38% 55.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7975640 44.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9279550 52.34% 55.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7945926 44.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126244558 33.75% 33.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174203 0.58% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6782034 1.81% 36.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8468832 2.26% 38.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3426641 0.92% 39.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1600511 0.43% 39.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20905751 5.59% 45.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7170121 1.92% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133236 1.91% 49.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101536664 27.14% 76.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88488853 23.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126287490 33.78% 33.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175875 0.58% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6775486 1.81% 36.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8466993 2.26% 38.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3427515 0.92% 39.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1596271 0.43% 39.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20850336 5.58% 45.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7171756 1.92% 47.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7125550 1.91% 49.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101538371 27.16% 76.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88288328 23.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374106691 # Type of FU issued -system.cpu.iq.rate 2.736374 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17807974 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047601 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654078451 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288293032 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250000264 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249673983 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130403978 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118157993 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263169120 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128745545 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11104268 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373879260 # Type of FU issued +system.cpu.iq.rate 2.739276 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17728490 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047418 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653579688 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 287780184 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249896445 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249383595 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130278814 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118034540 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263004554 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128603196 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11120232 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8887436 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 113793 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14364 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9127801 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8791220 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109151 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14386 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8866037 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 171663 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1472 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 183726 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1452 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5084206 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 279212 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 42812 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384249465 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 945099 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103536184 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91503384 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11713 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 308 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14364 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1301821 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 354554 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1656375 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370204175 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100335709 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3902516 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5049613 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 296711 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36519 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 383930075 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 867040 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103439968 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91241620 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11905 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 347 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 346 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14386 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1268963 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 369292 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1638255 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 369960329 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100240998 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3918931 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1542 # number of nop insts executed -system.cpu.iew.exec_refs 187704225 # number of memory reference insts executed -system.cpu.iew.exec_branches 38278467 # Number of branches executed -system.cpu.iew.exec_stores 87368516 # Number of stores executed -system.cpu.iew.exec_rate 2.707829 # Inst execution rate -system.cpu.iew.wb_sent 368827623 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368158257 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183056844 # num instructions producing a value -system.cpu.iew.wb_consumers 364050324 # num instructions consuming a value +system.cpu.iew.exec_nop 1580 # number of nop insts executed +system.cpu.iew.exec_refs 187474433 # number of memory reference insts executed +system.cpu.iew.exec_branches 31994663 # Number of branches executed +system.cpu.iew.exec_stores 87233435 # Number of stores executed +system.cpu.iew.exec_rate 2.710563 # Inst execution rate +system.cpu.iew.wb_sent 368586369 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 367930985 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182884452 # num instructions producing a value +system.cpu.iew.wb_consumers 363518435 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.692865 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502834 # average fanout of values written-back +system.cpu.iew.wb_rate 2.695695 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503095 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35184491 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34865105 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1583973 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131408979 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.656326 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.660791 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1563496 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131214438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.660264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659830 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34626776 26.35% 26.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28501850 21.69% 48.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13315357 10.13% 58.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11364955 8.65% 66.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13794993 10.50% 77.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7395322 5.63% 82.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3829564 2.91% 85.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3937630 3.00% 88.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14642532 11.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34444562 26.25% 26.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28434634 21.67% 47.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13308561 10.14% 58.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11464288 8.74% 66.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13753280 10.48% 77.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7411902 5.65% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3868194 2.95% 85.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3893489 2.97% 88.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14635528 11.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131408979 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131214438 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 177024331 # Number of memory references committed system.cpu.commit.loads 94648748 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 36546710 # Number of branches committed +system.cpu.commit.branches 30563497 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14642532 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14635528 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501013476 # The number of ROB reads -system.cpu.rob.rob_writes 773587232 # The number of ROB writes -system.cpu.timesIdled 6387 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223029 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 500506553 # The number of ROB reads +system.cpu.rob.rob_writes 772913753 # The number of ROB writes +system.cpu.timesIdled 6384 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 224310 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.500725 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.500725 # CPI: Total CPI of All Threads -system.cpu.ipc 1.997106 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.997106 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1769939132 # number of integer regfile reads -system.cpu.int_regfile_writes 232882500 # number of integer regfile writes -system.cpu.fp_regfile_reads 188356577 # number of floating regfile reads -system.cpu.fp_regfile_writes 132592082 # number of floating regfile writes -system.cpu.misc_regfile_reads 567391435 # number of misc regfile reads +system.cpu.cpi 0.499890 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.499890 # CPI: Total CPI of All Threads +system.cpu.ipc 2.000440 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.000440 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1768566472 # number of integer regfile reads +system.cpu.int_regfile_writes 232719908 # number of integer regfile writes +system.cpu.fp_regfile_reads 188077369 # number of floating regfile reads +system.cpu.fp_regfile_writes 132460333 # number of floating regfile writes +system.cpu.misc_regfile_reads 566743063 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.icache.replacements 13893 # number of replacements -system.cpu.icache.tagsinuse 1849.968594 # Cycle average of tags in use -system.cpu.icache.total_refs 37534809 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15782 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2378.330313 # Average number of references to valid blocks. +system.cpu.icache.replacements 13969 # number of replacements +system.cpu.icache.tagsinuse 1853.582812 # Cycle average of tags in use +system.cpu.icache.total_refs 37474292 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15862 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2362.519985 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1849.968594 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.903305 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.903305 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37534809 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37534809 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37534809 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37534809 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37534809 # number of overall hits -system.cpu.icache.overall_hits::total 37534809 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17059 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17059 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17059 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17059 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17059 # number of overall misses -system.cpu.icache.overall_misses::total 17059 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 362452498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 362452498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 362452498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 362452498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 362452498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 362452498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37551868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37551868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37551868 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37551868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37551868 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37551868 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000454 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000454 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000454 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000454 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000454 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000454 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21246.995603 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21246.995603 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21246.995603 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21246.995603 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 477 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1853.582812 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.905070 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.905070 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37474292 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37474292 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37474292 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37474292 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37474292 # number of overall hits +system.cpu.icache.overall_hits::total 37474292 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17149 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17149 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17149 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17149 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17149 # number of overall misses +system.cpu.icache.overall_misses::total 17149 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 365626498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 365626498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 365626498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 365626498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 365626498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 365626498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37491441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37491441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37491441 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37491441 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37491441 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37491441 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000457 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000457 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000457 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000457 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000457 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000457 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21320.572512 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21320.572512 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21320.572512 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21320.572512 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21320.572512 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21320.572512 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 571 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.058824 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.826087 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1275 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1275 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1275 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1275 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1275 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1275 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15784 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15784 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15784 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15784 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15784 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15784 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296328498 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 296328498 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296328498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 296328498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296328498 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 296328498 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000420 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000420 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000420 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18773.979853 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18773.979853 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1286 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1286 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1286 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1286 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1286 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1286 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15863 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15863 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15863 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15863 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15863 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15863 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298815998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 298815998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298815998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 298815998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298815998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 298815998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000423 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000423 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18837.294207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18837.294207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18837.294207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18837.294207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18837.294207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18837.294207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3956.608160 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13151 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.436273 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3972.424027 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13210 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5413 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.440421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 373.077110 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2771.508511 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 812.022538 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.084580 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.024781 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.120746 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12748 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 293 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13041 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1043 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1043 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12748 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 311 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13059 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12748 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 311 # number of overall hits -system.cpu.l2cache.overall_hits::total 13059 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3032 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1507 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4539 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 370.369860 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2790.334230 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 811.719937 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011303 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.085154 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.024772 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.121229 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12805 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 296 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13101 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1038 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1038 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12805 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 313 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13118 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12805 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 313 # number of overall hits +system.cpu.l2cache.overall_hits::total 13118 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3054 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1501 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4555 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2792 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2792 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3032 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2798 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2798 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3054 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 4299 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7331 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3032 # number of overall misses +system.cpu.l2cache.demand_misses::total 7353 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3054 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4299 # number of overall misses -system.cpu.l2cache.overall_misses::total 7331 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153017500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 82832500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 235850000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 135162000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 135162000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 153017500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 217994500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 371012000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 153017500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 217994500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 371012000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15780 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1800 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17580 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1043 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1043 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 7353 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 154851500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 81349000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 236200500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 135537500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 135537500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 154851500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 216886500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 371738000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 154851500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 216886500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 371738000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15859 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1797 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17656 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1038 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1038 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2810 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2810 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15780 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4610 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20390 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15780 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4610 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20390 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192142 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.837222 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.258191 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2815 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2815 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15859 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4612 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20471 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15859 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4612 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20471 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835281 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.257986 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993594 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.993594 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192142 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.932538 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.359539 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192142 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.932538 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.359539 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50467.513193 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54965.162575 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51960.784314 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48410.458453 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48410.458453 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50467.513193 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50708.187951 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50608.648206 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50467.513193 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50708.187951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50608.648206 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993961 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.993961 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192572 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.932134 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359191 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192572 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.932134 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359191 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50704.485920 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54196.535643 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51855.214050 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48440.850608 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48440.850608 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50704.485920 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50450.453594 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50555.963552 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50704.485920 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50450.453594 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50555.963552 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -666,176 +666,176 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 53 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 53 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1467 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4486 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3041 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1462 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4503 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2792 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2792 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3019 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4259 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3019 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7278 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115047807 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62983881 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178031688 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2798 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2798 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3041 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4260 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3041 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4260 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7301 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116555085 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61723123 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178278208 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100921221 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100921221 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115047807 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163905102 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 278952909 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115047807 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163905102 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 278952909 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101204481 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101204481 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116555085 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162927604 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 279482689 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116555085 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162927604 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 279482689 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191752 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813578 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255041 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38107.918847 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42933.797546 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.065091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993961 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993961 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191752 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923677 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356651 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191752 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923677 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356651 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38327.880631 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42218.278386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39590.985565 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36146.569126 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36146.569126 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36170.293424 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36170.293424 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38327.880631 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38245.916432 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38280.056020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38327.880631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38245.916432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38280.056020 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1413 # number of replacements -system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use -system.cpu.dcache.total_refs 170925187 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37077.047072 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1412 # number of replacements +system.cpu.dcache.tagsinuse 3109.263410 # Cycle average of tags in use +system.cpu.dcache.total_refs 170806114 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4612 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37035.150477 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3109.949983 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.759265 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.759265 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88871803 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88871803 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031525 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031525 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10952 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10952 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 3109.263410 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.759098 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.759098 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88752695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88752695 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031490 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031490 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11022 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11022 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170903328 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170903328 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170903328 # number of overall hits -system.cpu.dcache.overall_hits::total 170903328 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4023 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4023 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21140 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21140 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170784185 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170784185 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170784185 # number of overall hits +system.cpu.dcache.overall_hits::total 170784185 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4014 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4014 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21175 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21175 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25163 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25163 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25163 # number of overall misses -system.cpu.dcache.overall_misses::total 25163 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177641500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177641500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 874574146 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 874574146 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25189 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25189 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25189 # number of overall misses +system.cpu.dcache.overall_misses::total 25189 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 176938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 176938000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 876193651 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 876193651 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 116000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1052215646 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1052215646 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1052215646 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1052215646 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88875826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88875826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1053131651 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1053131651 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1053131651 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1053131651 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88756709 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88756709 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10954 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10954 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11024 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170928491 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170928491 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170928491 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170928491 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170809374 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170809374 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170809374 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170809374 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000183 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000183 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44156.475267 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44156.475267 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41370.584011 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41370.584011 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44080.219233 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44080.219233 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41378.684817 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41378.684817 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41815.985614 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41815.985614 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15531 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 796 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 449 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41809.188574 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41809.188574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41809.188574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41809.188574 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15380 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 834 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 443 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.590200 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.230769 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.717833 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 64.153846 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1043 # number of writebacks -system.cpu.dcache.writebacks::total 1043 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2222 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2222 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18329 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18329 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks +system.cpu.dcache.writebacks::total 1038 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2216 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2216 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18359 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18359 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20551 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20551 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20551 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20551 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1801 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1801 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2811 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2811 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87720000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 87720000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138213500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 138213500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 225933500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 225933500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 225933500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 225933500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20575 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20575 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20575 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20575 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1798 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1798 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2816 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2816 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4614 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4614 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4614 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4614 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86261500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86261500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138581500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 138581500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224843000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 224843000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224843000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 224843000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -844,14 +844,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48706.274292 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48706.274292 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49168.801138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49168.801138 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47976.362625 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47976.362625 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49212.180398 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49212.180398 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48730.602514 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48730.602514 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48730.602514 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48730.602514 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 89ba10791..0f1bf2663 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -527,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 63003fae2..a5e7d0a83 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 20:27:21 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Mar 3 2013 21:21:53 +gem5 started Mar 4 2013 01:12:21 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1387,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 625047295000 because target called exit() +Exiting @ tick 627439125000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 675c50cd2..2c1851d5a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.627778 # Number of seconds simulated -sim_ticks 627777658000 # Number of ticks simulated -final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.627439 # Number of seconds simulated +sim_ticks 627439125000 # Number of ticks simulated +final_tick 627439125000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109787 # Simulator instruction rate (inst/s) -host_op_rate 149515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49785649 # Simulator tick rate (ticks/s) -host_mem_usage 262368 # Number of bytes of host memory used -host_seconds 12609.61 # Real time elapsed on the host +host_inst_rate 96597 # Simulator instruction rate (inst/s) +host_op_rate 131552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43780556 # Simulator tick rate (ticks/s) +host_mem_usage 260984 # Number of bytes of host memory used +host_seconds 14331.46 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory -system.physmem.bytes_read::total 30397824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242368 # Number of bytes read from this memory +system.physmem.bytes_read::total 30397376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474959 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 246813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48174508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48421322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 246813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6738488 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6738488 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6738488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 246813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48174508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474966 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 247049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48199685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48446733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 247049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6742123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6742123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6742123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 247049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48199685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55188857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474959 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545372 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30397824 # Total number of bytes read from memory +system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30397376 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30397376 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4308 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis +system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4291 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29691 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29689 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 29720 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29747 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 29651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29680 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29627 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29682 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29602 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 29611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29633 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29649 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4133 # Tr system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 627777588500 # Total gap between requests +system.physmem.totGap 627439056500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 474966 # Categorize read packet sizes +system.physmem.readPktSize::6 474959 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,12 +92,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 66098 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 405906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -156,36 +156,36 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3182824500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 21162788250 # Sum of mem lat for all requests -system.physmem.totBusLat 2374030000 # Total cycles spent in databus access -system.physmem.totBankLat 15605933750 # Total cycles spent in bank access -system.physmem.avgQLat 6703.42 # Average queueing delay per request -system.physmem.avgBankLat 32868.02 # Average bank access latency per request +system.physmem.totQLat 3462811500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 21441489000 # Sum of mem lat for all requests +system.physmem.totBusLat 2374050000 # Total cycles spent in databus access +system.physmem.totBankLat 15604627500 # Total cycles spent in bank access +system.physmem.avgQLat 7293.05 # Average queueing delay per request +system.physmem.avgBankLat 32864.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 44571.44 # Average memory access latency -system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 45158.04 # Average memory access latency +system.physmem.avgRdBW 48.45 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.45 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time system.physmem.avgWrQLen 17.42 # Average write queue length over time -system.physmem.readRowHits 143321 # Number of row buffer hits during reads -system.physmem.writeRowHits 45521 # Number of row buffer hits during writes +system.physmem.readRowHits 143341 # Number of row buffer hits during reads +system.physmem.writeRowHits 45511 # Number of row buffer hits during writes system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes -system.physmem.avgGap 1160264.94 # Average gap between requests -system.cpu.branchPred.lookups 438315942 # Number of BP lookups -system.cpu.branchPred.condPredicted 349727890 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30635219 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 247833723 # Number of BTB lookups -system.cpu.branchPred.BTBHits 226959266 # Number of BTB hits +system.physmem.writeRowHitRate 68.85 # Row buffer hit rate for writes +system.physmem.avgGap 1159654.26 # Average gap between requests +system.cpu.branchPred.lookups 440649573 # Number of BP lookups +system.cpu.branchPred.condPredicted 353682166 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30631043 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 252533039 # Number of BTB lookups +system.cpu.branchPred.BTBHits 230279415 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806740 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.187837 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 51764959 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806562 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,100 +229,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1255555317 # number of cpu cycles simulated +system.cpu.numCycles 1254878251 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 353470076 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2285596018 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438315942 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 279264180 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 600835401 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 132517239 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 333121635 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10719821 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1213961612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.592462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 354654463 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2286055838 # Number of instructions fetch has processed +system.cpu.fetch.Branches 440649573 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 282044374 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 601927539 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 156613440 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 130193180 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 518 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 10572 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 335557697 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11970074 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1212716808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.588686 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.181757 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 613170569 50.51% 50.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42771992 3.52% 54.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 71974346 5.93% 72.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 42167023 3.47% 75.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30997748 2.55% 78.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 230060886 18.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 610833811 50.37% 50.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43093126 3.55% 53.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 96161904 7.93% 61.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 57061464 4.71% 66.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 71748155 5.92% 72.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 43390011 3.58% 76.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30893705 2.55% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 32839857 2.71% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226694775 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1213961612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 402973570 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105164432 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561876513 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16833922 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 127113175 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44705454 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3047243320 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 127113175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 438520828 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34437480 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 439400 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 541081761 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72368968 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2975054899 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4810930 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 57090211 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 1212716808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.351149 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.821735 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 405646781 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 102637713 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 561793047 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16722466 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 125916801 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44665335 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13931 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3029413956 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28108 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 125916801 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 441580002 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34476908 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 437379 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 540507560 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 69798158 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2946364126 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4812832 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 54672934 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2946030115 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14164064845 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13593631976 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 570432869 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 2931066413 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14023290204 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13452684524 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570605680 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 952890025 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25236 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 195466614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 973207403 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 490834559 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40613980 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2806590515 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2437414876 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13391013 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 908731819 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2361150824 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1213961612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.007819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875089 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 937926323 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 22415 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19926 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 179121288 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 970649993 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 487168712 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36377618 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40069949 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2792240287 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29328 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2432835777 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13263841 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 894381457 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2312630775 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 7944 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1212716808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.006104 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 377942739 31.13% 31.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183591536 15.12% 46.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 202672014 16.70% 62.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169721523 13.98% 76.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132842970 10.94% 87.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 93759245 7.72% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37926008 3.12% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12454026 1.03% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 376728714 31.06% 31.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183811265 15.16% 46.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 203907049 16.81% 63.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169580498 13.98% 77.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132860198 10.96% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92416507 7.62% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37964146 3.13% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12426731 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3021700 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1213961612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1212716808 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 716116 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24381 0.03% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available @@ -350,322 +350,322 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55152382 62.89% 63.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55122687 62.92% 63.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31746374 36.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1108357154 45.47% 45.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502588 0.23% 46.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23405386 0.96% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838249094 34.39% 81.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442425361 18.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1103971506 45.38% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223452 0.46% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502427 0.23% 46.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23409752 0.96% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838269607 34.46% 81.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442207267 18.18% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2437414876 # Type of FU issued -system.cpu.iq.rate 1.941304 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87694306 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6067362312 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3632711697 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2254358254 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122514371 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82707334 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56439819 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2461788341 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63320841 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84306513 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2432835777 # Type of FU issued +system.cpu.iq.rate 1.938703 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87609558 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036011 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6056740662 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3603968769 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2248867979 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122521099 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82749412 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56444030 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2457121441 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63323894 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84335781 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 341820222 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8583 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429956 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 213839262 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 339262812 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8485 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1431215 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 210173415 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 127113175 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12638633 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1558332 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2806632387 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 973207403 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 490834559 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1554341 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 125916801 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12646480 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1559895 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2792282007 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1384453 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 970649993 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 487168712 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19342 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1555909 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429956 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32461974 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33956380 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2363518752 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792548156 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 1431215 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32433063 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1530059 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 33963122 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2358070725 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792574818 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 74765052 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12468 # number of nop insts executed -system.cpu.iew.exec_refs 1216269086 # number of memory reference insts executed -system.cpu.iew.exec_branches 322574286 # Number of branches executed -system.cpu.iew.exec_stores 423720930 # Number of stores executed -system.cpu.iew.exec_rate 1.882449 # Inst execution rate -system.cpu.iew.wb_sent 2336489228 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2310798073 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347631579 # num instructions producing a value -system.cpu.iew.wb_consumers 2523967689 # num instructions consuming a value +system.cpu.iew.exec_nop 12392 # number of nop insts executed +system.cpu.iew.exec_refs 1216182478 # number of memory reference insts executed +system.cpu.iew.exec_branches 319878188 # Number of branches executed +system.cpu.iew.exec_stores 423607660 # Number of stores executed +system.cpu.iew.exec_rate 1.879123 # Inst execution rate +system.cpu.iew.wb_sent 2331089515 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2305312009 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347373640 # num instructions producing a value +system.cpu.iew.wb_consumers 2522763992 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back +system.cpu.iew.wb_rate 1.837080 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534086 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 921296175 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 906945779 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30621418 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1086848437 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.734682 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.398805 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30617374 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1086800007 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.734759 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.398832 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 446548721 41.09% 41.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288590719 26.55% 67.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95114953 8.75% 76.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46461870 4.27% 87.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22187798 2.04% 89.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15847039 1.46% 90.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10983692 1.01% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90884050 8.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 446471329 41.08% 41.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288644992 26.56% 67.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95109223 8.75% 76.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70211025 6.46% 82.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46444999 4.27% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22203598 2.04% 89.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15846659 1.46% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10983551 1.01% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90884631 8.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1086848437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1086800007 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 908382478 # Number of memory references committed system.cpu.commit.loads 631387181 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299634395 # Number of branches committed +system.cpu.commit.branches 298259106 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90884050 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90884631 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3802578575 # The number of ROB reads -system.cpu.rob.rob_writes 5740389473 # The number of ROB writes -system.cpu.timesIdled 353174 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41593705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3788179168 # The number of ROB reads +system.cpu.rob.rob_writes 5710492063 # The number of ROB writes +system.cpu.timesIdled 353297 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42161443 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.906950 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11774707263 # number of integer regfile reads -system.cpu.int_regfile_writes 2226782267 # number of integer regfile writes -system.cpu.fp_regfile_reads 68797357 # number of floating regfile reads -system.cpu.fp_regfile_writes 49551943 # number of floating regfile writes -system.cpu.misc_regfile_reads 1364040345 # number of misc regfile reads +system.cpu.cpi 0.906461 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.906461 # CPI: Total CPI of All Threads +system.cpu.ipc 1.103191 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.103191 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11756795674 # number of integer regfile reads +system.cpu.int_regfile_writes 2218922402 # number of integer regfile writes +system.cpu.fp_regfile_reads 68796713 # number of floating regfile reads +system.cpu.fp_regfile_writes 49556201 # number of floating regfile writes +system.cpu.misc_regfile_reads 1363984791 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.icache.replacements 22740 # number of replacements -system.cpu.icache.tagsinuse 1642.119596 # Cycle average of tags in use -system.cpu.icache.total_refs 333085977 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13639.884398 # Average number of references to valid blocks. +system.cpu.icache.replacements 22806 # number of replacements +system.cpu.icache.tagsinuse 1643.708828 # Cycle average of tags in use +system.cpu.icache.total_refs 335522072 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24489 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13700.929887 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1642.119596 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 333090004 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 333090004 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 333090004 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 333090004 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 333090004 # number of overall hits -system.cpu.icache.overall_hits::total 333090004 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 31630 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 31630 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 31630 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 31630 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 31630 # number of overall misses -system.cpu.icache.overall_misses::total 31630 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 481232999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 481232999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 481232999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 481232999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 481232999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 481232999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 333121634 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 333121634 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 333121634 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 333121634 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 333121634 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 333121634 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15214.448277 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15214.448277 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15214.448277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15214.448277 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1643.708828 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.802592 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.802592 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 335526084 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 335526084 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 335526084 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 335526084 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 335526084 # number of overall hits +system.cpu.icache.overall_hits::total 335526084 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31612 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31612 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31612 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31612 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31612 # number of overall misses +system.cpu.icache.overall_misses::total 31612 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 479792499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 479792499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 479792499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 479792499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 479792499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 479792499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 335557696 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 335557696 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 335557696 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 335557696 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 335557696 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 335557696 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15177.543306 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15177.543306 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15177.543306 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15177.543306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15177.543306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15177.543306 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 835 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.692308 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2899 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2899 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2899 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2899 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2899 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28731 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28731 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28731 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28731 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28731 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28731 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386564499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 386564499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386564499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 386564499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386564499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 386564499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2827 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2827 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2827 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2827 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2827 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28785 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28785 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28785 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28785 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28785 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28785 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386126499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 386126499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386126499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 386126499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386126499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 386126499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13454.613449 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13454.613449 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13414.156644 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13414.156644 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13414.156644 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13414.156644 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13414.156644 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13414.156644 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 442184 # number of replacements -system.cpu.l2cache.tagsinuse 32692.574562 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1110053 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 474931 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.337293 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 442178 # number of replacements +system.cpu.l2cache.tagsinuse 32692.553116 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1110010 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 474925 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.337232 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1286.532429 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 50.222145 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31355.819987 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039262 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 1287.010485 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 50.235756 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31355.306875 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039276 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001533 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.956904 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.956888 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.997698 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21996 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1058215 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1080211 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96321 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96321 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6442 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6442 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21996 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1064657 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1086653 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21996 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1064657 # number of overall hits -system.cpu.l2cache.overall_hits::total 1086653 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2425 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406491 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408916 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4308 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4308 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2425 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 472566 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 474991 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2425 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 472566 # number of overall misses -system.cpu.l2cache.overall_misses::total 474991 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 133322500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28783806000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28917128500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174251000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3174251000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 133322500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 31958057000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32091379500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 133322500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 31958057000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32091379500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 24421 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1464706 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1489127 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 96321 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96321 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4311 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4311 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 72517 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72517 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 24421 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1537223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1561644 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 24421 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1537223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1561644 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099300 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277524 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.274601 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999304 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999304 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911166 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911166 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099300 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.307415 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.304161 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099300 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.307415 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.304161 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54978.350515 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70810.438607 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70716.549365 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.121075 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.121075 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67562.079071 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67562.079071 # average overall miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 22064 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1058101 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1080165 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 96323 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 96323 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 22064 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1064542 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1086606 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 22064 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1064542 # number of overall hits +system.cpu.l2cache.overall_hits::total 1086606 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2426 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 406486 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 408912 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4291 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4291 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66074 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66074 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2426 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 472560 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 474986 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2426 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 472560 # number of overall misses +system.cpu.l2cache.overall_misses::total 474986 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132157500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29065267000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29197424500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174202000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3174202000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 132157500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 32239469000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32371626500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 132157500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 32239469000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32371626500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 24490 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1464587 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1489077 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 96323 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 96323 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4296 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4296 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72515 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72515 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 24490 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1537102 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1561592 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 24490 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1537102 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1561592 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099061 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277543 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.274608 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.998836 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.998836 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911177 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911177 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099061 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.307436 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.304168 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099061 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.307436 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.304168 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54475.474031 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71503.734446 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71402.708896 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.106547 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.106547 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54475.474031 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68223.017183 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68152.801346 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54475.474031 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68223.017183 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68152.801346 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -677,122 +677,122 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2421 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406470 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408891 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4308 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4308 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2421 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 472545 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 474966 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2421 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 474966 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103134689 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729007693 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832142382 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43084308 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43084308 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2357071286 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2357071286 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103134689 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086078979 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26189213668 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103134689 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086078979 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26189213668 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277510 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999304 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999304 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.304145 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.304145 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.036762 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58378.251022 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58284.829898 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406463 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 408885 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4291 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4291 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66074 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66074 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2422 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 472537 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 474959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2422 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 472537 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 474959 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 101956685 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24008915183 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24110871868 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42914291 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42914291 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2357034286 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2357034286 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101956685 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26365949469 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26467906154 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101956685 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26365949469 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26467906154 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098898 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277527 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998836 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.998836 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911177 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911177 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098898 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307421 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304151 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098898 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307421 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304151 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42096.071429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59067.898389 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58967.367030 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.664185 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.664185 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.644096 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.644096 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42096.071429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55796.582001 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55726.717788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42096.071429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55796.582001 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55726.717788 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533127 # number of replacements -system.cpu.dcache.tagsinuse 4094.656080 # Cycle average of tags in use -system.cpu.dcache.total_refs 969988245 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 631.000346 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1533005 # number of replacements +system.cpu.dcache.tagsinuse 4094.655355 # Cycle average of tags in use +system.cpu.dcache.total_refs 969956043 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537101 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 631.029479 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.656080 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4094.655355 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 693861536 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693861536 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276093810 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276093810 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 693829407 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693829407 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276093791 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276093791 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 969955346 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 969955346 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 969955346 # number of overall hits -system.cpu.dcache.overall_hits::total 969955346 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1953541 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1953541 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 841868 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 841868 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 969923198 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 969923198 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 969923198 # number of overall hits +system.cpu.dcache.overall_hits::total 969923198 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953276 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953276 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 841887 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 841887 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2795409 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2795409 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2795409 # number of overall misses -system.cpu.dcache.overall_misses::total 2795409 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 66484216000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 66484216000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39427025969 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39427025969 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105911241969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105911241969 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105911241969 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105911241969 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695815077 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695815077 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2795163 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795163 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795163 # number of overall misses +system.cpu.dcache.overall_misses::total 2795163 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 66762023500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 66762023500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39426392469 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39426392469 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106188415969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106188415969 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106188415969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106188415969 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695782683 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695782683 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972750755 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972750755 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972750755 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972750755 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 972718361 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972718361 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972718361 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972718361 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003040 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses @@ -801,52 +801,52 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34032.669906 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34032.669906 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46832.788476 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46832.788476 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37887.565637 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37887.565637 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34179.513545 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34179.513545 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46830.979061 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46830.979061 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37990.062107 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37990.062107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37990.062107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37990.062107 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 726 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 90 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807018 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.300000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.157303 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96321 # number of writebacks -system.cpu.dcache.writebacks::total 96321 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765041 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765041 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96323 # number of writebacks +system.cpu.dcache.writebacks::total 96323 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488688 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 488688 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765077 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765077 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1253875 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1253875 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1253875 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1253875 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76827 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76827 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541534 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541534 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541534 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541534 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831573000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831573000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409419500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409419500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240992500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44240992500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240992500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44240992500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1253765 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1253765 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1253765 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1253765 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464588 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464588 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76810 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76810 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541398 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541398 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541398 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541398 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41111704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41111704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3408970500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3408970500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44520674500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44520674500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44520674500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44520674500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses @@ -855,14 +855,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.956279 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.956279 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44377.881474 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44377.881474 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28070.490814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28070.490814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44381.857831 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44381.857831 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28883.308853 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28883.308853 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28883.308853 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28883.308853 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 0d9336fbc..39e20487b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -527,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr index e45cd058f..b6a1a957f 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4] hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index b7ae68a85..9f7f9be51 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,13 +1,11 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 20:59:12 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Mar 3 2013 21:21:53 +gem5 started Mar 4 2013 01:35:26 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 26275145500 because target called exit() +Exiting @ tick 25578307500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index bd8287e69..6f25374e1 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.025578 # Number of seconds simulated -sim_ticks 25577832000 # Number of ticks simulated -final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25578307500 # Number of ticks simulated +final_tick 25578307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133487 # Simulator instruction rate (inst/s) -host_op_rate 189436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48151664 # Simulator tick rate (ticks/s) -host_mem_usage 268312 # Number of bytes of host memory used -host_seconds 531.19 # Real time elapsed on the host +host_inst_rate 122516 # Simulator instruction rate (inst/s) +host_op_rate 173866 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44194830 # Simulator tick rate (ticks/s) +host_mem_usage 267056 # Number of bytes of host memory used +host_seconds 578.76 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372416 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128779 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83944 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83944 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11662599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 310563929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 322226528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11662599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11662599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 210041883 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 210041883 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 210041883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11662599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 310563929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 532268411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128779 # Total number of read requests seen -system.physmem.writeReqs 83944 # Total number of write requests seen -system.physmem.cpureqs 213035 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8241856 # Total number of bytes read from memory -system.physmem.bytesWritten 5372416 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8241856 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372416 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372288 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128774 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83942 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83942 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11654876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 310553151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 322208027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11654876 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11654876 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 210032974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 210032974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 210032974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11654876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 310553151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 532241001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128775 # Total number of read requests seen +system.physmem.writeReqs 83942 # Total number of write requests seen +system.physmem.cpureqs 213036 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8241536 # Total number of bytes read from memory +system.physmem.bytesWritten 5372288 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8241536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372288 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 7976 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8062 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8171 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 319 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 7977 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8064 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8170 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8108 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7993 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8127 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8038 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8126 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8035 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7981 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7987 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 5142 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5371 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5372 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5263 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5277 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5350 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5133 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25577735000 # Total gap between requests +system.physmem.totGap 25578289000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128779 # Categorize read packet sizes +system.physmem.readPktSize::6 128775 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83944 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83942 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 70073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,11 +124,11 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3640 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -139,53 +139,53 @@ system.physmem.wrQLenPdf::11 3650 # Wh system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests -system.physmem.totBusLat 643885000 # Total cycles spent in databus access -system.physmem.totBankLat 1400217500 # Total cycles spent in bank access -system.physmem.avgQLat 24884.85 # Average queueing delay per request -system.physmem.avgBankLat 10873.20 # Average bank access latency per request +system.physmem.totQLat 3208033250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5250782000 # Sum of mem lat for all requests +system.physmem.totBusLat 643865000 # Total cycles spent in databus access +system.physmem.totBankLat 1398883750 # Total cycles spent in bank access +system.physmem.avgQLat 24912.31 # Average queueing delay per request +system.physmem.avgBankLat 10863.18 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40758.05 # Average memory access latency -system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 210.04 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 40775.49 # Average memory access latency +system.physmem.avgRdBW 322.21 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 210.03 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 322.21 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 210.03 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 4.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.21 # Average read queue length over time -system.physmem.avgWrQLen 9.73 # Average write queue length over time -system.physmem.readRowHits 116758 # Number of row buffer hits during reads -system.physmem.writeRowHits 52879 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.59 # Average write queue length over time +system.physmem.readRowHits 116753 # Number of row buffer hits during reads +system.physmem.writeRowHits 52875 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes -system.physmem.avgGap 120239.63 # Average gap between requests -system.cpu.branchPred.lookups 16629564 # Number of BP lookups -system.cpu.branchPred.condPredicted 12762911 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 603280 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10503277 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7769578 # Number of BTB hits +system.physmem.avgGap 120245.63 # Average gap between requests +system.cpu.branchPred.lookups 16623364 # Number of BP lookups +system.cpu.branchPred.condPredicted 12760071 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 602765 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10462695 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7764975 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.972894 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825196 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113459 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 74.215821 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1825729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113390 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +229,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 51155665 # number of cpu cycles simulated +system.cpu.numCycles 51156616 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12528030 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85177625 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16623364 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9590704 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21186632 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2363015 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10581483 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 556 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11675113 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179601 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46030680 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.591102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335075 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466538 3.19% 70.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1380808 3.00% 73.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 959441 2.08% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1192836 2.59% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24864286 54.02% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2136700 4.64% 58.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1964680 4.27% 62.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2042011 4.44% 67.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1465176 3.18% 70.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1378812 3.00% 73.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 958023 2.08% 75.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1192746 2.59% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10028246 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46030680 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324950 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.665036 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14611647 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8930047 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19464619 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1393461 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1630906 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3329793 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104768 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116826129 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 364020 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1630906 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16323488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2561901 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 880060 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19095828 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5538497 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114955733 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 140 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 16360 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4684188 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 269 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115265758 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529627924 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529622592 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 274406 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16133086 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20210 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13085457 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29620481 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22434207 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3897313 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4409985 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111515856 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35838 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107234062 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 271666 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10778201 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25823888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2052 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46030680 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.329622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.987561 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10772740 23.40% 23.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8089543 17.57% 40.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7436956 16.16% 57.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7132439 15.49% 72.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5411666 11.76% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3908589 8.49% 92.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1839107 4.00% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 868081 1.89% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 571559 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46030680 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112263 4.55% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1357458 55.03% 59.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 996979 40.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56638968 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91700 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56624593 52.80% 52.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91608 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 212 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 187 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued @@ -384,292 +384,292 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28903478 26.95% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21630689 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28897959 26.95% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21619708 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued -system.cpu.iq.rate 2.096836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107234062 # Type of FU issued +system.cpu.iq.rate 2.096191 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2466700 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023003 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263236655 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122357738 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105553758 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 515 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109700502 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2179129 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2321749 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6850 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30026 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1892744 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2313373 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29813 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1878469 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 507 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1630906 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1049242 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45608 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111561445 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 293593 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29620481 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22434207 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19918 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6795 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5249 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29813 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 391440 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181697 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573137 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106207608 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28598944 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1026454 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9761 # number of nop insts executed -system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed -system.cpu.iew.exec_branches 14602542 # Number of branches executed -system.cpu.iew.exec_stores 21344564 # Number of stores executed -system.cpu.iew.exec_rate 2.076700 # Inst execution rate -system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53282087 # num instructions producing a value -system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value +system.cpu.iew.exec_nop 9751 # number of nop insts executed +system.cpu.iew.exec_refs 49933957 # number of memory reference insts executed +system.cpu.iew.exec_branches 14599960 # Number of branches executed +system.cpu.iew.exec_stores 21335013 # Number of stores executed +system.cpu.iew.exec_rate 2.076127 # Inst execution rate +system.cpu.iew.wb_sent 105772826 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105553928 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53290488 # num instructions producing a value +system.cpu.iew.wb_consumers 103570522 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back +system.cpu.iew.wb_rate 2.063349 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514533 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10929916 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 499809 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44399774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.266508 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764024 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15322992 34.51% 34.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11640164 26.22% 60.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3466305 7.81% 68.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2879897 6.49% 75.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880990 4.24% 79.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1948005 4.39% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685170 1.54% 85.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 565050 1.27% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6011201 13.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44399774 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 47862846 # Number of memory references committed system.cpu.commit.loads 27307108 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13741505 # Number of branches committed +system.cpu.commit.branches 13741485 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6011201 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149959530 # The number of ROB reads -system.cpu.rob.rob_writes 224865260 # The number of ROB writes -system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 149925618 # The number of ROB reads +system.cpu.rob.rob_writes 224764611 # The number of ROB writes +system.cpu.timesIdled 74074 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5125936 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.721441 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads -system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511661173 # number of integer regfile reads -system.cpu.int_regfile_writes 103341311 # number of integer regfile writes -system.cpu.fp_regfile_reads 804 # number of floating regfile reads -system.cpu.fp_regfile_writes 688 # number of floating regfile writes -system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads +system.cpu.cpi 0.721454 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.721454 # CPI: Total CPI of All Threads +system.cpu.ipc 1.386089 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.386089 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511542927 # number of integer regfile reads +system.cpu.int_regfile_writes 103323311 # number of integer regfile writes +system.cpu.fp_regfile_reads 788 # number of floating regfile reads +system.cpu.fp_regfile_writes 660 # number of floating regfile writes +system.cpu.misc_regfile_reads 49174075 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.icache.replacements 28586 # number of replacements -system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use -system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks. +system.cpu.icache.replacements 28620 # number of replacements +system.cpu.icache.tagsinuse 1814.212486 # Cycle average of tags in use +system.cpu.icache.total_refs 11640356 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30656 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 379.708899 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11645446 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11645446 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11645446 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11645446 # number of overall hits -system.cpu.icache.overall_hits::total 11645446 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34686 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34686 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34686 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses -system.cpu.icache.overall_misses::total 34686 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11680132 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11680132 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11680132 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002970 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002970 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1814.212486 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885846 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885846 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11640361 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11640361 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11640361 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11640361 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11640361 # number of overall hits +system.cpu.icache.overall_hits::total 11640361 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34752 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34752 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34752 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34752 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34752 # number of overall misses +system.cpu.icache.overall_misses::total 34752 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 732057000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 732057000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 732057000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 732057000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 732057000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 732057000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11675113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11675113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11675113 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11675113 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11675113 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11675113 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002977 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002977 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002977 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002977 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002977 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002977 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21065.176105 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21065.176105 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21065.176105 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21065.176105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21065.176105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21065.176105 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 767 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 30.440000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.958333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3741 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3741 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3741 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3741 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3741 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3741 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30945 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 30945 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 30945 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3763 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3763 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3763 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3763 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3763 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3763 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30989 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 30989 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 30989 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 30989 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 30989 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 30989 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 594458000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 594458000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 594458000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 594458000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 594458000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 594458000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002654 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002654 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002654 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19182.871341 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19182.871341 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19182.871341 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19182.871341 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19182.871341 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19182.871341 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 95649 # number of replacements -system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use -system.cpu.l2cache.total_refs 88124 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 126758 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.695215 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 95644 # number of replacements +system.cpu.l2cache.tagsinuse 30089.524370 # Cycle average of tags in use +system.cpu.l2cache.total_refs 88146 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 126756 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.695399 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.822011 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.041948 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.054317 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.918275 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 25825 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33460 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 59285 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129109 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129109 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4785 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4785 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 25825 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 38245 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 64070 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 25825 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 38245 # number of overall hits -system.cpu.l2cache.overall_hits::total 64070 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4676 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21922 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26598 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 312 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 312 # number of UpgradeReq misses +system.cpu.l2cache.occ_blocks::writebacks 26934.597461 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1374.602931 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1780.323979 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.821979 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.041950 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.054331 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.918259 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 25863 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33463 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 59326 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 129088 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 129088 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 19 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 19 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4769 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4769 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 25863 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 38232 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 64095 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 25863 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 38232 # number of overall hits +system.cpu.l2cache.overall_hits::total 64095 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4674 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21921 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26595 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 319 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 319 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 102257 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 102257 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4676 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124179 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128855 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4676 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124179 # number of overall misses -system.cpu.l2cache.overall_misses::total 128855 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses::cpu.inst 4674 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 124178 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128852 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4674 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 124178 # number of overall misses +system.cpu.l2cache.overall_misses::total 128852 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 304002000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1479409000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1783411000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6641217500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 30501 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55382 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 85883 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 129109 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 129109 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 332 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 332 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107042 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107042 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 30501 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 162424 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 192925 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 30501 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 162424 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 192925 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.153306 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395833 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.309700 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.939759 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.939759 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955298 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955298 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153306 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.764536 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.667902 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153306 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.764536 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.667902 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.717949 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.717949 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6653931500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6653931500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 304002000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8133340500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8437342500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 304002000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8133340500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8437342500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 30537 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55384 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 85921 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 129088 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 129088 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 338 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 338 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107026 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107026 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 30537 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 162410 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 192947 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 30537 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 162410 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 192947 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.153060 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395800 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.309529 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.943787 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.943787 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955441 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955441 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153060 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.764596 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.667810 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153060 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.764596 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.667810 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65041.078306 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67488.207655 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67058.131228 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 72.100313 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 72.100313 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65070.669979 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65070.669979 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65041.078306 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65497.435133 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65480.881166 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65041.078306 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65497.435133 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65480.881166 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -678,195 +678,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83944 # number of writebacks -system.cpu.l2cache.writebacks::total 83944 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83942 # number of writebacks +system.cpu.l2cache.writebacks::total 83942 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21861 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26522 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 312 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 312 # number of UpgradeReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4659 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21859 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26518 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 319 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 319 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128779 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251555285 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461018603 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5385248857 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.939759 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.939759 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955298 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955298 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4659 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124116 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128775 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4659 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124116 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128775 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 245046791 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1206365816 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1451412607 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3199316 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3199316 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5398042204 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5398042204 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245046791 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6604408020 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6849454811 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245046791 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6604408020 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6849454811 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394681 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308632 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.943787 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.943787 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955441 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955441 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764214 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.667411 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764214 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.667411 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52596.435072 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55188.518047 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54733.109850 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.203762 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.203762 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52788.974877 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52788.974877 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52596.435072 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53211.576429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53189.320994 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52596.435072 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53211.576429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53189.320994 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158328 # number of replacements -system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use -system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158314 # number of replacements +system.cpu.dcache.tagsinuse 4072.315596 # Cycle average of tags in use +system.cpu.dcache.total_refs 44364658 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162410 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.164571 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4072.315596 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 26064858 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26064858 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267205 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267205 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits -system.cpu.dcache.overall_hits::total 44337915 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 44332063 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44332063 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44332063 # number of overall hits +system.cpu.dcache.overall_hits::total 44332063 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124444 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124444 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582696 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582696 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses -system.cpu.dcache.overall_misses::total 1707154 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4246899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1707140 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707140 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707140 # number of overall misses +system.cpu.dcache.overall_misses::total 1707140 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4243660500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4243660500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98452063982 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98452063982 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1297000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1297000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102695724482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102695724482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102695724482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102695724482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26189302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26189302 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16026 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16026 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16031 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16031 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46045069 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46045069 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46045069 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46045069 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46039203 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46039203 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46039203 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46039203 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079732 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079732 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002808 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002808 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079733 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079733 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002807 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002807 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037080 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037080 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037080 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037080 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34100.965093 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34100.965093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62205.290202 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62205.290202 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28822.222222 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28822.222222 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60156.592009 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60156.592009 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5240 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.352459 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.305785 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks -system.cpu.dcache.writebacks::total 129109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 129088 # number of writebacks +system.cpu.dcache.writebacks::total 129088 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69028 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69028 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475364 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475364 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107343 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162756 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1544392 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544392 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544392 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544392 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55416 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55416 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162748 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162748 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162748 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162748 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1874890000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1874890000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6816019991 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6816019991 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8690909991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8690909991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8690909991 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8690909991 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33833.008517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33833.008517 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63504.080712 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63504.080712 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index b3f283cca..c948b1f36 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -527,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index fa5d435db..8a302018f 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 21:12:52 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Mar 3 2013 21:21:53 +gem5 started Mar 4 2013 01:41:28 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 506353996500 because target called exit() +Exiting @ tick 517371024000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index dd9108dcd..8f6283962 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517371 # Nu sim_ticks 517371024000 # Number of ticks simulated final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170437 # Simulator instruction rate (inst/s) -host_op_rate 190135 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57090080 # Simulator tick rate (ticks/s) -host_mem_usage 485276 # Number of bytes of host memory used -host_seconds 9062.36 # Real time elapsed on the host +host_inst_rate 139447 # Simulator instruction rate (inst/s) +host_op_rate 155563 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46709499 # Simulator tick rate (ticks/s) +host_mem_usage 485516 # Number of bytes of host memory used +host_seconds 11076.36 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory @@ -177,13 +177,13 @@ system.physmem.writeRowHits 271156 # Nu system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes system.physmem.avgGap 154562.37 # Average gap between requests -system.cpu.branchPred.lookups 303290886 # Number of BP lookups +system.cpu.branchPred.lookups 303290873 # Number of BP lookups system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 174596646 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 174596633 # Number of BTB lookups system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.481336 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.481343 # BTB Hit Percentage system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -234,7 +234,7 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303290886 # Number of branches that fetch encountered +system.cpu.fetch.Branches 303290873 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing @@ -430,7 +430,7 @@ system.cpu.iew.iewExecSquashedInsts 29996171 # Nu system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 130 # number of nop insts executed system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed -system.cpu.iew.exec_branches 238330381 # Number of branches executed +system.cpu.iew.exec_branches 238330373 # Number of branches executed system.cpu.iew.exec_stores 190143920 # Number of stores executed system.cpu.iew.exec_rate 1.921365 # Inst execution rate system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit |