diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:42 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:42 -0400 |
| commit | 55dce6419dbcc2ea37802c5b8688bdd5299505b9 (patch) | |
| tree | c8219e0cd1b00870c506d392ed8554cf3a9d7a61 /tests | |
| parent | 477e7039b36dc816bf1116631ace714d0c83dd21 (diff) | |
| download | gem5-55dce6419dbcc2ea37802c5b8688bdd5299505b9.tar.xz | |
inorder: update SE regressions
Diffstat (limited to 'tests')
19 files changed, 1703 insertions, 1731 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr index 79a2396a6..1b49765a7 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr @@ -1,11 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout index ff066f3a4..52e5d9fa3 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:58:24 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing +gem5 compiled Jun 19 2011 06:59:13 +gem5 started Jun 19 2011 07:12:22 +gem5 executing on m60-009.pool +command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -43,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 261641972500 because target called exit() +Exiting @ tick 279017416500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 74577bc37..a0423dfde 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,301 +1,304 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 209357 # Simulator instruction rate (inst/s) -host_mem_usage 403360 # Number of bytes of host memory used -host_seconds 2874.78 # Real time elapsed on the host -host_tick_rate 91012809 # Simulator tick rate (ticks/s) +sim_seconds 0.279017 # Number of seconds simulated +sim_ticks 279017416500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 128000 # Simulator instruction rate (inst/s) +host_tick_rate 59339940 # Simulator tick rate (ticks/s) +host_mem_usage 192984 # Number of bytes of host memory used +host_seconds 4702.02 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.261642 # Number of seconds simulated -sim_ticks 261641972500 # Number of ticks simulated -system.cpu.activity 88.058146 # Percentage of cycles cpu is active -system.cpu.agen_unit.agens 155868116 # Number of Address Generations -system.cpu.branch_predictor.BTBHitPct 90.344266 # BTB Hit Percentage -system.cpu.branch_predictor.BTBHits 29143677 # Number of BTB hits -system.cpu.branch_predictor.BTBLookups 32258469 # Number of BTB lookups -system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.condIncorrect 22153653 # Number of conditional branches incorrect -system.cpu.branch_predictor.condPredicted 59309256 # Number of conditional branches predicted -system.cpu.branch_predictor.lookups 64114012 # Number of BP lookups -system.cpu.branch_predictor.predictedNotTaken 31921338 # Number of Branches Predicted As Not Taken (False). -system.cpu.branch_predictor.predictedTaken 32192674 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. -system.cpu.comBranches 62547159 # Number of Branches instructions committed -system.cpu.comFloats 24 # Number of Floating Point instructions committed -system.cpu.comInts 349039879 # Number of Integer instructions committed +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 114517555 # DTB read hits +system.cpu.dtb.read_misses 2631 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 114520186 # DTB read accesses +system.cpu.dtb.write_hits 39666604 # DTB write hits +system.cpu.dtb.write_misses 2302 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 39668906 # DTB write accesses +system.cpu.dtb.data_hits 154184159 # DTB hits +system.cpu.dtb.data_misses 4933 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 154189092 # DTB accesses +system.cpu.itb.fetch_hits 29078095 # ITB hits +system.cpu.itb.fetch_misses 22 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 29078117 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 558034834 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 547808694 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 412073 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 61249901 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 496784933 # Number of cycles cpu stages are processed. +system.cpu.activity 89.024000 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed -system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed -system.cpu.comNops 36304520 # Number of Nop instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed +system.cpu.comBranches 62547159 # Number of Branches instructions committed +system.cpu.comNops 36304520 # Number of Nop instructions committed +system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed +system.cpu.comInts 349039879 # Number of Integer instructions committed +system.cpu.comFloats 24 # Number of Floating Point instructions committed system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total) -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 0.869449 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 0.869449 # CPI: Total CPI of All Threads +system.cpu.cpi 0.927188 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.cpi_total 0.927188 # CPI: Total CPI of All Threads +system.cpu.ipc 1.078529 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.ipc_total 1.078529 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 90037625 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 84897563 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 39773148 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 49497029 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 39091844 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 78.978163 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 41686827 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 48350798 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541420411 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1005275257 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 257533113 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 154627572 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 38276366 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1491795 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 39768161 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 22779717 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 63.580352 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 411890550 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.stage0.idleCycles 210144173 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 347890661 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.342105 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 246346046 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 311688788 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 55.854719 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 214904658 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 343130176 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 61.489025 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 446207500 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111827334 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.039490 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 210384695 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347650139 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 62.299003 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 30 # number of replacements +system.cpu.icache.tagsinuse 726.393228 # Cycle average of tags in use +system.cpu.icache.total_refs 29077078 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 852 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 34128.025822 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 726.393228 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.354684 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 29077078 # number of ReadReq hits +system.cpu.icache.demand_hits 29077078 # number of demand (read+write) hits +system.cpu.icache.overall_hits 29077078 # number of overall hits +system.cpu.icache.ReadReq_misses 1015 # number of ReadReq misses +system.cpu.icache.demand_misses 1015 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1015 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 56421500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 56421500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 56421500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 29078093 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 29078093 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 29078093 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000035 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000035 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000035 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55587.684729 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55587.684729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55587.684729 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 163 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 163 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 163 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 852 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 852 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 852 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 45615500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45615500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45615500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53539.319249 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 451299 # number of replacements +system.cpu.dcache.tagsinuse 4094.156589 # Cycle average of tags in use +system.cpu.dcache.total_refs 152394384 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 334.642199 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 267634000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.156589 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999550 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 114120508 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38273876 # number of WriteReq hits +system.cpu.dcache.demand_hits 152394384 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 152394384 # number of overall hits +system.cpu.dcache.ReadReq_misses 393534 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1177445 # number of WriteReq misses +system.cpu.dcache.demand_misses 1570979 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1570979 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 8150455500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25241828500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 33392284000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 33392284000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20625.927414 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17534.174485 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114120879 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 8109351500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.003433 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 393163 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 191931 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3528437000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 22782.990625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20965.470977 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38930908 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11856564500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013191 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 520413 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 266250 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 5328647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15543.103448 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 336.085787 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 116 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1803000 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 21854.685324 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19449.234181 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153051787 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 19965916000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005934 # miss rate for demand accesses -system.cpu.dcache.demand_misses 913576 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 458181 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8857084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4091.682212 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.998946 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 21854.685324 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19449.234181 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153051787 # number of overall hits -system.cpu.dcache.overall_miss_latency 19965916000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005934 # miss rate for overall accesses -system.cpu.dcache.overall_misses 913576 # number of overall misses -system.cpu.dcache.overall_mshr_hits 458181 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8857084000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.029846 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010203 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 20710.930949 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 21437.798369 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 21255.716340 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 21255.716340 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12054000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3423892000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2783 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 216217 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4331.297161 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15835.443097 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 408187 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 192302 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 923282 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1115584 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1115584 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 3562178000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5466807000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9028985000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9028985000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.846625 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21509.059147 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4091.682212 # Cycle average of tags in use -system.cpu.dcache.total_refs 153051787 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 444176000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 408189 # number of writebacks -system.cpu.dtb.data_accesses 153970296 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 153965363 # DTB hits -system.cpu.dtb.data_misses 4933 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 114516673 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 114514042 # DTB read hits -system.cpu.dtb.read_misses 2631 # DTB read misses -system.cpu.dtb.write_accesses 39453623 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 39451321 # DTB write hits -system.cpu.dtb.write_misses 2302 # DTB write misses -system.cpu.execution_unit.executions 419011350 # Number of Instructions Executed. -system.cpu.execution_unit.mispredictPct 35.419120 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.mispredicted 22153653 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 40393506 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predictedNotTakenIncorrect 19275234 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.predictedTakenIncorrect 2878419 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.icache.ReadReq_accesses 25645163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55761.178862 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53508.177570 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 25644179 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 54869000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 984 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 128 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 45803000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 856 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 29958.153037 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 43000 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 25645163 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55761.178862 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53508.177570 # average overall mshr miss latency -system.cpu.icache.demand_hits 25644179 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 54869000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000038 # miss rate for demand accesses -system.cpu.icache.demand_misses 984 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 128 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 45803000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 856 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 728.253324 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.355592 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 25645163 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55761.178862 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53508.177570 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 25644179 # number of overall hits -system.cpu.icache.overall_miss_latency 54869000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000038 # miss rate for overall accesses -system.cpu.icache.overall_misses 984 # number of overall misses -system.cpu.icache.overall_mshr_hits 128 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 45803000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 856 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.sampled_refs 856 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 728.253324 # Cycle average of tags in use -system.cpu.icache.total_refs 25644179 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 62489806 # Number of cycles cpu's stages were not processed -system.cpu.ipc 1.150154 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 1.150154 # IPC: Total IPC of All Threads -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 25645185 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 25645165 # ITB hits -system.cpu.itb.fetch_misses 20 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 254171 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52150.173943 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40002.080663 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 194094 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 3133026000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.236364 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 60077 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2403205000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236364 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 60077 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 202080 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52172.605478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.213360 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 170059 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1670619000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.158457 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32021 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1281103000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158457 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32021 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 408189 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 408189 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.969472 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 73794 # number of replacements +system.cpu.l2cache.tagsinuse 17696.077368 # Cycle average of tags in use +system.cpu.l2cache.total_refs 445682 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89681 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.969637 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 1642.043968 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16054.033399 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.050111 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.489930 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 170050 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 408187 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 364155 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 364155 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32017 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 92092 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92092 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1674832000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3134450000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4809282000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4809282000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 202067 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 408187 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 456247 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 456247 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.158447 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.201847 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.201847 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52310.709935 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.613816 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52222.581766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52222.581766 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1314000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10346.456693 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 456251 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52157.973029 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40004.212904 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 364153 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4803645000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.201858 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 92098 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 59344 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3684308000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.201858 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 92098 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 1650.286010 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15989.036396 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.050363 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487947 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 456251 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52157.973029 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40004.212904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 364153 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4803645000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.201858 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 92098 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3684308000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.201858 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 92098 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 32017 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 92092 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92092 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 73800 # number of replacements -system.cpu.l2cache.sampled_refs 89688 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 1280946000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406895000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3687841000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3687841000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.201847 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.201847 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.308086 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.835622 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17639.322406 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445702 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 59346 # number of writebacks -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed -system.cpu.numCycles 523283946 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.regfile_manager.regFileAccesses 1022190210 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.regfile_manager.regFileReads 558335321 # Number of Reads from Register File -system.cpu.regfile_manager.regFileWrites 463854889 # Number of Writes to Register File -system.cpu.regfile_manager.regForwards 256259728 # Number of Registers Read Through Forwarding Logic -system.cpu.runCycles 460794140 # Number of cycles cpu stages are processed. -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage0.idleCycles 186436323 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 336847623 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 64.371863 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 209154116 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 314129830 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 60.030473 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197582511 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 325701435 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.241817 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 410314498 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 112969448 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.588556 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 180086100 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 343197846 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 65.585396 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 508404874 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.timesIdled 455729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr index 79a2396a6..1b49765a7 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr @@ -1,11 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 124e9408d..78f49b74e 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,15 +1,11 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:58:35 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing +gem5 compiled Jun 19 2011 06:59:13 +gem5 started Jun 19 2011 13:35:14 +gem5 executing on m60-009.pool +command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 43687852500 because target called exit() +Exiting @ tick 46960422500 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index e986b9b66..33754d9f7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,301 +1,304 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 198512 # Simulator instruction rate (inst/s) -host_mem_usage 241900 # Number of bytes of host memory used -host_seconds 445.02 # Real time elapsed on the host -host_tick_rate 98171525 # Simulator tick rate (ticks/s) +sim_seconds 0.046960 # Number of seconds simulated +sim_ticks 46960422500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 121209 # Simulator instruction rate (inst/s) +host_tick_rate 64432457 # Simulator tick rate (ticks/s) +host_mem_usage 201704 # Number of bytes of host memory used +host_seconds 728.83 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.043688 # Number of seconds simulated -sim_ticks 43687852500 # Number of ticks simulated -system.cpu.activity 70.715162 # Percentage of cycles cpu is active -system.cpu.agen_unit.agens 35033051 # Number of Address Generations -system.cpu.branch_predictor.BTBHitPct 40.125186 # BTB Hit Percentage -system.cpu.branch_predictor.BTBHits 4678520 # Number of BTB hits -system.cpu.branch_predictor.BTBLookups 11659809 # Number of BTB lookups -system.cpu.branch_predictor.RASInCorrect 1539 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.condIncorrect 753993 # Number of conditional branches incorrect -system.cpu.branch_predictor.condPredicted 9173160 # Number of conditional branches predicted -system.cpu.branch_predictor.lookups 14237671 # Number of BP lookups -system.cpu.branch_predictor.predictedNotTaken 6139595 # Number of Branches Predicted As Not Taken (False). -system.cpu.branch_predictor.predictedTaken 8098076 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.usedRAS 1660495 # Number of times the RAS was used to get a target. -system.cpu.comBranches 13754477 # Number of Branches instructions committed -system.cpu.comFloats 151453 # Number of Floating Point instructions committed -system.cpu.comInts 30791227 # Number of Integer instructions committed +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20277221 # DTB read hits +system.cpu.dtb.read_misses 90148 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 20367369 # DTB read accesses +system.cpu.dtb.write_hits 14736811 # DTB write hits +system.cpu.dtb.write_misses 7252 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 14744063 # DTB write accesses +system.cpu.dtb.data_hits 35014032 # DTB hits +system.cpu.dtb.data_misses 97400 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 35111432 # DTB accesses +system.cpu.itb.fetch_hits 12387546 # ITB hits +system.cpu.itb.fetch_misses 10588 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 12398134 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.numCycles 93920846 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 77525843 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 305872 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24229643 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69691203 # Number of cycles cpu stages are processed. +system.cpu.activity 74.202061 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed -system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed -system.cpu.comNops 8748916 # Number of Nop instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed +system.cpu.comBranches 13754477 # Number of Branches instructions committed +system.cpu.comNops 8748916 # Number of Nop instructions committed +system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed +system.cpu.comInts 30791227 # Number of Integer instructions committed +system.cpu.comFloats 151453 # Number of Floating Point instructions committed system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 0.989077 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 0.989077 # CPI: Total CPI of All Threads +system.cpu.cpi 1.063167 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.cpi_total 1.063167 # CPI: Total CPI of All Threads +system.cpu.ipc 0.940586 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.ipc_total 0.940586 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 18775711 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12354362 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4821711 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 15677307 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 4750423 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660962 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 30.301269 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8154380 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10621331 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74177297 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 126496547 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65349 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 292979 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14162850 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35055536 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4522867 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 188344 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4711211 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9061038 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 34.208000 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44765481 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.stage0.idleCycles 41151668 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52769178 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 56.184735 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 51441694 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42479152 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.228673 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 50863748 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43057098 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.844027 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 71800106 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120740 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.552535 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47858752 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46062094 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 49.043525 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 83802 # number of replacements +system.cpu.icache.tagsinuse 1886.866724 # Cycle average of tags in use +system.cpu.icache.total_refs 12270472 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 85848 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 142.932532 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1886.866724 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.921322 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 12270472 # number of ReadReq hits +system.cpu.icache.demand_hits 12270472 # number of demand (read+write) hits +system.cpu.icache.overall_hits 12270472 # number of overall hits +system.cpu.icache.ReadReq_misses 117039 # number of ReadReq misses +system.cpu.icache.demand_misses 117039 # number of demand (read+write) misses +system.cpu.icache.overall_misses 117039 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 2068714000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 2068714000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 2068714000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 12387511 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 12387511 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 12387511 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.009448 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.009448 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.009448 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 17675.424431 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 17675.424431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 17675.424431 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1666000 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 174 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 9574.712644 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 31191 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 31191 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 31191 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 85848 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 85848 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 85848 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 1347366500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1347366500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1347366500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006930 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.006930 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.006930 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15694.791958 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15694.791958 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15694.791958 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 200251 # number of replacements +system.cpu.dcache.tagsinuse 4073.088977 # Cycle average of tags in use +system.cpu.dcache.total_refs 34126006 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.000279 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 486750000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4073.088977 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994406 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 20180454 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 13945552 # number of WriteReq hits +system.cpu.dcache.demand_hits 34126006 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 34126006 # number of overall hits +system.cpu.dcache.ReadReq_misses 96184 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 667825 # number of WriteReq misses +system.cpu.dcache.demand_misses 764009 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 764009 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4158459500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 35331617000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 39490076500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 39490076500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 43413.349504 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34421.526841 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20182230 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4098567500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004656 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 94408 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 33642 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2091658500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 50157.576620 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49503.360543 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14405989 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10402079500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.014192 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 207388 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 63810 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 7107593500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16833.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 169.264666 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 162 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.004744 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.045700 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.021898 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.021898 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 43234.420486 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 52905.502190 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 51687.972917 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 51687.972917 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2727000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6330419000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124111 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51006.107436 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 48047.843576 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 45018.459069 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34588219 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14500647000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.008650 # miss rate for demand accesses -system.cpu.dcache.demand_misses 301796 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 97452 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9199252000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.writebacks 161216 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 35417 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 524245 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 559662 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 559662 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 60767 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 143580 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 204347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2088747000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 7254442500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9343189500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9343189500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4071.844772 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994103 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 48047.843576 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 45018.459069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34588219 # number of overall hits -system.cpu.dcache.overall_miss_latency 14500647000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.008650 # miss rate for overall accesses -system.cpu.dcache.overall_misses 301796 # number of overall misses -system.cpu.dcache.overall_mshr_hits 97452 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9199252000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34373.047871 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.438780 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 45722.176005 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 45722.176005 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4071.844772 # Cycle average of tags in use -system.cpu.dcache.total_refs 34588219 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 497796000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 161214 # number of writebacks -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.execution_unit.executions 44841137 # Number of Instructions Executed. -system.cpu.execution_unit.mispredictPct 5.481801 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.mispredicted 753993 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 13000484 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predictedNotTakenIncorrect 550902 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.predictedTakenIncorrect 203091 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.icache.ReadReq_accesses 11384439 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18620.927639 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.720286 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 11286707 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1819860500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.008585 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 97732 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 9063 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1379487500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.007789 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 88669 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 18115.384615 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 127.291774 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 39 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 706500 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11384439 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18620.927639 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15557.720286 # average overall mshr miss latency -system.cpu.icache.demand_hits 11286707 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1819860500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.008585 # miss rate for demand accesses -system.cpu.icache.demand_misses 97732 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 9063 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1379487500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.007789 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 88669 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1881.619179 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.918759 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 11384439 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18620.927639 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15557.720286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 11286707 # number of overall hits -system.cpu.icache.overall_miss_latency 1819860500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.008585 # miss rate for overall accesses -system.cpu.icache.overall_misses 97732 # number of overall misses -system.cpu.icache.overall_mshr_hits 9063 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1379487500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.007789 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 88669 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 86622 # number of replacements -system.cpu.icache.sampled_refs 88668 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1881.619179 # Cycle average of tags in use -system.cpu.icache.total_refs 11286707 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 25587834 # Number of cycles cpu's stages were not processed -system.cpu.ipc 1.011044 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 1.011044 # IPC: Total IPC of All Threads -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 11389716 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 11384460 # ITB hits -system.cpu.itb.fetch_misses 5256 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 143582 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52040.829752 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.848005 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12097 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 6842588500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.915748 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 131485 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259511500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915748 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 131485 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 149430 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52294.157340 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40025.851037 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 106453 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2247446000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.287606 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 42977 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1720191000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 42977 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 161214 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 161214 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.775484 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 148058 # number of replacements +system.cpu.l2cache.tagsinuse 18662.722702 # Cycle average of tags in use +system.cpu.l2cache.total_refs 131525 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 173403 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.758493 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 3004.603682 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15658.119020 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.091693 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.477848 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 103488 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 161216 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 12270 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 115758 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 115758 # number of overall hits +system.cpu.l2cache.ReadReq_misses 42937 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 131500 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 174437 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 174437 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 2242217000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 6854385000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 9096602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 9096602000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 146425 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 161216 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 143770 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 290195 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 290195 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.293235 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.914655 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.601103 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.601103 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52221.091366 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52124.600760 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52148.351554 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52148.351554 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 293012 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52103.234515 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40007.007257 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 118550 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9090034500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.595409 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 174462 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 120515 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 6979702500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.595409 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 174462 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 3048.873160 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15598.097053 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.093044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.476016 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 293012 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52103.234515 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40007.007257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 118550 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9090034500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.595409 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 174462 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 6979702500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.595409 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 174462 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 42937 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 131500 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 174437 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 174437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 148090 # number of replacements -system.cpu.l2cache.sampled_refs 173435 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 1718546000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262803000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 6981349000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 6981349000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293235 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.914655 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.601103 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.601103 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.827072 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40021.315589 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40022.179927 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40022.179927 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18646.970214 # Cycle average of tags in use -system.cpu.l2cache.total_refs 134496 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120516 # number of writebacks -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.mult_div_unit.multiplies 41101 # Number of Multipy Operations Executed -system.cpu.numCycles 87375706 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.regfile_manager.regFileAccesses 145605009 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.regfile_manager.regFileReads 93058128 # Number of Reads from Register File -system.cpu.regfile_manager.regFileWrites 52546881 # Number of Writes to Register File -system.cpu.regfile_manager.regForwards 13517276 # Number of Registers Read Through Forwarding Logic -system.cpu.runCycles 61787872 # Number of cycles cpu stages are processed. -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage0.idleCycles 42493951 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 44881755 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 51.366400 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 48181868 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 39193838 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 44.856677 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46079607 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 41296099 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 47.262678 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 63477269 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 23898437 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 27.351352 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 39338499 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 48037207 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 54.977761 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 69007682 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.timesIdled 289197 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr index 79a2396a6..1b49765a7 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr @@ -1,11 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 6c62eaee3..a850d490c 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:58:24 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing +gem5 compiled Jun 19 2011 06:59:13 +gem5 started Jun 19 2011 08:31:13 +gem5 executing on m60-009.pool +command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 979951369500 because target called exit() +Exiting @ tick 1016488689500 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 3b06d5b45..a608e7e97 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,301 +1,304 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 191712 # Simulator instruction rate (inst/s) -host_mem_usage 1122860 # Number of bytes of host memory used -host_seconds 9492.28 # Real time elapsed on the host -host_tick_rate 103236678 # Simulator tick rate (ticks/s) +sim_seconds 1.016489 # Number of seconds simulated +sim_ticks 1016488689500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 111625 # Simulator instruction rate (inst/s) +host_tick_rate 62351436 # Simulator tick rate (ticks/s) +host_mem_usage 193064 # Number of bytes of host memory used +host_seconds 16302.57 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated -sim_seconds 0.979951 # Number of seconds simulated -sim_ticks 979951369500 # Number of ticks simulated -system.cpu.activity 74.309805 # Percentage of cycles cpu is active -system.cpu.agen_unit.agens 614316005 # Number of Address Generations -system.cpu.branch_predictor.BTBHitPct 69.872947 # BTB Hit Percentage -system.cpu.branch_predictor.BTBHits 82064192 # Number of BTB hits -system.cpu.branch_predictor.BTBLookups 117447733 # Number of BTB lookups -system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.condIncorrect 79224651 # Number of conditional branches incorrect -system.cpu.branch_predictor.condPredicted 175157411 # Number of conditional branches predicted -system.cpu.branch_predictor.lookups 253574750 # Number of BP lookups -system.cpu.branch_predictor.predictedNotTaken 124923988 # Number of Branches Predicted As Not Taken (False). -system.cpu.branch_predictor.predictedTaken 128650762 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. -system.cpu.comBranches 214632552 # Number of Branches instructions committed -system.cpu.comFloats 190 # Number of Floating Point instructions committed -system.cpu.comInts 916086844 # Number of Integer instructions committed +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 444614416 # DTB read hits +system.cpu.dtb.read_misses 4897078 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 449511494 # DTB read accesses +system.cpu.dtb.write_hits 160920901 # DTB write hits +system.cpu.dtb.write_misses 1701304 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 162622205 # DTB write accesses +system.cpu.dtb.data_hits 605535317 # DTB hits +system.cpu.dtb.data_misses 6598382 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 612133699 # DTB accesses +system.cpu.itb.fetch_hits 237932826 # ITB hits +system.cpu.itb.fetch_misses 22 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 237932848 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.numCycles 2032977380 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 1759886457 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 7533536 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 440243372 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1592734008 # Number of cycles cpu stages are processed. +system.cpu.activity 78.344896 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed -system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed -system.cpu.comNops 83736345 # Number of Nop instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed +system.cpu.comBranches 214632552 # Number of Branches instructions committed +system.cpu.comNops 83736345 # Number of Nop instructions committed +system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed +system.cpu.comInts 916086844 # Number of Integer instructions committed +system.cpu.comFloats 190 # Number of Floating Point instructions committed system.cpu.committedInsts 1819780127 # Number of Instructions Simulated (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions Simulated (Total) -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 1.077000 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 1.077000 # CPI: Total CPI of All Threads +system.cpu.cpi 1.117156 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.cpi_total 1.117156 # CPI: Total CPI of All Threads +system.cpu.ipc 0.895131 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.ipc_total 0.895131 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 338882102 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 262365824 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 145832523 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 223761389 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 153206045 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 68.468490 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 189687399 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 149194703 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667621622 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 3043824239 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 226 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 571 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 655476684 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617179738 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 132311663 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 6922402 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 139234065 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 75965071 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 64.700104 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1137833135 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.stage0.idleCycles 823371490 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1209605890 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.499230 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1094712452 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 938264928 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.152256 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1056818268 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 976159112 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.016231 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1623201304 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409776076 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.156450 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 1008711848 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1024265532 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.382535 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1 # number of replacements +system.cpu.icache.tagsinuse 664.417711 # Cycle average of tags in use +system.cpu.icache.total_refs 237931761 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 277309.744755 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 664.417711 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.324423 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 237931761 # number of ReadReq hits +system.cpu.icache.demand_hits 237931761 # number of demand (read+write) hits +system.cpu.icache.overall_hits 237931761 # number of overall hits +system.cpu.icache.ReadReq_misses 1062 # number of ReadReq misses +system.cpu.icache.demand_misses 1062 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1062 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 58372500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 58372500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 58372500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 237932823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 237932823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 237932823 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 54964.689266 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 54964.689266 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 54964.689266 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 81000 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 204 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 204 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 204 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 858 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 858 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 858 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 45874500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45874500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45874500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53466.783217 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53466.783217 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53466.783217 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9107352 # number of replacements +system.cpu.dcache.tagsinuse 4082.698985 # Cycle average of tags in use +system.cpu.dcache.total_refs 595070238 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.310172 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12613555000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4082.698985 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.996753 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 437271427 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 157798811 # number of WriteReq hits +system.cpu.dcache.demand_hits 595070238 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 595070238 # number of overall hits +system.cpu.dcache.ReadReq_misses 7324236 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 2929691 # number of WriteReq misses +system.cpu.dcache.demand_misses 10253927 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 10253927 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 180890019000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 110280256500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 291170275500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 291170275500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24782.275660 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21696.910468 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 437273551 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 181458598000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.016469 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7322112 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 99789 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 156702095500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7222323 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 36133.458705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30848.973440 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 158603354 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 76788947500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013222 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2125148 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 235828 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 58283582500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15086.569579 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 65.397306 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 618 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9323500 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27335.708502 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23594.611641 # average overall mshr miss latency -system.cpu.dcache.demand_hits 595876905 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 258247545500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.015607 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9447260 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 335617 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 214985678000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9111643 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4081.685602 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.996505 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27335.708502 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23594.611641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 595876905 # number of overall hits -system.cpu.dcache.overall_miss_latency 258247545500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.015607 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9447260 # number of overall misses -system.cpu.dcache.overall_mshr_hits 335617 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 214985678000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9111643 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_miss_rate 0.016474 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.018228 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.016940 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.016940 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 24697.459093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37642.282582 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 28395.977024 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 28395.977024 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10999500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8090380500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 208980 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.882651 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38713.659202 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 3058572 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 101954 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1040525 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1142479 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1142479 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7222282 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1889166 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9111448 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9111448 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9107547 # number of replacements -system.cpu.dcache.sampled_refs 9111643 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 156087353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 59191861000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 215279214000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 215279214000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.916151 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.270960 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23627.332780 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23627.332780 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4081.685602 # Cycle average of tags in use -system.cpu.dcache.total_refs 595876905 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12696089000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 3058780 # number of writebacks -system.cpu.dtb.data_accesses 611922547 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 605324165 # DTB hits -system.cpu.dtb.data_misses 6598382 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 444595663 # DTB read hits -system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 160728502 # DTB write hits -system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.execution_unit.executions 1162207758 # Number of Instructions Executed. -system.cpu.execution_unit.mispredictPct 36.911759 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.mispredicted 79224651 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 135407901 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predictedNotTakenIncorrect 71572967 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.predictedTakenIncorrect 7651684 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.icache.ReadReq_accesses 207004701 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 54777.453839 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53438.372093 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 207003672 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 56366000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1029 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 169 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 45957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 23666.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 240701.944186 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 142000 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 207004701 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 54777.453839 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53438.372093 # average overall mshr miss latency -system.cpu.icache.demand_hits 207003672 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 56366000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses -system.cpu.icache.demand_misses 1029 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 169 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 45957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 860 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 664.403935 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.324416 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 207004701 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 54777.453839 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53438.372093 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 207003672 # number of overall hits -system.cpu.icache.overall_miss_latency 56366000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses -system.cpu.icache.overall_misses 1029 # number of overall misses -system.cpu.icache.overall_mshr_hits 169 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 45957000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 860 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 860 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 664.403935 # Cycle average of tags in use -system.cpu.icache.total_refs 207003672 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 503502831 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.928505 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.928505 # IPC: Total IPC of All Threads -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 207004724 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 207004706 # ITB hits -system.cpu.itb.fetch_misses 18 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52171.425069 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.113019 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 1000086 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 46392605000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.470664 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 889234 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569460500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470664 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 889234 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7223183 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52232.293721 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40052.296896 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5415265 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 94431704000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.250294 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1807918 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72411268500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250294 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1807918 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 3058780 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 3058780 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.790606 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 2686299 # number of replacements +system.cpu.l2cache.tagsinuse 26362.253179 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 225759748000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15507.582634 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10854.670545 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.473254 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.331258 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5414817 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3058572 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 1000333 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6415150 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6415150 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1807881 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 889275 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2697156 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2697156 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 94453448000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 46507349000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 140960797000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 140960797000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7222698 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3058572 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1889608 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9112306 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9112306 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.250305 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.470613 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.295990 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.295990 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52245.390045 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.050659 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52262.752692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52262.752692 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9112503 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52212.225711 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40035.092201 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 6415351 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 140824309000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.295984 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2697152 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 1170911 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 107980729000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.295984 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2697152 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 15023.339345 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11052.003329 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.458476 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.337280 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 9112503 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52212.225711 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40035.092201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 6415351 # number of overall hits -system.cpu.l2cache.overall_miss_latency 140824309000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.295984 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2697152 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 107980729000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.295984 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2697152 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 1807881 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 889275 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2697156 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2697156 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2686322 # number of replacements -system.cpu.l2cache.sampled_refs 2710967 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 72354306000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671086000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 108025392000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 108025392000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250305 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.295990 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.295990 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.608723 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.547862 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.592121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.592121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26075.342674 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7565242 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 230207194000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1170923 # number of writebacks -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed -system.cpu.numCycles 1959902740 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.regfile_manager.regFileAccesses 3178023708 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.regfile_manager.regFileReads 1801820745 # Number of Reads from Register File -system.cpu.regfile_manager.regFileWrites 1376202963 # Number of Writes to Register File -system.cpu.regfile_manager.regForwards 604786987 # Number of Registers Read Through Forwarding Logic -system.cpu.runCycles 1456399909 # Number of cycles cpu stages are processed. -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage0.idleCycles 902142172 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1057760568 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 53.970054 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1064240534 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 895662206 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.699319 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1036315285 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 923587455 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 47.124147 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1537492347 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 422410393 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.552620 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 932643705 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1027259035 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.413776 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 1619523667 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.timesIdled 8517352 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr index 79a2396a6..1b49765a7 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr @@ -1,11 +1,6 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index 21f9ae246..d3c569634 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:01:01 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing +gem5 compiled Jun 19 2011 06:59:13 +gem5 started Jun 19 2011 06:59:18 +gem5 executing on m60-009.pool +command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second @@ -27,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 40531279000 because target called exit() +122 123 124 Exiting @ tick 42094188000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 53d449590..d48c1814c 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,301 +1,304 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 197293 # Simulator instruction rate (inst/s) -host_mem_usage 267004 # Number of bytes of host memory used -host_seconds 465.82 # Real time elapsed on the host -host_tick_rate 87010339 # Simulator tick rate (ticks/s) +sim_seconds 0.042094 # Number of seconds simulated +sim_ticks 42094188000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 121365 # Simulator instruction rate (inst/s) +host_tick_rate 55588778 # Simulator tick rate (ticks/s) +host_mem_usage 196912 # Number of bytes of host memory used +host_seconds 757.24 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.040531 # Number of seconds simulated -sim_ticks 40531279000 # Number of ticks simulated -system.cpu.activity 91.670040 # Percentage of cycles cpu is active -system.cpu.agen_unit.agens 27308571 # Number of Address Generations -system.cpu.branch_predictor.BTBHitPct 59.146483 # BTB Hit Percentage -system.cpu.branch_predictor.BTBHits 4489525 # Number of BTB hits -system.cpu.branch_predictor.BTBLookups 7590519 # Number of BTB lookups -system.cpu.branch_predictor.RASInCorrect 138 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.condIncorrect 2806970 # Number of conditional branches incorrect -system.cpu.branch_predictor.condPredicted 7883251 # Number of conditional branches predicted -system.cpu.branch_predictor.lookups 11539980 # Number of BP lookups -system.cpu.branch_predictor.predictedNotTaken 4913265 # Number of Branches Predicted As Not Taken (False). -system.cpu.branch_predictor.predictedTaken 6626715 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.comBranches 10240685 # Number of Branches instructions committed -system.cpu.comFloats 3775974 # Number of Floating Point instructions committed -system.cpu.comInts 43665352 # Number of Integer instructions committed +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 19996214 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 19996224 # DTB read accesses +system.cpu.dtb.write_hits 6501905 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6501928 # DTB write accesses +system.cpu.dtb.data_hits 26498119 # DTB hits +system.cpu.dtb.data_misses 33 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 26498152 # DTB accesses +system.cpu.itb.fetch_hits 10077672 # ITB hits +system.cpu.itb.fetch_misses 49 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 10077721 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 84188377 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 83816425 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 10559 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7701629 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76486748 # Number of cycles cpu stages are processed. +system.cpu.activity 90.851909 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed -system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed -system.cpu.comNops 7723346 # Number of Nop instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed +system.cpu.comBranches 10240685 # Number of Branches instructions committed +system.cpu.comNops 7723346 # Number of Nop instructions committed +system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed +system.cpu.comInts 43665352 # Number of Integer instructions committed +system.cpu.comFloats 3775974 # Number of Floating Point instructions committed system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 0.882044 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 0.882044 # CPI: Total CPI of All Threads +system.cpu.cpi 0.916056 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.cpi_total 0.916056 # CPI: Total CPI of All Threads +system.cpu.ipc 1.091636 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.ipc_total 1.091636 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 13660151 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 10092693 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4598416 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 8981993 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 4278316 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 131 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 47.632146 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 6418014 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7242137 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73810840 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136386312 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206031 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 8057919 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38650469 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26688179 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3946440 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 651118 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4597558 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5643144 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 44.894950 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57370437 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.stage0.idleCycles 27496111 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56692266 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 67.339778 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34731944 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49456433 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.744965 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34177132 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 50011245 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.403978 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 66154944 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18033433 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.420336 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30219873 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53968504 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.104459 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 7205 # number of replacements +system.cpu.icache.tagsinuse 1491.617776 # Cycle average of tags in use +system.cpu.icache.total_refs 10066620 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9090 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1107.438944 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1491.617776 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.728329 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 10066620 # number of ReadReq hits +system.cpu.icache.demand_hits 10066620 # number of demand (read+write) hits +system.cpu.icache.overall_hits 10066620 # number of overall hits +system.cpu.icache.ReadReq_misses 11049 # number of ReadReq misses +system.cpu.icache.demand_misses 11049 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11049 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 285327000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 285327000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 285327000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 10077669 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 10077669 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 10077669 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001096 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001096 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001096 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 25823.784958 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 25823.784958 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 25823.784958 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 13900 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1959 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1959 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1959 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 9090 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 9090 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 9090 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 218831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 218831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 218831500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000902 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000902 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000902 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 24073.872387 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 24073.872387 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 24073.872387 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 157 # number of replacements +system.cpu.dcache.tagsinuse 1441.601089 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491207 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11916.872245 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 1441.601089 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.351953 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 19995646 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits +system.cpu.dcache.demand_hits 26491207 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 26491207 # number of overall hits +system.cpu.dcache.ReadReq_misses 552 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses +system.cpu.dcache.demand_misses 6094 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 6094 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28390000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 303795000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 332185000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 332185000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51752.929688 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48810.526316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19995686 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 512 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 23185000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55921.258907 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52792.620137 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6496893 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 235428500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000648 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 4210 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 2462 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 92281500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 52826.923077 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11917.489429 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 26 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 51431.159420 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 54816.853122 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54510.173942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54510.173942 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1373500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41040500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49866.950182 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55469.292673 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51941.745389 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26492579 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 261926000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000178 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4722 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2499 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 115466500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.writebacks 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 77 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 3794 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 3871 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 3871 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 1441.508051 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.351931 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55469.292673 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51941.745389 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26492579 # number of overall hits -system.cpu.dcache.overall_miss_latency 261926000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000178 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4722 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2499 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 115466500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 23213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 92992000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 116205000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 116205000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53199.084668 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52273.954116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52273.954116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.508051 # Cycle average of tags in use -system.cpu.dcache.total_refs 26492579 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.execution_unit.executions 57928840 # Number of Instructions Executed. -system.cpu.execution_unit.mispredictPct 27.409983 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.mispredicted 2806970 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 7433715 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predictedNotTakenIncorrect 1384945 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.predictedTakenIncorrect 1422025 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.icache.ReadReq_accesses 9759564 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26779.967317 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23139.993880 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 9749161 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 278592000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.001066 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 599 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 226864500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 9804 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 994.406467 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 202500 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 9759564 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26779.967317 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23139.993880 # average overall mshr miss latency -system.cpu.icache.demand_hits 9749161 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 278592000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.001066 # miss rate for demand accesses -system.cpu.icache.demand_misses 10403 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 599 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 226864500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.001005 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 9804 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1493.341252 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.729171 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 9759564 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26779.967317 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23139.993880 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 9749161 # number of overall hits -system.cpu.icache.overall_miss_latency 278592000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.001066 # miss rate for overall accesses -system.cpu.icache.overall_misses 10403 # number of overall misses -system.cpu.icache.overall_mshr_hits 599 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 226864500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.001005 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 9804 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 7919 # number of replacements -system.cpu.icache.sampled_refs 9804 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1493.341252 # Cycle average of tags in use -system.cpu.icache.total_refs 9749161 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 6752479 # Number of cycles cpu's stages were not processed -system.cpu.ipc 1.133730 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 1.133730 # IPC: Total IPC of All Threads -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 9759619 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 9759572 # ITB hits -system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52355.691057 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40114.401858 # average ReadExReq mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 2189.147121 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6359 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3281 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.938129 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 2171.310088 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.837033 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.066263 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000544 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 6350 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 90156500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 6376 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6376 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3215 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69077000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10279 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52322.761194 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40125.621891 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7063 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 168270000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.312871 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 129044000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.312871 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses +system.cpu.l2cache.demand_misses 4937 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 4937 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 168259500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 90562500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 258822000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 258822000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 9565 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.154784 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 11313 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 11313 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.336121 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.436401 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.436401 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52335.769829 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52591.463415 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52424.954426 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52424.954426 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12027 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52334.244633 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40121.709194 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7089 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 258426500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.410576 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 198121000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.410576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 2173.408531 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.762817 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.066327 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000542 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 12027 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52334.244633 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40121.709194 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7089 # number of overall hits -system.cpu.l2cache.overall_miss_latency 258426500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.410576 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4938 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 198121000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.410576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 3215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 4937 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 4937 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 129008000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 198352500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 198352500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.336121 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.436401 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.436401 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40126.905132 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.744483 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40176.726757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40176.726757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2191.171348 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7072 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.mult_div_unit.multiplies 458252 # Number of Multipy Operations Executed -system.cpu.numCycles 81062559 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.regfile_manager.regFileAccesses 152685930 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.regfile_manager.regFileReads 84258569 # Number of Reads from Register File -system.cpu.regfile_manager.regFileWrites 68427361 # Number of Writes to Register File -system.cpu.regfile_manager.regForwards 38185928 # Number of Registers Read Through Forwarding Logic -system.cpu.runCycles 74310080 # Number of cycles cpu stages are processed. -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage0.idleCycles 27951091 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53111468 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 65.519111 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33262621 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 47799938 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.966727 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 32674404 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 48388155 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.692361 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 63236282 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 17826277 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.990765 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 26883065 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 54179494 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 66.836644 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 80607865 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.timesIdled 10786 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index f797f48a3..56aa11fc5 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,16 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:58:24 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing +gem5 compiled Jun 11 2011 02:50:17 +gem5 started Jun 11 2011 02:50:25 +gem5 executing on zooks +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 22294500 because target called exit() +Exiting @ tick 21139000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index f36ebb971..f4facbbd3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,296 +1,299 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 116380 # Simulator instruction rate (inst/s) -host_mem_usage 203032 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 403915000 # Simulator tick rate (ticks/s) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 21139000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 46714 # Simulator instruction rate (inst/s) +host_tick_rate 154158882 # Simulator tick rate (ticks/s) +host_mem_usage 159872 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22294500 # Number of ticks simulated -system.cpu.activity 16.075353 # Percentage of cycles cpu is active -system.cpu.agen_unit.agens 2186 # Number of Address Generations -system.cpu.branch_predictor.BTBHitPct 23.015873 # BTB Hit Percentage -system.cpu.branch_predictor.BTBHits 87 # Number of BTB hits -system.cpu.branch_predictor.BTBLookups 378 # Number of BTB lookups -system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.condIncorrect 542 # Number of conditional branches incorrect -system.cpu.branch_predictor.condPredicted 995 # Number of conditional branches predicted -system.cpu.branch_predictor.lookups 1423 # Number of BP lookups -system.cpu.branch_predictor.predictedNotTaken 1183 # Number of Branches Predicted As Not Taken (False). -system.cpu.branch_predictor.predictedTaken 240 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.usedRAS 125 # Number of times the RAS was used to get a target. -system.cpu.comBranches 1051 # Number of Branches instructions committed -system.cpu.comFloats 2 # Number of Floating Point instructions committed -system.cpu.comInts 3265 # Number of Integer instructions committed +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1188 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1195 # DTB read accesses +system.cpu.dtb.write_hits 899 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 902 # DTB write accesses +system.cpu.dtb.data_hits 2087 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2097 # DTB accesses +system.cpu.itb.fetch_hits 955 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 972 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 42279 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 11424 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 458 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34857 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7422 # Number of cycles cpu stages are processed. +system.cpu.activity 17.554814 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed -system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed -system.cpu.comNops 17 # Number of Nop instructions committed system.cpu.comStores 865 # Number of Store instructions committed +system.cpu.comBranches 1051 # Number of Branches instructions committed +system.cpu.comNops 17 # Number of Nop instructions committed +system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed +system.cpu.comInts 3265 # Number of Integer instructions committed +system.cpu.comFloats 2 # Number of Floating Point instructions committed system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 6.962836 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 6.962836 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56786.458333 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53789.473684 # average ReadReq mshr miss latency +system.cpu.cpi 6.601968 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.cpi_total 6.601968 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151470 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.ipc_total 0.151470 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1673 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1207 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 702 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1421 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 419 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 29.486277 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 570 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1103 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5160 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9740 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 3004 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2133 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 369 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 290 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 659 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 393 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.642586 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 4442 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.stage0.idleCycles 37253 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 5026 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.887698 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38359 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3920 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.271742 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38092 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4187 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.903262 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40935 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1344 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.178883 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 37801 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4478 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.591547 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 139.199781 # Cycle average of tags in use +system.cpu.icache.total_refs 583 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1.936877 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 139.199781 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.067969 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 583 # number of ReadReq hits +system.cpu.icache.demand_hits 583 # number of demand (read+write) hits +system.cpu.icache.overall_hits 583 # number of overall hits +system.cpu.icache.ReadReq_misses 372 # number of ReadReq misses +system.cpu.icache.demand_misses 372 # number of demand (read+write) misses +system.cpu.icache.overall_misses 372 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 20556000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 20556000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 20556000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 955 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 955 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 955 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.389529 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.389529 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.389529 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55258.064516 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55258.064516 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55258.064516 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 302 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 302 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 302 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 16052500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 16052500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 16052500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.316230 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.316230 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.316230 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53153.973510 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53153.973510 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53153.973510 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 102.923226 # Cycle average of tags in use +system.cpu.dcache.total_refs 1704 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.142857 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 102.923226 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.025128 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1089 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5451500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081013 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5110000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56582.191781 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53561.643836 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 719 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8261000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.168786 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 146 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 73 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 54000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.761905 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.WriteReq_hits 615 # number of WriteReq hits +system.cpu.dcache.demand_hits 1704 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1704 # number of overall hits +system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 251 # number of WriteReq misses +system.cpu.dcache.demand_misses 349 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 349 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5567500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 13605500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 19173000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19173000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1187 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 866 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 2053 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2053 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.082561 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.289838 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.169995 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.169995 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 56811.224490 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 54205.179283 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54936.962751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54936.962751 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 162000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1656500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 46013.888889 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56663.223140 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53690.476190 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1808 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13712500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.118049 # miss rate for demand accesses -system.cpu.dcache.demand_misses 242 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 74 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9020000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 178 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 181 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 181 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 101.981030 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.024898 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56663.223140 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53690.476190 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1808 # number of overall hits -system.cpu.dcache.overall_miss_latency 13712500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.118049 # miss rate for overall accesses -system.cpu.dcache.overall_misses 242 # number of overall misses -system.cpu.dcache.overall_mshr_hits 74 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9020000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 5121500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3908500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9030000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9030000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.080034 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084296 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.081831 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.081831 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53910.526316 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53541.095890 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 101.981030 # Cycle average of tags in use -system.cpu.dcache.total_refs 1808 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2050 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1185 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.execution_unit.executions 4596 # Number of Instructions Executed. -system.cpu.execution_unit.mispredictPct 51.569933 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.mispredicted 542 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 509 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predictedNotTakenIncorrect 537 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.predictedTakenIncorrect 5 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.icache.ReadReq_accesses 955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55322.580645 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53094.684385 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 614 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 18865000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.357068 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15981500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.315183 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 301 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.046667 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 955 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55322.580645 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency -system.cpu.icache.demand_hits 614 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 18865000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.357068 # miss rate for demand accesses -system.cpu.icache.demand_misses 341 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15981500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.315183 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 301 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 136.964505 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.066877 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 955 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55322.580645 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 614 # number of overall hits -system.cpu.icache.overall_miss_latency 18865000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.357068 # miss rate for overall accesses -system.cpu.icache.overall_misses 341 # number of overall misses -system.cpu.icache.overall_mshr_hits 40 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15981500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.315183 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 301 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 300 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 136.964505 # Cycle average of tags in use -system.cpu.icache.total_refs 614 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 37422 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.143620 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.143620 # IPC: Total IPC of All Threads -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 972 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 955 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 195.664492 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 195.664492 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005971 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses 396 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 469 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 469 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 20706500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3820500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 24527000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 24527000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52321.917808 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40267.123288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3819500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997481 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2939500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 396 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52229.113924 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40054.430380 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 20630500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997475 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 395 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15821500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997475 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 395 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002538 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.demand_miss_rate 0.997872 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997872 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52289.141414 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52335.616438 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52296.375267 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52296.375267 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 469 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52243.589744 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40087.606838 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 24450000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997868 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 468 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 18761000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997868 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 468 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 192.950109 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005888 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 469 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52243.589744 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40087.606838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 24450000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997868 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 468 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 18761000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997868 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 468 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 396 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 469 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 469 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 394 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 15879000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2941000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18820000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18820000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.997872 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.997872 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40098.484848 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40287.671233 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40127.931770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40127.931770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 192.950109 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed -system.cpu.numCycles 44590 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.regfile_manager.regFileAccesses 10530 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.regfile_manager.regFileReads 5947 # Number of Reads from Register File -system.cpu.regfile_manager.regFileWrites 4583 # Number of Writes to Register File -system.cpu.regfile_manager.regForwards 2845 # Number of Registers Read Through Forwarding Logic -system.cpu.runCycles 7168 # Number of cycles cpu stages are processed. -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage0.idleCycles 39847 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4743 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 10.636914 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 40758 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3832 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.593855 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 40488 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4102 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.199372 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 43180 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1410 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.162144 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40181 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4409 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.887867 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 11319 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini index 75367618d..ad4f6b32e 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -204,7 +204,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 99ccb1cf2..15c18bd45 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,16 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:18:54 -M5 started Apr 19 2011 12:19:08 -M5 executing on maize -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing +gem5 compiled Jun 19 2011 14:43:48 +gem5 started Jun 19 2011 14:43:49 +gem5 executing on zooks +command line: build/MIPS_SE/gem5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 21538000 because target called exit() +Exiting @ tick 19782000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index d39207b30..340c12899 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,282 +1,285 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 121226 # Simulator instruction rate (inst/s) -host_mem_usage 203988 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 446414211 # Simulator tick rate (ticks/s) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 19782000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 56447 # Simulator instruction rate (inst/s) +host_tick_rate 191567423 # Simulator tick rate (ticks/s) +host_mem_usage 158160 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21538000 # Number of ticks simulated -system.cpu.activity 13.954082 # Percentage of cycles cpu is active -system.cpu.agen_unit.agens 2404 # Number of Address Generations -system.cpu.branch_predictor.BTBHitPct 14.054054 # BTB Hit Percentage -system.cpu.branch_predictor.BTBHits 26 # Number of BTB hits -system.cpu.branch_predictor.BTBLookups 185 # Number of BTB lookups -system.cpu.branch_predictor.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.condIncorrect 844 # Number of conditional branches incorrect -system.cpu.branch_predictor.condPredicted 778 # Number of conditional branches predicted -system.cpu.branch_predictor.lookups 1066 # Number of BP lookups -system.cpu.branch_predictor.predictedNotTaken 949 # Number of Branches Predicted As Not Taken (False). -system.cpu.branch_predictor.predictedTaken 117 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. -system.cpu.comBranches 916 # Number of Branches instructions committed -system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.comInts 2155 # Number of Integer instructions committed +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 8 # Number of system calls +system.cpu.numCycles 39565 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 9153 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34165 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5400 # Number of cycles cpu stages are processed. +system.cpu.activity 13.648427 # Percentage of cycles cpu is active system.cpu.comLoads 1164 # Number of Load instructions committed -system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed -system.cpu.comNops 657 # Number of Nop instructions committed system.cpu.comStores 925 # Number of Store instructions committed +system.cpu.comBranches 916 # Number of Branches instructions committed +system.cpu.comNops 657 # Number of Nop instructions committed +system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed +system.cpu.comInts 2155 # Number of Integer instructions committed +system.cpu.comFloats 0 # Number of Floating Point instructions committed system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 7.392655 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 7.392655 # CPI: Total CPI of All Threads +system.cpu.cpi 6.789943 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.cpi_total 6.789943 # CPI: Total CPI of All Threads +system.cpu.ipc 0.147277 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.ipc_total 0.147277 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1173 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 886 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 609 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1011 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 413 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 40.850643 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 506 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 667 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5107 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8515 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 1342 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2229 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 313 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 287 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 600 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 316 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 65.502183 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3130 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed +system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed +system.cpu.stage0.idleCycles 35845 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3720 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 9.402249 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36724 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2841 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.180589 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 36774 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2791 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.054215 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 38322 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.141666 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36660 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.342348 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 13 # number of replacements +system.cpu.icache.tagsinuse 148.154290 # Cycle average of tags in use +system.cpu.icache.total_refs 442 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1.385580 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 148.154290 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.072341 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 442 # number of ReadReq hits +system.cpu.icache.demand_hits 442 # number of demand (read+write) hits +system.cpu.icache.overall_hits 442 # number of overall hits +system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses +system.cpu.icache.demand_misses 341 # number of demand (read+write) misses +system.cpu.icache.overall_misses 341 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 19026500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 19026500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 19026500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 783 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 783 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 783 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.435504 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.435504 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.435504 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55796.187683 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55796.187683 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55796.187683 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 16952000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 16952000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 16952000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.407407 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.407407 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.407407 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53141.065831 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53141.065831 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53141.065831 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 89.737794 # Cycle average of tags in use +system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 89.737794 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.021909 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1075 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 763 # number of WriteReq hits +system.cpu.dcache.demand_hits 1838 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1838 # number of overall hits +system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 162 # number of WriteReq misses +system.cpu.dcache.demand_misses 251 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 251 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5072500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 8910500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 13983000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 13983000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56676.136364 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53678.160920 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4987500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.075601 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 4670000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55935.483871 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53637.254902 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 832 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5202000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.100541 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 93 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 42 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2735500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 53100 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13.826087 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.076460 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.175135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.120153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.120153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55003.086420 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 55709.163347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 55709.163347 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 265500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56295.580110 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10189500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.086644 # miss rate for demand accesses -system.cpu.dcache.demand_misses 181 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7405500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 111 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 89.067186 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021745 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56295.580110 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1908 # number of overall hits -system.cpu.dcache.overall_miss_latency 10189500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.086644 # miss rate for overall accesses -system.cpu.dcache.overall_misses 181 # number of overall misses -system.cpu.dcache.overall_mshr_hits 43 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7405500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 4702500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2745500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7448000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 54051.724138 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53971.014493 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53971.014493 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 89.067186 # Cycle average of tags in use -system.cpu.dcache.total_refs 1908 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.execution_unit.executions 3261 # Number of Instructions Executed. -system.cpu.execution_unit.mispredictPct 92.139738 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.mispredicted 844 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 72 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predictedNotTakenIncorrect 812 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.predictedTakenIncorrect 32 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.icache.ReadReq_accesses 853 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55527.559055 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53156.739812 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 472 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 21156000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.446659 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 16957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.373974 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31000 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1.479624 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 62000 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 853 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55527.559055 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency -system.cpu.icache.demand_hits 472 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 21156000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.446659 # miss rate for demand accesses -system.cpu.icache.demand_misses 381 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 62 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 16957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.373974 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 145.295903 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.070945 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 853 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55527.559055 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 472 # number of overall hits -system.cpu.icache.overall_miss_latency 21156000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.446659 # miss rate for overall accesses -system.cpu.icache.overall_misses 381 # number of overall misses -system.cpu.icache.overall_mshr_hits 62 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 16957000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.373974 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 145.295903 # Cycle average of tags in use -system.cpu.icache.total_refs 472 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 37066 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.135269 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.135269 # IPC: Total IPC of All Threads -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52470.588235 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40235.294118 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2676000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 205.489748 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 205.489748 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006271 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2052000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 455 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 21170000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2682000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 23852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 23852000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52357.673267 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40153.465347 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21152500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16222000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52400.990099 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52588.235294 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52421.978022 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52421.978022 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52370.329670 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23828500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 18274000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 202.151439 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006169 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52370.329670 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23828500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 455 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 18274000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 16247000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2058000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18305000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40215.346535 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40352.941176 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 202.151439 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed -system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed -system.cpu.numCycles 43077 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.regfile_manager.regFileAccesses 10004 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.regfile_manager.regFileReads 6594 # Number of Reads from Register File -system.cpu.regfile_manager.regFileWrites 3410 # Number of Writes to Register File -system.cpu.regfile_manager.regForwards 1378 # Number of Registers Read Through Forwarding Logic -system.cpu.runCycles 6011 # Number of cycles cpu stages are processed. -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage0.idleCycles 39203 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3874 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 8.993198 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 40159 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2918 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 6.773916 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 40245 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2832 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 6.574274 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41757 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1320 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.064280 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 39874 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3203 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.435522 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 10193 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.timesIdled 427 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 8 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |