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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:20 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:20 -0500 |
| commit | 4c7a7796ade354a41fac9b4c14d4715cbe9e78c4 (patch) | |
| tree | ab16bb0360e685242aefa25f2743c342859ef4ec /util/checkpoint-tester.py | |
| parent | 5480ec798aba313a03c0760d88aeadff1037f48d (diff) | |
| download | gem5-4c7a7796ade354a41fac9b4c14d4715cbe9e78c4.tar.xz | |
ARM: Implement the Instruction Set Attribute Registers (ISAR).
The ISAR registers describe which features the processor supports.
Transcribe the values listed in section B5.2.5 of the ARM ARM
into the registers as read-only values
Diffstat (limited to 'util/checkpoint-tester.py')
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