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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-18 13:19:49 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-10 10:15:05 +0000 |
| commit | 3a5ff476ffdcfcef2a6d0427d9add590984596e7 (patch) | |
| tree | 6e3992c2a60ddeea4322b1f9ac04800de37de5e7 /util/checkpoint-tester.py | |
| parent | 55a10a13f93ed5bbc12790bfcbdfbbf1975f0211 (diff) | |
| download | gem5-3a5ff476ffdcfcef2a6d0427d9add590984596e7.tar.xz | |
arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
gem5-ARM is not using floatRegs anymore and moved towards the
vecRegs register file (which is used for SIMD&FP + SVE instructions)
Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'util/checkpoint-tester.py')
0 files changed, 0 insertions, 0 deletions