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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-08-07 14:51:17 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-08-07 14:51:17 -0500 |
commit | e0387415988a11f30b5aac66cd5cc32f7387e08e (patch) | |
tree | d0b6b1f6dd744c4cc491d4dca38c9063d69895cf /util/cpt_upgrader.py | |
parent | b5bb2a25aa702ad3d1a173e9e86d2addc24d9c13 (diff) | |
download | gem5-e0387415988a11f30b5aac66cd5cc32f7387e08e.tar.xz |
x86: add tlb checkpointing
This patch adds checkpointing support to x86 tlb. It upgrades the
cpt_upgrader.py script so that previously created checkpoints can
be updated. It moves the checkpoint version to 6.
Diffstat (limited to 'util/cpt_upgrader.py')
-rwxr-xr-x | util/cpt_upgrader.py | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py index e1f56b3ba..623c9b297 100755 --- a/util/cpt_upgrader.py +++ b/util/cpt_upgrader.py @@ -193,7 +193,21 @@ def from_4(cpt): del mr[137] cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr)) +# Version 6 of the checkpoint format adds tlb to x86 checkpoints +def from_5(cpt): + if cpt.get('root','isa') == 'x86': + for sec in cpt.sections(): + import re + # Search for all ISA sections + if re.search('.*sys.*\.cpu.*\.dtb$', sec): + cpt.set(sec, '_size', '0') + cpt.set(sec, 'lruSeq', '0') + if re.search('.*sys.*\.cpu.*\.itb$', sec): + cpt.set(sec, '_size', '0') + cpt.set(sec, 'lruSeq', '0') + else: + print "ISA is not x86" migrations = [] migrations.append(from_0) @@ -201,6 +215,7 @@ migrations.append(from_1) migrations.append(from_2) migrations.append(from_3) migrations.append(from_4) +migrations.append(from_5) verbose_print = False |