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authorNilay Vaish <nilay@cs.wisc.edu>2015-09-03 15:40:20 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-09-03 15:40:20 -0500
commit80b911afd573ecda0cefb8f24b83d94b7faf4b7b (patch)
tree95aa2f9794fe70fa812c63583f9db6602457b69e /util/cpt_upgraders/arm-contextidr-el2.py
parent2ab38ba13c6245480a08cd5b8651b5af8fce5a4b (diff)
parent87b9da2df4d4dc0028566a7803ee55159343d735 (diff)
downloadgem5-80b911afd573ecda0cefb8f24b83d94b7faf4b7b.tar.xz
merged with recent commits.
Diffstat (limited to 'util/cpt_upgraders/arm-contextidr-el2.py')
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diff --git a/util/cpt_upgraders/arm-contextidr-el2.py b/util/cpt_upgraders/arm-contextidr-el2.py
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+++ b/util/cpt_upgraders/arm-contextidr-el2.py
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+# Add the ARM CONTEXTIDR_EL2 miscreg.
+def upgrader(cpt):
+ if cpt.get('root','isa') == 'arm':
+ for sec in cpt.sections():
+ import re
+ # Search for all ISA sections
+ if re.search('.*sys.*\.cpu.*\.isa$', sec):
+ miscRegs = cpt.get(sec, 'miscRegs').split()
+ # CONTEXTIDR_EL2 defaults to 0b11111100000000000001
+ miscRegs[599:599] = [0xFC001]
+ cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in miscRegs))
+
+legacy_version = 14