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| author | Joel Hestness <hestness@cs.utexas.edu> | 2010-08-12 17:16:02 -0700 |
|---|---|---|
| committer | Joel Hestness <hestness@cs.utexas.edu> | 2010-08-12 17:16:02 -0700 |
| commit | 53c241fc16e4edaae8440b3dd360503537dbaba3 (patch) | |
| tree | 770f719bfdc90226ba7b755782382a3192513c78 /util/m5 | |
| parent | 2e9e75447a50146e0e8346de4362f7a4570f84ec (diff) | |
| download | gem5-53c241fc16e4edaae8440b3dd360503537dbaba3.tar.xz | |
TimingSimpleCPU: fix NO_ACCESS memory op handling
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op
doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs
to handle the case where the current status of the CPU is Running
and not DcacheWaitResponse or DTBWaitResponse
Diffstat (limited to 'util/m5')
0 files changed, 0 insertions, 0 deletions