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authorAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:58:24 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:58:24 -0600
commite6c31ceb2bf62da1241fe6cfcfbd67fd055ce8cd (patch)
tree84e831a6f5b211e0298a6d8266bd7d623a6dc1e0 /util/mkblankimage.sh
parent5fcf442f4f0d85c5f3fcf6bfd4ecbf37a1f3f4c9 (diff)
downloadgem5-e6c31ceb2bf62da1241fe6cfcfbd67fd055ce8cd.tar.xz
ARM: Don't return the result of a table walk the same cycle it's completed.
The L1 cache may have been accessed to provide this data, which confuses it, if it ends up being accesses twice in one cycle. Instead wait 1 tick which will force the timing simple CPU to forward to its next clock cycle when the translation completes. Also prevent multiple outstanding table walks from occuring at once.
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