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authorAndreas Hansson <andreas.hansson@arm.com>2014-05-09 18:58:48 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-05-09 18:58:48 -0400
commit5c2c3f598ee08875c273e78db7755e1306bea46e (patch)
tree88cec6722aa2bb4d8b35bbe1498ed829679b0f48 /util/oprofile-top.py
parentdbaf43394b23bbe8a3ed617d9f519a328cc8af6e (diff)
downloadgem5-5c2c3f598ee08875c273e78db7755e1306bea46e.tar.xz
mem: Make DRAM read/write switching less conservative
This patch changes the read/write event loop to use a single event (nextReqEvent), along with a state variable, thus joining the two control flows. This change makes it easier to follow the state transitions, and control what happens when. With the new loop we modify the overly conservative switching times such that the write-to-read switch allows bank preparation to happen in parallel with the bus turn around. Similarly, the read-to-write switch uses the introduced tRTW constraint.
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