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| author | Iru Cai <mytbk920423@gmail.com> | 2019-05-07 16:45:42 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 16:05:50 +0800 |
| commit | 37c22a55794fd442d783ef4ea161bf87e74227f5 (patch) | |
| tree | 9a116491a90e6366adc3d494c2683c65915ff7aa /util/statetrace/arch/tracechild_arm.hh | |
| parent | fe63e05867125d3899788bc4c72e677d195ae264 (diff) | |
| download | gem5-37c22a55794fd442d783ef4ea161bf87e74227f5.tar.xz | |
set cache latency
According to the configuration of the paper, L1 latency is 1 and L2 is 8
Change-Id: I1529e7336c033f56dcf1c132309da29b9687c7e3
Diffstat (limited to 'util/statetrace/arch/tracechild_arm.hh')
0 files changed, 0 insertions, 0 deletions