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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-27 04:56:00 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-27 04:56:00 -0400 |
| commit | a7a1e6004a0d2508913277b5c60d245fdcad2681 (patch) | |
| tree | fa367fcbea69318b4cf16e40d1799f5a08365eff /util/style.py | |
| parent | 801ce65eaeda04017ac0df544eaa4c8ffae98455 (diff) | |
| download | gem5-a7a1e6004a0d2508913277b5c60d245fdcad2681.tar.xz | |
mem: Ignore uncacheable MSHRs when finding matches
This patch changes how we search for matching MSHRs, ignoring any MSHR
that is allocated for an uncacheable access. By doing so, this patch
fixes a corner case in the MSHRs where incorrect data ended up being
copied into a (cacheable) read packet due to a first uncacheable MSHR
target of size 4, followed by a cacheable target to the same MSHR of
size 64. The latter target was filled with nonsense data.
Diffstat (limited to 'util/style.py')
0 files changed, 0 insertions, 0 deletions