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author | Christian Menard <christian.menard@tu-dresden.de> | 2017-05-23 00:48:52 +0200 |
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committer | Christian Menard <christian.menard@tu-dresden.de> | 2017-05-30 10:47:32 +0000 |
commit | 01921763a47d1ed2238ee5d4435edbf752783a95 (patch) | |
tree | 3c1a8f43e2baeeaec04208f297b9e782e9393eae /util/tlm/examples/master_port/tlm.py | |
parent | 6e8b0f659602602765fcfdb4d32a8aa2548d669e (diff) | |
download | gem5-01921763a47d1ed2238ee5d4435edbf752783a95.tar.xz |
misc: Reorder sources in util/tlm and rewrite build scripts
* Use one SConstruct to build everything instead of one SConstruct for
each example.
* Introduce SConscripts for sub-directories.
* Build in 'build' instead of the source tree.
* Build and link to SystemC from the ext/systemc directory. This
ensures that SystemC does not need to be installed on the host and
avoids possible issues caused by an incompatible SystemC build.
* Update the README and add some minor fixes
Change-Id: I641ed94f542626864fb7af499ad1be8fd4ad929f
Reviewed-on: https://gem5-review.googlesource.com/3480
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'util/tlm/examples/master_port/tlm.py')
-rw-r--r-- | util/tlm/examples/master_port/tlm.py | 75 |
1 files changed, 0 insertions, 75 deletions
diff --git a/util/tlm/examples/master_port/tlm.py b/util/tlm/examples/master_port/tlm.py deleted file mode 100644 index 0b017a6d1..000000000 --- a/util/tlm/examples/master_port/tlm.py +++ /dev/null @@ -1,75 +0,0 @@ -# -# Copyright (c) 2016, Dresden University of Technology (TU Dresden) -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Christian Menard -# - -import m5 -from m5.objects import * - -import os - -# Base System Architecture: -# +-----+ ^ -# | TLM | | TLM World -# +--+--+ | (see main.cc) -# | v -# +----------v-----------+ External Port (see sc_master_port.*) -# | Membus | ^ -# +----------+-----------+ | -# | | gem5 World -# +---v----+ | -# | Memory | | -# +--------+ v -# - -# Create a system with a Crossbar and a simple Memory: -system = System() -system.membus = IOXBar(width = 16) -system.physmem = SimpleMemory(range = AddrRange('512MB')) -system.clk_domain = SrcClockDomain(clock = '1.5GHz', - voltage_domain = VoltageDomain(voltage = '1V')) - -# Create a external TLM port: -system.tlm = ExternalMaster() -system.tlm.port_type = "tlm_master" -system.tlm.port_data = "transactor" - -# Route the connections: -system.system_port = system.membus.slave -system.physmem.port = system.membus.master -system.tlm.port = system.membus.slave -system.mem_mode = 'timing' - -# Start the simulation: -root = Root(full_system = False, system = system) -m5.instantiate() -m5.simulate() |