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| author | Christian Menard <Christian.Menard@tu-dresden.de> | 2017-02-09 19:15:41 -0500 |
|---|---|---|
| committer | Christian Menard <Christian.Menard@tu-dresden.de> | 2017-02-09 19:15:41 -0500 |
| commit | 03f740664bc8db8890359c9c5ad02df9db478bae (patch) | |
| tree | 27de717f997634ca22d04200a51b54305244929b /util/tlm/examples/master_port/tlm.py | |
| parent | ccd9210e1a1bdce828a13a4ffdf84548ffe61592 (diff) | |
| download | gem5-03f740664bc8db8890359c9c5ad02df9db478bae.tar.xz | |
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
Changeset 11798:3a490c57058d
---------------------------
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Introduce transactor modules that represent the gem5 ports in the
* SystemC world.
* Update the SimControl module and let it keep track of the gem5 ports.
Reviewed at http://reviews.gem5.org/r/3775/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'util/tlm/examples/master_port/tlm.py')
| -rw-r--r-- | util/tlm/examples/master_port/tlm.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/tlm/examples/master_port/tlm.py b/util/tlm/examples/master_port/tlm.py index 13c4388a9..0b017a6d1 100644 --- a/util/tlm/examples/master_port/tlm.py +++ b/util/tlm/examples/master_port/tlm.py @@ -61,7 +61,7 @@ system.clk_domain = SrcClockDomain(clock = '1.5GHz', # Create a external TLM port: system.tlm = ExternalMaster() system.tlm.port_type = "tlm_master" -system.tlm.port_data = "memory" +system.tlm.port_data = "transactor" # Route the connections: system.system_port = system.membus.slave |