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author | Christian Menard <Christian.Menard@tu-dresden.de> | 2017-02-09 19:15:30 -0500 |
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committer | Christian Menard <Christian.Menard@tu-dresden.de> | 2017-02-09 19:15:30 -0500 |
commit | b25ea094d4350b8257d5f383a123ea620b614adf (patch) | |
tree | bf2be24b719fb45325012542bb77288f18ccb66e /util/tlm/examples/slave_port/sc_target.hh | |
parent | 41a61589545c284d109019c3cb528762b8345aa0 (diff) | |
download | gem5-b25ea094d4350b8257d5f383a123ea620b614adf.tar.xz |
misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Restructure the existing sources in preparation of the addition of the
* new
Master Port.
* Refractor names to allow for distinction of the slave and master port.
* Replace the Makefile by a SConstruct.
Testing Done: The examples provided in util/tlm (now
util/tlm/examples/slave_port) still compile and run error free.
Reviewed at http://reviews.gem5.org/r/3527/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'util/tlm/examples/slave_port/sc_target.hh')
-rw-r--r-- | util/tlm/examples/slave_port/sc_target.hh | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/util/tlm/examples/slave_port/sc_target.hh b/util/tlm/examples/slave_port/sc_target.hh new file mode 100644 index 000000000..7a2d075d9 --- /dev/null +++ b/util/tlm/examples/slave_port/sc_target.hh @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2015, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Matthias Jung + */ + +#ifndef __SIM_SC_TARGET_HH__ +#define __SIM_SC_TARGET_HH__ + +#include <tlm_utils/peq_with_cb_and_phase.h> +#include <tlm_utils/simple_target_socket.h> + +#include <iostream> +#include <systemc> +#include <tlm> + +using namespace sc_core; +using namespace std; + +struct Target: sc_module +{ + /** TLM interface socket: */ + tlm_utils::simple_target_socket<Target> socket; + + /** TLM related member variables: */ + tlm::tlm_generic_payload* transaction_in_progress; + sc_event target_done_event; + bool response_in_progress; + bool debug; + tlm::tlm_generic_payload* next_response_pending; + tlm::tlm_generic_payload* end_req_pending; + tlm_utils::peq_with_cb_and_phase<Target> m_peq; + + /** Storage, may be implemented with a map for large devices */ + unsigned char *mem; + + Target(sc_core::sc_module_name name, + bool debug, + unsigned long long int size, + unsigned int offset); + SC_HAS_PROCESS(Target); + + /** TLM interface functions */ + virtual void b_transport(tlm::tlm_generic_payload& trans, + sc_time& delay); + virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans); + virtual tlm::tlm_sync_enum nb_transport_fw( + tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, + sc_time& delay); + + /** Callback of Payload Event Queue: */ + void peq_cb(tlm::tlm_generic_payload& trans, + const tlm::tlm_phase& phase); + + /** Helping function common to b_transport and nb_transport */ + void execute_transaction(tlm::tlm_generic_payload& trans); + + /** Helping functions and processes: */ + void send_end_req(tlm::tlm_generic_payload& trans); + void send_response(tlm::tlm_generic_payload& trans); + + /** Method process that runs on target_done_event */ + void execute_transaction_process(); + + /** Helping Variables **/ + unsigned long long int size; + unsigned offset; +}; + +#endif //__SIM_SC_TARGET_HH__ + |