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author | Christian Menard <Christian.Menard@tu-dresden.de> | 2017-02-09 19:15:30 -0500 |
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committer | Christian Menard <Christian.Menard@tu-dresden.de> | 2017-02-09 19:15:30 -0500 |
commit | b25ea094d4350b8257d5f383a123ea620b614adf (patch) | |
tree | bf2be24b719fb45325012542bb77288f18ccb66e /util/tlm/examples/slave_port/tgen.cfg | |
parent | 41a61589545c284d109019c3cb528762b8345aa0 (diff) | |
download | gem5-b25ea094d4350b8257d5f383a123ea620b614adf.tar.xz |
misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Restructure the existing sources in preparation of the addition of the
* new
Master Port.
* Refractor names to allow for distinction of the slave and master port.
* Replace the Makefile by a SConstruct.
Testing Done: The examples provided in util/tlm (now
util/tlm/examples/slave_port) still compile and run error free.
Reviewed at http://reviews.gem5.org/r/3527/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'util/tlm/examples/slave_port/tgen.cfg')
-rw-r--r-- | util/tlm/examples/slave_port/tgen.cfg | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/util/tlm/examples/slave_port/tgen.cfg b/util/tlm/examples/slave_port/tgen.cfg new file mode 100644 index 000000000..e341d8574 --- /dev/null +++ b/util/tlm/examples/slave_port/tgen.cfg @@ -0,0 +1,57 @@ +# Copyright (c) 2015, University of Kaiserslautern +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Matthias Jung + + +# This format supports comments using the '#' symbol as the leading +# character of the line +# +# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order, +# where the states are the nodes in the graph, init describes what +# state to start in, and transition describes the edges of the graph. +# +# STATE <id> <duration (ticks)> <type> +# +# State IDLE idles +# +# States LINEAR and RANDOM have additional <percent reads> <start addr> +# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)> +# <data limit (bytes)> +# +# State TRACE plays back a pre-recorded trace once +# +# Addresses are expressed as decimal numbers. The period in the linear +# and random state is from a uniform random distribution over the +# interval. If a specific value is desired, then the min and max can +# be set to the same value. +STATE 0 1000000 LINEAR 50 0 256 4 5000 5000 64 +INIT 0 +TRANSITION 0 0 1 |