misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Restructure the existing sources in preparation of the addition of the
 * new
   Master Port.
 * Refractor names to allow for distinction of the slave and master port.
 * Replace the Makefile by a SConstruct.

Testing Done: The examples provided in util/tlm (now
util/tlm/examples/slave_port) still compile and run error free.

Reviewed at http://reviews.gem5.org/r/3527/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

8 files changed, 867 insertions, 0 deletions

diff --git a/util/tlm/examples/slave_port/SConstruct b/util/tlm/examples/slave_port/SConstruct
new file mode 100644
index 000000000..8ca9959a0
--- /dev/null
+++ b/util/tlm/examples/slave_port/SConstruct
@@ -0,0 +1,77 @@
+#!python
+
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+#    contributors may be used to endorse or promote products derived from
+#    this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+
+import os
+
+gem5_arch = 'ARM'
+gem5_variant = 'opt'
+#gem5_variant = 'debug'
+
+gem5_root = '#../../../..'
+
+target = 'gem5.' + gem5_variant + '.sc'
+
+env = Environment()
+
+# Import PKG_CONFIG_PATH from the external environment
+if os.environ.has_key('PKG_CONFIG_PATH'):
+    env['ENV']['PKG_CONFIG_PATH'] = os.environ['PKG_CONFIG_PATH']
+
+# search for SystemC
+env.ParseConfig('pkg-config --cflags --libs systemc')
+
+# add include dirs
+env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch,
+                    gem5_root + '/util/systemc',
+                    gem5_root + '/util/tlm'])
+
+env.Append(LIBS=['gem5_' + gem5_variant])
+env.Append(LIBPATH=[gem5_root + '/build/' + gem5_arch])
+
+env.Append(CXXFLAGS=['-std=c++11',
+                     '-DSC_INCLUDE_DYNAMIC_PROCESSES',
+                     '-DTRACING_ON'])
+
+if gem5_variant == 'debug':
+    env.Append(CXXFLAGS=['-g', '-DDEBUG'])
+
+src_systemc = [gem5_root + '/util/systemc/sc_gem5_control.cc',
+               gem5_root + '/util/systemc/sc_logger.cc',
+               gem5_root + '/util/systemc/sc_module.cc',
+               gem5_root + '/util/systemc/stats.cc']
+
+src_tlm     = Glob(gem5_root + '/util/tlm/*.cc')
+src_main    = Glob('*.cc')
+
+main = env.Program(target, src_systemc + src_tlm + src_main)
diff --git a/util/tlm/examples/slave_port/main.cc b/util/tlm/examples/slave_port/main.cc
new file mode 100644
index 000000000..256a99d1b
--- /dev/null
+++ b/util/tlm/examples/slave_port/main.cc
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ *          Christian Menard
+ *          Abdul Mutaal Ahmad
+ */
+
+/**
+ * @file
+ *
+ *  Example top level file for SystemC-TLM integration with C++-only
+ *  instantiation.
+ *
+ */
+
+#include <tlm_utils/simple_target_socket.h>
+
+#include <systemc>
+#include <tlm>
+
+#include "sc_target.hh"
+#include "sim_control.hh"
+#include "stats.hh"
+
+// Defining global string variable decalred in stats.hh
+std::string filename;
+
+void
+reportHandler(const sc_core::sc_report &report,
+              const sc_core::sc_actions &actions)
+{
+    uint64_t systemc_time = report.get_time().value();
+    uint64_t gem5_time = curTick();
+
+    std::cerr << report.get_time();
+
+    if (gem5_time < systemc_time) {
+        std::cerr << " (<) ";
+    } else if (gem5_time > systemc_time) {
+        std::cerr << " (!) ";
+    } else {
+        std::cerr << " (=) ";
+    }
+
+    std::cerr << ": " << report.get_msg_type()
+              << ' ' << report.get_msg() << '\n';
+}
+
+int
+sc_main(int argc, char **argv)
+{
+    sc_core::sc_report_handler::set_handler(reportHandler);
+
+    SimControl sim_control("gem5", argc, argv);
+    Target *memory;
+
+    filename = "m5out/stats-systemc.txt";
+
+    tlm::tlm_initiator_socket <> *mem_port =
+        dynamic_cast<tlm::tlm_initiator_socket<> *>(
+                    sc_core::sc_find_object("gem5.memory")
+                );
+
+    if (mem_port) {
+        SC_REPORT_INFO("sc_main", "Port Found");
+        unsigned long long int size = 512*1024*1024ULL;
+        memory = new Target("memory",
+                            sim_control.getDebugFlag(),
+                            size,
+                            sim_control.getOffset());
+
+        memory->socket.bind(*mem_port);
+    } else {
+        SC_REPORT_FATAL("sc_main", "Port Not Found");
+        std::exit(EXIT_FAILURE);
+    }
+
+    sc_core::sc_start();
+
+    SC_REPORT_INFO("sc_main", "End of Simulation");
+
+    CxxConfig::statsDump();
+
+    return EXIT_SUCCESS;
+}
diff --git a/util/tlm/examples/slave_port/run_gem5.sh b/util/tlm/examples/slave_port/run_gem5.sh
new file mode 100644
index 000000000..a4a0b8021
--- /dev/null
+++ b/util/tlm/examples/slave_port/run_gem5.sh
@@ -0,0 +1,53 @@
+#!/bin/bash
+# Copyright (c) 2015, University of Kaiserslautern
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+# 1. Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+# 
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+# 
+# 3. Neither the name of the copyright holder nor the names of its
+#    contributors may be used to endorse or promote products derived from
+#    this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# 
+# Authors: Matthias Jung
+
+# Color Definition:
+RCol='\e[0m'; # Text Reset
+BGre='\e[1;31m';
+echo -e "\n${BGre}Create gem5 Configuration${RCol}\n"
+
+../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py \
+--tlm-memory=memory                                         \
+--cpu-type=timing                                           \
+--num-cpu=1                                                 \
+--mem-type=SimpleMemory                                     \
+--mem-size=512MB                                            \
+--mem-channels=1                                            \
+--caches --l2cache                                          \
+--machine-type=VExpress_EMM                                 \
+--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
+--kernel=vmlinux.aarch32.ll_20131205.0-gem5
+
+echo -e "\n${BGre}Run gem5 ${RCol}\n"
+
+time ./gem5.opt.sc m5out/config.ini -o 2147483648 
diff --git a/util/tlm/examples/slave_port/sc_target.cc b/util/tlm/examples/slave_port/sc_target.cc
new file mode 100644
index 000000000..c44a27149
--- /dev/null
+++ b/util/tlm/examples/slave_port/sc_target.cc
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ */
+
+#include "sc_target.hh"
+
+using namespace sc_core;
+using namespace std;
+
+Target::Target(sc_core::sc_module_name name,
+    bool debug,
+    unsigned long long int size,
+    unsigned int offset) :
+    socket("socket"),
+    transaction_in_progress(0),
+    response_in_progress(false),
+    next_response_pending(0),
+    end_req_pending(0),
+    m_peq(this, &Target::peq_cb),
+    debug(debug),
+    size(size),
+    offset(offset)
+{
+    /* Register tlm transport functions */
+    socket.register_b_transport(this, &Target::b_transport);
+    socket.register_transport_dbg(this, &Target::transport_dbg);
+    socket.register_nb_transport_fw(this, &Target::nb_transport_fw);
+
+
+    /* allocate storage memory */
+    mem = new unsigned char[size];
+
+    SC_METHOD(execute_transaction_process);
+    sensitive << target_done_event;
+    dont_initialize();
+}
+
+void
+Target::b_transport(tlm::tlm_generic_payload& trans, sc_time& delay)
+{
+    /* Execute the read or write commands */
+    execute_transaction(trans);
+}
+
+unsigned int
+Target::transport_dbg(tlm::tlm_generic_payload& trans)
+{
+    tlm::tlm_command cmd = trans.get_command();
+    sc_dt::uint64    adr = trans.get_address() - offset;
+    unsigned char*   ptr = trans.get_data_ptr();
+    unsigned int     len = trans.get_data_length();
+
+    unsigned char *mem_array_ptr = mem + adr;
+
+    /* Load / Store the access: */
+    if ( cmd == tlm::TLM_READ_COMMAND ) {
+        if (debug) {
+            SC_REPORT_INFO("target", "tlm::TLM_READ_COMMAND");
+        }
+        std::memcpy(ptr, mem_array_ptr, len);
+    } else if ( cmd == tlm::TLM_WRITE_COMMAND ) {
+        if (debug) {
+            SC_REPORT_INFO("target", "tlm::TLM_WRITE_COMMAND");
+        }
+        std::memcpy(mem_array_ptr, ptr, len);
+    }
+
+    return len;
+}
+
+
+/* TLM-2 non-blocking transport method */
+tlm::tlm_sync_enum Target::nb_transport_fw(tlm::tlm_generic_payload& trans,
+                                           tlm::tlm_phase& phase,
+                                           sc_time& delay)
+{
+    /* Queue the transaction until the annotated time has elapsed */
+    m_peq.notify(trans, phase, delay);
+    return tlm::TLM_ACCEPTED;
+}
+
+void
+Target::peq_cb(tlm::tlm_generic_payload& trans,
+               const tlm::tlm_phase& phase)
+{
+    sc_time delay;
+
+    if (phase == tlm::BEGIN_REQ) {
+        if (debug) SC_REPORT_INFO("target", "tlm::BEGIN_REQ");
+
+        /* Increment the transaction reference count */
+        trans.acquire();
+
+        if ( !transaction_in_progress ) {
+            send_end_req(trans);
+        } else {
+            /* Put back-pressure on initiator by deferring END_REQ until
+             * pipeline is clear */
+            end_req_pending = &trans;
+        }
+    } else if (phase == tlm::END_RESP) {
+        /* On receiving END_RESP, the target can release the transaction and
+         * allow other pending transactions to proceed */
+        if (!response_in_progress) {
+            SC_REPORT_FATAL("TLM-2", "Illegal transaction phase END_RESP"
+                            "received by target");
+        }
+
+        transaction_in_progress = 0;
+
+        /* Target itself is now clear to issue the next BEGIN_RESP */
+        response_in_progress = false;
+        if (next_response_pending) {
+            send_response( *next_response_pending );
+            next_response_pending = 0;
+        }
+
+        /* ... and to unblock the initiator by issuing END_REQ */
+        if (end_req_pending) {
+            send_end_req( *end_req_pending );
+            end_req_pending = 0;
+        }
+
+    } else /* tlm::END_REQ or tlm::BEGIN_RESP */ {
+            SC_REPORT_FATAL("TLM-2", "Illegal transaction phase received by"
+                            "target");
+    }
+}
+
+void
+Target::send_end_req(tlm::tlm_generic_payload& trans)
+{
+    tlm::tlm_phase bw_phase;
+    sc_time delay;
+
+    /* Queue the acceptance and the response with the appropriate latency */
+    bw_phase = tlm::END_REQ;
+    delay = sc_time(10.0, SC_NS); // Accept delay
+
+    tlm::tlm_sync_enum status;
+    status = socket->nb_transport_bw(trans, bw_phase, delay);
+
+    /* Ignore return value;
+     * initiator cannot terminate transaction at this point
+     * Queue internal event to mark beginning of response: */
+    delay = delay + sc_time(40.0, SC_NS); // Latency
+    target_done_event.notify(delay);
+
+    assert(transaction_in_progress == 0);
+    transaction_in_progress = &trans;
+}
+
+void
+Target::execute_transaction_process()
+{
+    /* Execute the read or write commands */
+    execute_transaction( *transaction_in_progress );
+
+    /* Target must honor BEGIN_RESP/END_RESP exclusion rule; i.e. must not
+     * send BEGIN_RESP until receiving previous END_RESP or BEGIN_REQ */
+    if (response_in_progress) {
+        /* Target allows only two transactions in-flight */
+        if (next_response_pending) {
+            SC_REPORT_FATAL("TLM-2", "Attempt to have two pending responses"
+                            "in target");
+        }
+        next_response_pending = transaction_in_progress;
+    } else {
+        send_response( *transaction_in_progress );
+    }
+}
+
+void
+Target::execute_transaction(tlm::tlm_generic_payload& trans)
+{
+    tlm::tlm_command cmd = trans.get_command();
+    sc_dt::uint64    adr = trans.get_address() - offset;
+    unsigned char*   ptr = trans.get_data_ptr();
+    unsigned int     len = trans.get_data_length();
+    unsigned char*   byt = trans.get_byte_enable_ptr();
+    unsigned int     wid = trans.get_streaming_width();
+
+    if ( byt != 0 ) {
+        cout << "Byte Error" << endl;
+        trans.set_response_status( tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE );
+        return;
+    }
+
+    //if ( len > 4 || wid < len ) {
+    //    cout << "Burst Error len=" << len << " wid=" << wid << endl;
+    //    trans.set_response_status( tlm::TLM_BURST_ERROR_RESPONSE );
+    //    return;
+    //}
+
+    unsigned char *mem_array_ptr = mem + adr;
+
+    /* Load / Store the access: */
+    if ( cmd == tlm::TLM_READ_COMMAND ) {
+        if (debug) {
+            SC_REPORT_INFO("target", "tlm::TLM_READ_COMMAND");
+        }
+        std::memcpy(ptr, mem_array_ptr, len);
+    } else if ( cmd == tlm::TLM_WRITE_COMMAND ) {
+        if (debug) {
+            SC_REPORT_INFO("target", "tlm::TLM_WRITE_COMMAND");
+        }
+        std::memcpy(mem_array_ptr, ptr, len);
+    }
+
+    trans.set_response_status( tlm::TLM_OK_RESPONSE );
+}
+
+void
+Target::send_response(tlm::tlm_generic_payload& trans)
+{
+    tlm::tlm_sync_enum status;
+    tlm::tlm_phase bw_phase;
+    sc_time delay;
+
+    response_in_progress = true;
+    bw_phase = tlm::BEGIN_RESP;
+    delay = sc_time(10.0, SC_NS);
+    status = socket->nb_transport_bw( trans, bw_phase, delay );
+
+    if (status == tlm::TLM_UPDATED) {
+        /* The timing annotation must be honored */
+        m_peq.notify(trans, bw_phase, delay);
+    } else if (status == tlm::TLM_COMPLETED) {
+        /* The initiator has terminated the transaction */
+        transaction_in_progress = 0;
+        response_in_progress = false;
+    }
+    trans.release();
+}
diff --git a/util/tlm/examples/slave_port/sc_target.hh b/util/tlm/examples/slave_port/sc_target.hh
new file mode 100644
index 000000000..7a2d075d9
--- /dev/null
+++ b/util/tlm/examples/slave_port/sc_target.hh
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ */
+
+#ifndef __SIM_SC_TARGET_HH__
+#define __SIM_SC_TARGET_HH__
+
+#include <tlm_utils/peq_with_cb_and_phase.h>
+#include <tlm_utils/simple_target_socket.h>
+
+#include <iostream>
+#include <systemc>
+#include <tlm>
+
+using namespace sc_core;
+using namespace std;
+
+struct Target: sc_module
+{
+    /** TLM interface socket: */
+    tlm_utils::simple_target_socket<Target> socket;
+
+    /** TLM related member variables: */
+    tlm::tlm_generic_payload*  transaction_in_progress;
+    sc_event                   target_done_event;
+    bool                       response_in_progress;
+    bool                       debug;
+    tlm::tlm_generic_payload*  next_response_pending;
+    tlm::tlm_generic_payload*  end_req_pending;
+    tlm_utils::peq_with_cb_and_phase<Target> m_peq;
+
+    /** Storage, may be implemented with a map for large devices */
+    unsigned char *mem;
+
+    Target(sc_core::sc_module_name name,
+        bool debug,
+        unsigned long long int size,
+        unsigned int offset);
+    SC_HAS_PROCESS(Target);
+
+    /** TLM interface functions */
+    virtual void b_transport(tlm::tlm_generic_payload& trans,
+                             sc_time& delay);
+    virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
+    virtual tlm::tlm_sync_enum nb_transport_fw(
+                tlm::tlm_generic_payload& trans,
+                tlm::tlm_phase& phase,
+                sc_time& delay);
+
+    /** Callback of Payload Event Queue: */
+    void peq_cb(tlm::tlm_generic_payload& trans,
+                const tlm::tlm_phase& phase);
+
+    /** Helping function common to b_transport and nb_transport */
+    void execute_transaction(tlm::tlm_generic_payload& trans);
+
+    /** Helping functions and processes: */
+    void send_end_req(tlm::tlm_generic_payload& trans);
+    void send_response(tlm::tlm_generic_payload& trans);
+
+    /** Method process that runs on target_done_event */
+    void execute_transaction_process();
+
+    /** Helping Variables **/
+    unsigned long long int size;
+    unsigned offset;
+};
+
+#endif //__SIM_SC_TARGET_HH__
+
diff --git a/util/tlm/examples/slave_port/tgen.cfg b/util/tlm/examples/slave_port/tgen.cfg
new file mode 100644
index 000000000..e341d8574
--- /dev/null
+++ b/util/tlm/examples/slave_port/tgen.cfg
@@ -0,0 +1,57 @@
+# Copyright (c) 2015, University of Kaiserslautern
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+# 1. Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+# 
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+# 
+# 3. Neither the name of the copyright holder nor the names of its
+#    contributors may be used to endorse or promote products derived from
+#    this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# 
+# Authors: Matthias Jung
+
+
+# This format supports comments using the '#' symbol as the leading
+# character of the line
+#
+# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order,
+# where the states are the nodes in the graph, init describes what
+# state to start in, and transition describes the edges of the graph.
+#
+# STATE <id> <duration (ticks)> <type>
+#
+# State IDLE idles
+#
+# States LINEAR and RANDOM have additional <percent reads> <start addr>
+# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)>
+# <data limit (bytes)>
+#
+# State TRACE plays back a pre-recorded trace once
+#
+# Addresses are expressed as decimal numbers. The period in the linear
+# and random state is from a uniform random distribution over the
+# interval. If a specific value is desired, then the min and max can
+# be set to the same value.
+STATE 0 1000000 LINEAR 50 0 256 4 5000 5000 64
+INIT 0
+TRANSITION 0 0 1
diff --git a/util/tlm/examples/slave_port/tlm.py b/util/tlm/examples/slave_port/tlm.py
new file mode 100644
index 000000000..9d6b26db1
--- /dev/null
+++ b/util/tlm/examples/slave_port/tlm.py
@@ -0,0 +1,78 @@
+# Copyright (c) 2015, University of Kaiserslautern
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+#    contributors may be used to endorse or promote products derived from
+#    this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matthias Jung
+
+import m5
+from m5.objects import *
+
+# This configuration shows a simple setup of a TrafficGen (CPU) and an
+# external TLM port for SystemC co-simulation
+#
+# Base System Architecture:
+# +-------------+  +-----+    ^
+# | System Port |  | CPU |    |
+# +-------+-----+  +--+--+    |
+#         |           |       | gem5 World
+#         |      +----+       | (see this file)
+#         |      |            |
+# +-------v------v-------+    |
+# |        Membus        |    v
+# +----------------+-----+    External Port (see sc_slave_port.*)
+#                  |          ^
+#              +---v---+      | TLM World
+#              |  TLM  |      | (see sc_target.*)
+#              +-------+      v
+#
+
+# Create a system with a Crossbar and a TrafficGenerator as CPU:
+system = System()
+system.membus = IOXBar(width = 16)
+system.physmem = SimpleMemory() # This must be instanciated, even if not needed
+system.cpu = TrafficGen(config_file = "tgen.cfg")
+system.clk_domain = SrcClockDomain(clock = '1.5GHz',
+    voltage_domain = VoltageDomain(voltage = '1V'))
+
+# Create a external TLM port:
+system.tlm = ExternalSlave()
+system.tlm.addr_ranges = [AddrRange('512MB')]
+system.tlm.port_type = "tlm_slave"
+system.tlm.port_data = "memory"
+
+# Route the connections:
+system.cpu.port = system.membus.slave
+system.system_port = system.membus.slave
+system.membus.master = system.tlm.port
+
+# Start the simulation:
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'
+m5.instantiate()
+m5.simulate() #Simulation time specified later on commandline
diff --git a/util/tlm/examples/slave_port/tlm_elastic.py b/util/tlm/examples/slave_port/tlm_elastic.py
new file mode 100644
index 000000000..3de0670c0
--- /dev/null
+++ b/util/tlm/examples/slave_port/tlm_elastic.py
@@ -0,0 +1,123 @@
+# Copyright (c) 2016, University of Kaiserslautern
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+#    contributors may be used to endorse or promote products derived from
+#    this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matthias Jung
+
+import m5
+import optparse
+
+from m5.objects import *
+from m5.util import addToPath, fatal
+
+addToPath('../../configs/common/')
+
+from Caches import *
+
+# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
+# and an external TLM port for SystemC co-simulation.
+#
+# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
+#
+# Base System Architecture:
+#
+#                  +-----------+       ^
+# +-------------+  | eTraceCPU |       |
+# | System Port |  +-----+-----+       |
+# +------+------+  | $D1 | $I1 |       |
+#        |         +--+--+--+--+       |
+#        |            |     |          | gem5 World
+#        |            |     |          | (see this file)
+#        |            |     |          |
+# +------v------------v-----v--+       |
+# |           Membus           |       v
+# +----------------+-----------+       External Port (see sc_port.*)
+#                  |                   ^
+#              +---v---+               | TLM World
+#              |  TLM  |               | (see sc_target.*)
+#              +-------+               v
+#
+#
+# Create a system with a Crossbar and an Elastic Trace Player as CPU:
+
+# Setup System:
+system = System(cpu=TraceCPU(cpu_id=0),
+                mem_mode='timing',
+                mem_ranges = [AddrRange('512MB')],
+                cache_line_size = 64)
+
+# Create a top-level voltage domain:
+system.voltage_domain = VoltageDomain()
+
+# Create a source clock for the system. This is used as the clock period for
+# xbar and memory:
+system.clk_domain = SrcClockDomain(clock =  '1GHz',
+        voltage_domain = system.voltage_domain)
+
+# Create a CPU voltage domain:
+system.cpu_voltage_domain = VoltageDomain()
+
+# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
+# is actually used only by the caches connected to the CPU:
+system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
+        voltage_domain = system.cpu_voltage_domain)
+
+# Setup CPU and its L1 caches:
+system.cpu.createInterruptController()
+system.cpu.icache = L1_ICache(size="32kB")
+system.cpu.dcache = L1_DCache(size="32kB")
+system.cpu.icache.cpu_side = system.cpu.icache_port
+system.cpu.dcache.cpu_side = system.cpu.dcache_port
+
+# Assign input trace files to the eTraceCPU:
+system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
+system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
+
+# Setting up L1 BUS:
+system.membus = IOXBar(width = 16)
+system.physmem = SimpleMemory() # This must be instantiated, even if not needed
+
+# Create a external TLM port:
+system.tlm = ExternalSlave()
+system.tlm.addr_ranges = [AddrRange('512MB')]
+system.tlm.port_type = "tlm"
+system.tlm.port_data = "memory"
+
+# Connect everything:
+system.membus = SystemXBar()
+system.system_port = system.membus.slave
+system.cpu.icache.mem_side = system.membus.slave
+system.cpu.dcache.mem_side = system.membus.slave
+system.membus.master = system.tlm.port
+
+# Start the simulation:
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'
+m5.instantiate()
+m5.simulate() #Simulation time specified later on commandline