misc: Reorder sources in util/tlm and rewrite build scripts

* Use one SConstruct to build everything instead of one SConstruct for
  each example.
* Introduce SConscripts for sub-directories.
* Build in 'build' instead of the source tree.
* Build and link to SystemC from the ext/systemc directory. This
  ensures that SystemC does not need to be installed on the host and
  avoids possible issues caused by an incompatible SystemC build.
* Update the README and add some minor fixes

Change-Id: I641ed94f542626864fb7af499ad1be8fd4ad929f
Reviewed-on: https://gem5-review.googlesource.com/3480
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

7 files changed, 43 insertions, 454 deletions

diff --git a/util/tlm/examples/slave_port/tgen.cfg b/util/tlm/examples/common/SConscript
index e341d8574..8f83d523b 100644
--- a/util/tlm/examples/slave_port/tgen.cfg
+++ b/util/tlm/examples/common/SConscript
@@ -1,21 +1,23 @@
-# Copyright (c) 2015, University of Kaiserslautern
+#!python
+
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
 # All rights reserved.
-# 
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
 # met:
-# 
+#
 # 1. Redistributions of source code must retain the above copyright notice,
 #    this list of conditions and the following disclaimer.
-# 
+#
 # 2. Redistributions in binary form must reproduce the above copyright
 #    notice, this list of conditions and the following disclaimer in the
 #    documentation and/or other materials provided with the distribution.
-# 
+#
 # 3. Neither the name of the copyright holder nor the names of its
 #    contributors may be used to endorse or promote products derived from
 #    this software without specific prior written permission.
-# 
+#
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 # TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
@@ -27,31 +29,15 @@
 # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-# 
-# Authors: Matthias Jung
+#
+# Authors: Christian Menard
 
+Import('env')
 
-# This format supports comments using the '#' symbol as the leading
-# character of the line
-#
-# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order,
-# where the states are the nodes in the graph, init describes what
-# state to start in, and transition describes the edges of the graph.
-#
-# STATE <id> <duration (ticks)> <type>
-#
-# State IDLE idles
-#
-# States LINEAR and RANDOM have additional <percent reads> <start addr>
-# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)>
-# <data limit (bytes)>
-#
-# State TRACE plays back a pre-recorded trace once
-#
-# Addresses are expressed as decimal numbers. The period in the linear
-# and random state is from a uniform random distribution over the
-# interval. If a specific value is desired, then the min and max can
-# be set to the same value.
-STATE 0 1000000 LINEAR 50 0 256 4 5000 5000 64
-INIT 0
-TRANSITION 0 0 1
+env = env.Clone()
+
+objs = []
+objs += env.Object('cli_parser.cc')
+objs += env.Object('report_handler.cc')
+
+Return('objs')
diff --git a/util/tlm/examples/slave_port/run_gem5.sh b/util/tlm/examples/master_port/SConscript
index fd14689b9..b6caa8a77 100644
--- a/util/tlm/examples/slave_port/run_gem5.sh
+++ b/util/tlm/examples/master_port/SConscript
@@ -1,22 +1,23 @@
-#!/bin/bash
-# Copyright (c) 2015, University of Kaiserslautern
+#!python
+
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
 # All rights reserved.
-# 
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
 # met:
-# 
+#
 # 1. Redistributions of source code must retain the above copyright notice,
 #    this list of conditions and the following disclaimer.
-# 
+#
 # 2. Redistributions in binary form must reproduce the above copyright
 #    notice, this list of conditions and the following disclaimer in the
 #    documentation and/or other materials provided with the distribution.
-# 
+#
 # 3. Neither the name of the copyright holder nor the names of its
 #    contributors may be used to endorse or promote products derived from
 #    this software without specific prior written permission.
-# 
+#
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 # TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
@@ -28,26 +29,16 @@
 # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-# 
-# Authors: Matthias Jung
+#
+# Authors: Christian Menard
+
+Import('env')
+Import('deps')
 
-# Color Definition:
-RCol='\e[0m'; # Text Reset
-BGre='\e[1;31m';
-echo -e "\n${BGre}Create gem5 Configuration${RCol}\n"
+env = env.Clone()
 
-../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py \
---tlm-memory=transactor                                     \
---cpu-type=timing                                           \
---num-cpu=1                                                 \
---mem-type=SimpleMemory                                     \
---mem-size=512MB                                            \
---mem-channels=1                                            \
---caches --l2cache                                          \
---machine-type=VExpress_EMM                                 \
---dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
---kernel=vmlinux.aarch32.ll_20131205.0-gem5
+src = [File('main.cc'), File('traffic_generator.cc')]
 
-echo -e "\n${BGre}Run gem5 ${RCol}\n"
+bin = env.Program('gem5.sc', src + deps)
 
-time ./gem5.opt.sc m5out/config.ini -o 2147483648 
+Return('bin')
diff --git a/util/tlm/examples/master_port/SConstruct b/util/tlm/examples/master_port/SConstruct
deleted file mode 100644
index a896a34e4..000000000
--- a/util/tlm/examples/master_port/SConstruct
+++ /dev/null
@@ -1,78 +0,0 @@
-#!python
-
-# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-#    this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in the
-#    documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-#    contributors may be used to endorse or promote products derived from
-#    this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Christian Menard
-
-import os
-
-gem5_arch = 'ARM'
-gem5_variant = 'opt'
-#gem5_variant = 'debug'
-
-gem5_root = '#../../../..'
-
-target = 'gem5.' + gem5_variant + '.sc'
-
-env = Environment()
-
-# Import PKG_CONFIG_PATH from the external environment
-if os.environ.has_key('PKG_CONFIG_PATH'):
-    env['ENV']['PKG_CONFIG_PATH'] = os.environ['PKG_CONFIG_PATH']
-
-# search for SystemC
-env.ParseConfig('pkg-config --cflags --libs systemc')
-
-# add include dirs
-env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch,
-                    gem5_root + '/util/systemc',
-                    gem5_root + '/util/tlm',
-                    '../common'])
-
-env.Append(LIBS=['gem5_' + gem5_variant])
-env.Append(LIBPATH=[gem5_root + '/build/' + gem5_arch])
-
-env.Append(CXXFLAGS=['-std=c++11',
-                     '-DSC_INCLUDE_DYNAMIC_PROCESSES',
-                     '-DTRACING_ON'])
-
-if gem5_variant == 'debug':
-    env.Append(CXXFLAGS=['-g', '-DDEBUG'])
-
-src_systemc = [gem5_root + '/util/systemc/sc_gem5_control.cc',
-               gem5_root + '/util/systemc/sc_logger.cc',
-               gem5_root + '/util/systemc/sc_module.cc',
-               gem5_root + '/util/systemc/stats.cc']
-
-src_tlm     = Glob(gem5_root + '/util/tlm/*.cc')
-src_main    = Glob('*.cc') + Glob('../common/*.cc')
-
-main = env.Program(target, src_systemc + src_tlm + src_main)
diff --git a/util/tlm/examples/master_port/tlm.py b/util/tlm/examples/slave_port/SConscript
index 0b017a6d1..3c7d71d6b 100644
--- a/util/tlm/examples/master_port/tlm.py
+++ b/util/tlm/examples/slave_port/SConscript
@@ -1,4 +1,5 @@
-#
+#!python
+
 # Copyright (c) 2016, Dresden University of Technology (TU Dresden)
 # All rights reserved.
 #
@@ -30,46 +31,14 @@
 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Christian Menard
-#
 
-import m5
-from m5.objects import *
-
-import os
-
-# Base System Architecture:
-#         +-----+           ^
-#         | TLM |           | TLM World
-#         +--+--+           | (see main.cc)
-#            |              v
-# +----------v-----------+  External Port (see sc_master_port.*)
-# |        Membus        |  ^
-# +----------+-----------+  |
-#            |              | gem5 World
-#        +---v----+         |
-#        | Memory |         |
-#        +--------+         v
-#
+Import('env')
+Import('deps')
 
-# Create a system with a Crossbar and a simple Memory:
-system = System()
-system.membus = IOXBar(width = 16)
-system.physmem = SimpleMemory(range = AddrRange('512MB'))
-system.clk_domain = SrcClockDomain(clock = '1.5GHz',
-    voltage_domain = VoltageDomain(voltage = '1V'))
+env = env.Clone()
 
-# Create a external TLM port:
-system.tlm = ExternalMaster()
-system.tlm.port_type = "tlm_master"
-system.tlm.port_data = "transactor"
+src = [File('main.cc'), File('sc_target.cc')]
 
-# Route the connections:
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-system.tlm.port = system.membus.slave
-system.mem_mode = 'timing'
+bin = env.Program('gem5.sc', src + deps)
 
-# Start the simulation:
-root = Root(full_system = False, system = system)
-m5.instantiate()
-m5.simulate()
+Return('bin')
diff --git a/util/tlm/examples/slave_port/SConstruct b/util/tlm/examples/slave_port/SConstruct
deleted file mode 100644
index a896a34e4..000000000
--- a/util/tlm/examples/slave_port/SConstruct
+++ /dev/null
@@ -1,78 +0,0 @@
-#!python
-
-# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-#    this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in the
-#    documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-#    contributors may be used to endorse or promote products derived from
-#    this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Christian Menard
-
-import os
-
-gem5_arch = 'ARM'
-gem5_variant = 'opt'
-#gem5_variant = 'debug'
-
-gem5_root = '#../../../..'
-
-target = 'gem5.' + gem5_variant + '.sc'
-
-env = Environment()
-
-# Import PKG_CONFIG_PATH from the external environment
-if os.environ.has_key('PKG_CONFIG_PATH'):
-    env['ENV']['PKG_CONFIG_PATH'] = os.environ['PKG_CONFIG_PATH']
-
-# search for SystemC
-env.ParseConfig('pkg-config --cflags --libs systemc')
-
-# add include dirs
-env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch,
-                    gem5_root + '/util/systemc',
-                    gem5_root + '/util/tlm',
-                    '../common'])
-
-env.Append(LIBS=['gem5_' + gem5_variant])
-env.Append(LIBPATH=[gem5_root + '/build/' + gem5_arch])
-
-env.Append(CXXFLAGS=['-std=c++11',
-                     '-DSC_INCLUDE_DYNAMIC_PROCESSES',
-                     '-DTRACING_ON'])
-
-if gem5_variant == 'debug':
-    env.Append(CXXFLAGS=['-g', '-DDEBUG'])
-
-src_systemc = [gem5_root + '/util/systemc/sc_gem5_control.cc',
-               gem5_root + '/util/systemc/sc_logger.cc',
-               gem5_root + '/util/systemc/sc_module.cc',
-               gem5_root + '/util/systemc/stats.cc']
-
-src_tlm     = Glob(gem5_root + '/util/tlm/*.cc')
-src_main    = Glob('*.cc') + Glob('../common/*.cc')
-
-main = env.Program(target, src_systemc + src_tlm + src_main)
diff --git a/util/tlm/examples/slave_port/tlm.py b/util/tlm/examples/slave_port/tlm.py
deleted file mode 100644
index ed4db4047..000000000
--- a/util/tlm/examples/slave_port/tlm.py
+++ /dev/null
@@ -1,78 +0,0 @@
-# Copyright (c) 2015, University of Kaiserslautern
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-#    this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in the
-#    documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-#    contributors may be used to endorse or promote products derived from
-#    this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Matthias Jung
-
-import m5
-from m5.objects import *
-
-# This configuration shows a simple setup of a TrafficGen (CPU) and an
-# external TLM port for SystemC co-simulation
-#
-# Base System Architecture:
-# +-------------+  +-----+    ^
-# | System Port |  | CPU |    |
-# +-------+-----+  +--+--+    |
-#         |           |       | gem5 World
-#         |      +----+       | (see this file)
-#         |      |            |
-# +-------v------v-------+    |
-# |        Membus        |    v
-# +----------------+-----+    External Port (see sc_slave_port.*)
-#                  |          ^
-#              +---v---+      | TLM World
-#              |  TLM  |      | (see sc_target.*)
-#              +-------+      v
-#
-
-# Create a system with a Crossbar and a TrafficGenerator as CPU:
-system = System()
-system.membus = IOXBar(width = 16)
-system.physmem = SimpleMemory() # This must be instanciated, even if not needed
-system.cpu = TrafficGen(config_file = "tgen.cfg")
-system.clk_domain = SrcClockDomain(clock = '1.5GHz',
-    voltage_domain = VoltageDomain(voltage = '1V'))
-
-# Create a external TLM port:
-system.tlm = ExternalSlave()
-system.tlm.addr_ranges = [AddrRange('512MB')]
-system.tlm.port_type = "tlm_slave"
-system.tlm.port_data = "transactor"
-
-# Route the connections:
-system.cpu.port = system.membus.slave
-system.system_port = system.membus.slave
-system.membus.master = system.tlm.port
-
-# Start the simulation:
-root = Root(full_system = False, system = system)
-root.system.mem_mode = 'timing'
-m5.instantiate()
-m5.simulate() #Simulation time specified later on commandline
diff --git a/util/tlm/examples/slave_port/tlm_elastic.py b/util/tlm/examples/slave_port/tlm_elastic.py
deleted file mode 100644
index 8930e2e1b..000000000
--- a/util/tlm/examples/slave_port/tlm_elastic.py
+++ /dev/null
@@ -1,123 +0,0 @@
-# Copyright (c) 2016, University of Kaiserslautern
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-#    this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in the
-#    documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-#    contributors may be used to endorse or promote products derived from
-#    this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Matthias Jung
-
-import m5
-import optparse
-
-from m5.objects import *
-from m5.util import addToPath, fatal
-
-addToPath('../../../../configs/common/')
-
-from Caches import *
-
-# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
-# and an external TLM port for SystemC co-simulation.
-#
-# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
-#
-# Base System Architecture:
-#
-#                  +-----------+       ^
-# +-------------+  | eTraceCPU |       |
-# | System Port |  +-----+-----+       |
-# +------+------+  | $D1 | $I1 |       |
-#        |         +--+--+--+--+       |
-#        |            |     |          | gem5 World
-#        |            |     |          | (see this file)
-#        |            |     |          |
-# +------v------------v-----v--+       |
-# |           Membus           |       v
-# +----------------+-----------+       External Port (see sc_port.*)
-#                  |                   ^
-#              +---v---+               | TLM World
-#              |  TLM  |               | (see sc_target.*)
-#              +-------+               v
-#
-#
-# Create a system with a Crossbar and an Elastic Trace Player as CPU:
-
-# Setup System:
-system = System(cpu=TraceCPU(cpu_id=0),
-                mem_mode='timing',
-                mem_ranges = [AddrRange('512MB')],
-                cache_line_size = 64)
-
-# Create a top-level voltage domain:
-system.voltage_domain = VoltageDomain()
-
-# Create a source clock for the system. This is used as the clock period for
-# xbar and memory:
-system.clk_domain = SrcClockDomain(clock =  '1GHz',
-        voltage_domain = system.voltage_domain)
-
-# Create a CPU voltage domain:
-system.cpu_voltage_domain = VoltageDomain()
-
-# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
-# is actually used only by the caches connected to the CPU:
-system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
-        voltage_domain = system.cpu_voltage_domain)
-
-# Setup CPU and its L1 caches:
-system.cpu.createInterruptController()
-system.cpu.icache = L1_ICache(size="32kB")
-system.cpu.dcache = L1_DCache(size="32kB")
-system.cpu.icache.cpu_side = system.cpu.icache_port
-system.cpu.dcache.cpu_side = system.cpu.dcache_port
-
-# Assign input trace files to the eTraceCPU:
-system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
-system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
-
-# Setting up L1 BUS:
-system.membus = IOXBar(width = 16)
-system.physmem = SimpleMemory() # This must be instantiated, even if not needed
-
-# Create a external TLM port:
-system.tlm = ExternalSlave()
-system.tlm.addr_ranges = [AddrRange('512MB')]
-system.tlm.port_type = "tlm"
-system.tlm.port_data = "memory"
-
-# Connect everything:
-system.membus = SystemXBar()
-system.system_port = system.membus.slave
-system.cpu.icache.mem_side = system.membus.slave
-system.cpu.dcache.mem_side = system.membus.slave
-system.membus.master = system.tlm.port
-
-# Start the simulation:
-root = Root(full_system = False, system = system)
-root.system.mem_mode = 'timing'
-m5.instantiate()
-m5.simulate() #Simulation time specified later on commandline