misc: Clean up and complete the gem5<->SystemC-TLM bridge [7/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Implement 'pipe through' for gem5 Packets (see explanation below)

Basically, this patch ensures that all transactions that originated in the
gem5 world are converted back to the original packet when entering the gem5
world.  So far, this only worked for packets that are responded to by a
SyctemC component (e.g. when a gem5 CPU sends a request to a SystemC
memory). By implementing the 'pipe through' this patch ensures, that
packets that are responded to by a gem5 component (e.g. when a gem5 CPU
sends a request to a gem5 memory via a SystemC interconnect) are handled
properly.

Reviewed at http://reviews.gem5.org/r/3796/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/util/tlm/sc_master_port.hh b/util/tlm/sc_master_port.hh
index 5fae9b6b4..a1ab3a8f2 100644
--- a/util/tlm/sc_master_port.hh
+++ b/util/tlm/sc_master_port.hh
@@ -59,6 +59,13 @@ class Gem5MasterTransactor;
  * added as a sender state to the gem5 packet. This way the payload can be
  * restored when the response packet arrives at the port.
  *
+ * Special care is required, when the TLM transaction originates from a
+ * SCSlavePort (i.e. it is a gem5 packet that enters back into the gem5 world).
+ * This is a common scenario, when multiple gem5 CPUs communicate via a SystemC
+ * interconnect. In this case, the master port restores the original packet
+ * from the payload extension (added by the SCSlavePort) and forwards it to the
+ * gem5 world. Throughout the code, this mechanism is called 'pipe through'.
+ *
  * If gem5 operates in atomic mode, the master port registers the TLM blocking
  * interface and automatically translates non-blocking requests to blocking.
  * If gem5 operates in timing mode, the transactor registers the non-blocking
@@ -82,6 +89,7 @@ class SCMasterPort : public ExternalMaster::Port
 
     bool waitForRetry;
     tlm::tlm_generic_payload* pendingRequest;
+    PacketPtr pendingPacket;
 
     bool needToSendRetry;