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author | Christian Menard <Christian.Menard@tu-dresden.de> | 2017-02-09 19:15:41 -0500 |
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committer | Christian Menard <Christian.Menard@tu-dresden.de> | 2017-02-09 19:15:41 -0500 |
commit | 03f740664bc8db8890359c9c5ad02df9db478bae (patch) | |
tree | 27de717f997634ca22d04200a51b54305244929b /util/tlm/sim_control.hh | |
parent | ccd9210e1a1bdce828a13a4ffdf84548ffe61592 (diff) | |
download | gem5-03f740664bc8db8890359c9c5ad02df9db478bae.tar.xz |
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
Changeset 11798:3a490c57058d
---------------------------
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Introduce transactor modules that represent the gem5 ports in the
* SystemC world.
* Update the SimControl module and let it keep track of the gem5 ports.
Reviewed at http://reviews.gem5.org/r/3775/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'util/tlm/sim_control.hh')
-rw-r--r-- | util/tlm/sim_control.hh | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/util/tlm/sim_control.hh b/util/tlm/sim_control.hh index d210d76dd..b411022de 100644 --- a/util/tlm/sim_control.hh +++ b/util/tlm/sim_control.hh @@ -46,6 +46,7 @@ #include "sc_module.hh" #include "sim/cxx_manager.hh" #include "sim/system.hh" +#include "sim_control_if.hh" namespace Gem5SystemC { @@ -58,7 +59,7 @@ namespace Gem5SystemC * While it is mandatory to have one instance of this class for running a gem5 * simulation in SystemC, it is not allowed to have multiple instances! */ -class Gem5SimControl : public Gem5SystemC::Module +class Gem5SimControl : public Module, public Gem5SimControlInterface { protected: CxxConfigManager* config_manager; @@ -66,6 +67,13 @@ class Gem5SimControl : public Gem5SystemC::Module Tick simulationEnd; + /* + * Keep track of the slave and master ports that are created by gem5 + * according to the config file. + */ + std::map<const std::string, SCSlavePort*> slavePorts; + std::map<const std::string, SCMasterPort*> masterPorts; + /// Pointer to a previously created instance. static Gem5SimControl* instance; @@ -90,7 +98,12 @@ class Gem5SimControl : public Gem5SystemC::Module uint64_t simulationEnd, const std::string& gem5DebugFlags); - void before_end_of_elaboration(); + void registerSlavePort(const std::string& name, SCSlavePort* port); + void registerMasterPort(const std::string& name, SCMasterPort* port); + SCSlavePort* getSlavePort(const std::string& name) override; + SCMasterPort* getMasterPort(const std::string& name) override; + + void end_of_elaboration(); void run(); }; |