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author | Christian Menard <Christian.Menard@tu-dresden.de> | 2017-02-09 19:15:41 -0500 |
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committer | Christian Menard <Christian.Menard@tu-dresden.de> | 2017-02-09 19:15:41 -0500 |
commit | 03f740664bc8db8890359c9c5ad02df9db478bae (patch) | |
tree | 27de717f997634ca22d04200a51b54305244929b /util/tlm/sim_control_if.hh | |
parent | ccd9210e1a1bdce828a13a4ffdf84548ffe61592 (diff) | |
download | gem5-03f740664bc8db8890359c9c5ad02df9db478bae.tar.xz |
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
Changeset 11798:3a490c57058d
---------------------------
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Introduce transactor modules that represent the gem5 ports in the
* SystemC world.
* Update the SimControl module and let it keep track of the gem5 ports.
Reviewed at http://reviews.gem5.org/r/3775/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'util/tlm/sim_control_if.hh')
-rw-r--r-- | util/tlm/sim_control_if.hh | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/util/tlm/sim_control_if.hh b/util/tlm/sim_control_if.hh new file mode 100644 index 000000000..b65e919d2 --- /dev/null +++ b/util/tlm/sim_control_if.hh @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2017, Dresden University of Technology (TU Dresden) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Christian Menard + */ + +#ifndef __SC_SIM_CONTROL_IF_HH__ +#define __SC_SIM_CONTROL_IF_HH__ + +#include <systemc> + +namespace Gem5SystemC +{ + +// forward declerations +class SCSlavePort; +class SCMasterPort; + +class Gem5SimControlInterface : public sc_core::sc_interface +{ + public: + virtual SCSlavePort* getSlavePort(const std::string& name) = 0; + virtual SCMasterPort* getMasterPort(const std::string& name) = 0; +}; + +} + +#endif |