style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.

4 files changed, 15 insertions, 15 deletions

diff --git a/util/tlm/main.cc b/util/tlm/main.cc
index 8add0aeef..c06565603 100644
--- a/util/tlm/main.cc
+++ b/util/tlm/main.cc
@@ -249,7 +249,7 @@ SimControl::run()
 {
     GlobalSimLoopExitEvent *exit_event = NULL;
 
-    if(sim_end == 0) {
+    if (sim_end == 0) {
         exit_event = simulate();
     } else {
         exit_event = simulate(sim_end);
diff --git a/util/tlm/sc_mm.cc b/util/tlm/sc_mm.cc
index 509d429c2..2a169a37a 100644
--- a/util/tlm/sc_mm.cc
+++ b/util/tlm/sc_mm.cc
@@ -47,7 +47,7 @@ MemoryManager::MemoryManager(): numberOfAllocations(0), numberOfFrees(0)
 
 MemoryManager::~MemoryManager()
 {
-    for(gp* payload: freePayloads) {
+    for (gp* payload: freePayloads) {
         delete payload;
         numberOfFrees++;
     }
@@ -56,7 +56,7 @@ MemoryManager::~MemoryManager()
 gp*
 MemoryManager::allocate()
 {
-    if(freePayloads.empty()) {
+    if (freePayloads.empty()) {
         numberOfAllocations++;
         return new gp(this);
     } else {
diff --git a/util/tlm/sc_port.cc b/util/tlm/sc_port.cc
index 3f2798021..04efce87b 100644
--- a/util/tlm/sc_port.cc
+++ b/util/tlm/sc_port.cc
@@ -191,7 +191,7 @@ sc_transactor::recvTimingReq(PacketPtr packet)
     /*  NOTE: normal tlm is blocking here. But in our case we return false
      *  and tell gem5 when a retry can be done. This is the main difference
      *  in the protocol:
-     *  if(requestInProgress)
+     *  if (requestInProgress)
      *  {
      *      wait(endRequestEvent);
      *  }
@@ -214,11 +214,11 @@ sc_transactor::recvTimingReq(PacketPtr packet)
     tlm::tlm_sync_enum status;
     status = iSocket->nb_transport_fw(*trans, phase, delay);
     /* Check returned value: */
-    if(status == tlm::TLM_ACCEPTED) {
+    if (status == tlm::TLM_ACCEPTED) {
         sc_assert(phase == tlm::BEGIN_REQ);
         /* Accepted but is now blocking until END_REQ (exclusion rule)*/
         blockingRequest = trans;
-    } else if(status == tlm::TLM_UPDATED) {
+    } else if (status == tlm::TLM_UPDATED) {
         /* The Timing annotation must be honored: */
         sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP);
 
@@ -226,7 +226,7 @@ sc_transactor::recvTimingReq(PacketPtr packet)
         pe = new payloadEvent<sc_transactor>(*this,
             &sc_transactor::pec, "PEQ");
         pe->notify(*trans, phase, delay);
-    } else if(status == tlm::TLM_COMPLETED) {
+    } else if (status == tlm::TLM_COMPLETED) {
         /* Transaction is over nothing has do be done. */
         sc_assert(phase == tlm::END_RESP);
         trans->release();
@@ -243,7 +243,7 @@ sc_transactor::pec(
 {
     sc_time delay;
 
-    if(phase == tlm::END_REQ ||
+    if (phase == tlm::END_REQ ||
             &trans == blockingRequest && phase == tlm::BEGIN_RESP) {
         sc_assert(&trans == blockingRequest);
         blockingRequest = NULL;
@@ -254,7 +254,7 @@ sc_transactor::pec(
            iSocket.sendRetryReq();
         }
     }
-    else if(phase == tlm::BEGIN_RESP)
+    else if (phase == tlm::BEGIN_RESP)
     {
         CAUGHT_UP;
 
diff --git a/util/tlm/sc_target.cc b/util/tlm/sc_target.cc
index 69025b387..bae1de126 100644
--- a/util/tlm/sc_target.cc
+++ b/util/tlm/sc_target.cc
@@ -84,12 +84,12 @@ Target::transport_dbg(tlm::tlm_generic_payload& trans)
 
     /* Load / Store the access: */
     if ( cmd == tlm::TLM_READ_COMMAND ) {
-        if(debug) {
+        if (debug) {
             SC_REPORT_INFO("target", "tlm::TLM_READ_COMMAND");
         }
         std::memcpy(ptr, mem_array_ptr, len);
     } else if ( cmd == tlm::TLM_WRITE_COMMAND ) {
-        if(debug) {
+        if (debug) {
             SC_REPORT_INFO("target", "tlm::TLM_WRITE_COMMAND");
         }
         std::memcpy(mem_array_ptr, ptr, len);
@@ -115,8 +115,8 @@ Target::peq_cb(tlm::tlm_generic_payload& trans,
 {
     sc_time delay;
 
-    if(phase == tlm::BEGIN_REQ) {
-        if(debug) SC_REPORT_INFO("target", "tlm::BEGIN_REQ");
+    if (phase == tlm::BEGIN_REQ) {
+        if (debug) SC_REPORT_INFO("target", "tlm::BEGIN_REQ");
 
         /* Increment the transaction reference count */
         trans.acquire();
@@ -226,12 +226,12 @@ Target::execute_transaction(tlm::tlm_generic_payload& trans)
 
     /* Load / Store the access: */
     if ( cmd == tlm::TLM_READ_COMMAND ) {
-        if(debug) {
+        if (debug) {
             SC_REPORT_INFO("target", "tlm::TLM_READ_COMMAND");
         }
         std::memcpy(ptr, mem_array_ptr, len);
     } else if ( cmd == tlm::TLM_WRITE_COMMAND ) {
-        if(debug) {
+        if (debug) {
             SC_REPORT_INFO("target", "tlm::TLM_WRITE_COMMAND");
         }
         std::memcpy(mem_array_ptr, ptr, len);