arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli    (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt       (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole           (AArch64 NEON, validation)
Ali Saidi            (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang         (AArch64 Linux support)
Rene De Jong         (AArch64 Linux support, performance opt.)
Matt Horsnell        (AArch64 MP, validation)
Matt Evans           (device models, code integration, validation)
Chris Adeniyi-Jones  (AArch64 syscall-emulation)
Prakash Ramrakhyani  (validation)
Dam Sunwoo           (validation)
Chander Sudanthi     (validation)
Stephan Diestelhorst (validation)
Andreas Hansson      (code integration, performance opt.)
Eric Van Hensbergen  (performance opt.)
Gabe Black

2 files changed, 469 insertions, 3 deletions

diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index e6ee7d562..fac9e07a7 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -225,9 +225,325 @@ def from_7(cpt):
             # Search for all ISA sections
             if re.search('.*sys.*\.cpu.*\.isa', sec):
                 mr = cpt.get(sec, 'miscRegs').split()
-                # Add dummy value for MISCREG_TEEHBR
-                mr.insert(51,0);
-                cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
+                if len(mr) == 161:
+                    print "MISCREG_TEEHBR already seems to be inserted."
+                else:
+                    # Add dummy value for MISCREG_TEEHBR
+                    mr.insert(51,0);
+                    cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
+
+# Version 9 of the checkpoint adds an all ARMv8 state
+def from_8(cpt):
+    if cpt.get('root','isa') != 'arm':
+        return
+    import re
+    print "Warning: The size of the FP register file has changed. "\
+          "To get similar results you need to adjust the number of "\
+          "physical registers in the CPU you're restoring into by "\
+          "NNNN."
+    # Find the CPU context's and upgrade their registers
+    for sec in cpt.sections():
+        re_xc_match = re.match('^.*?sys.*?\.cpu(\d+)*\.xc\.*', sec)
+        if not re_xc_match:
+            continue
+
+        # Update floating point regs
+        fpr = cpt.get(sec, 'floatRegs.i').split()
+        # v8 has 128 normal fp and 32 special fp regs compared
+        # to v7's 64 normal fp and 8 special fp regs.
+        # Insert the extra normal fp registers at end of v7 normal fp regs
+        for x in xrange(64):
+            fpr.insert(64, "0")
+        # Append the extra special registers
+        for x in xrange(24):
+            fpr.append("0")
+        cpt.set(sec, 'floatRegs.i', ' '.join(str(x) for x in fpr))
+
+        ir = cpt.get(sec, 'intRegs').split()
+        # Add in v8 int reg state
+        # Splice in R13_HYP
+        ir.insert(20, "0")
+        # Splice in INTREG_DUMMY and SP0 - SP3
+        ir.extend(["0", "0", "0", "0", "0"])
+        cpt.set(sec, 'intRegs', ' '.join(str(x) for x in ir))
+
+    # Update the cpu interrupt field
+    for sec in cpt.sections():
+        re_int_match = re.match("^.*?sys.*?\.cpu(\d+)*$", sec)
+        if not re_int_match:
+            continue
+
+        irqs = cpt.get(sec, "interrupts").split()
+        irqs.append("false")
+        irqs.append("false")
+        cpt.set(sec, "interrupts", ' '.join(str(x) for x in irqs))
+
+    # Update the per cpu interrupt structure
+    for sec in cpt.sections():
+        re_int_match = re.match("^.*?sys.*?\.cpu(\d+)*\.interrupts$", sec)
+        if not re_int_match:
+            continue
+
+        irqs = cpt.get(sec, "interrupts").split()
+        irqs.append("false")
+        irqs.append("false")
+        cpt.set(sec, "interrupts", ' '.join(str(x) for x in irqs))
+
+    # Update the misc regs and add in new isa specific fields
+    for sec in cpt.sections():
+        re_isa_match = re.match("^.*?sys.*?\.cpu(\d+)*\.isa$", sec)
+        if not re_isa_match:
+            continue
+
+        cpt.set(sec, 'haveSecurity', 'false')
+        cpt.set(sec, 'haveLPAE', 'false')
+        cpt.set(sec, 'haveVirtualization', 'false')
+        cpt.set(sec, 'haveLargeAsid64', 'false')
+        cpt.set(sec, 'physAddrRange64', '40')
+
+        # splice in the new misc registers, ~200 -> 605 registers,
+        # ordering does not remain consistent
+        mr_old = cpt.get(sec, 'miscRegs').split()
+        mr_new = [ '0' for x in xrange(605) ]
+
+        # map old v7 miscRegs to new v8 miscRegs
+        mr_new[0] = mr_old[0] # CPSR
+        mr_new[16] = mr_old[1] # CPSR_Q
+        mr_new[1] = mr_old[2] # SPSR
+        mr_new[2] = mr_old[3] # SPSR_FIQ
+        mr_new[3] = mr_old[4] # SPSR_IRQ
+        mr_new[4] = mr_old[5] # SPSR_SVC
+        mr_new[5] = mr_old[6] # SPSR_MON
+        mr_new[8] = mr_old[7] # SPSR_UND
+        mr_new[6] = mr_old[8] # SPSR_ABT
+        mr_new[432] = mr_old[9] # FPSR
+        mr_new[10] = mr_old[10] # FPSID
+        mr_new[11] = mr_old[11] # FPSCR
+        mr_new[18] = mr_old[12] # FPSCR_QC
+        mr_new[17] = mr_old[13] # FPSCR_EXC
+        mr_new[14] = mr_old[14] # FPEXC
+        mr_new[13] = mr_old[15] # MVFR0
+        mr_new[12] = mr_old[16] # MVFR1
+        mr_new[28] = mr_old[17] # SCTLR_RST,
+        mr_new[29] = mr_old[18] # SEV_MAILBOX,
+        mr_new[30] = mr_old[19] # DBGDIDR
+        mr_new[31] = mr_old[20] # DBGDSCR_INT,
+        mr_new[33] = mr_old[21] # DBGDTRRX_INT,
+        mr_new[34] = mr_old[22] # DBGTRTX_INT,
+        mr_new[35] = mr_old[23] # DBGWFAR,
+        mr_new[36] = mr_old[24] # DBGVCR,
+        #mr_new[] = mr_old[25] # DBGECR -> UNUSED,
+        #mr_new[] = mr_old[26] # DBGDSCCR -> UNUSED,
+        #mr_new[] = mr_old[27] # DBGSMCR -> UNUSED,
+        mr_new[37] = mr_old[28] # DBGDTRRX_EXT,
+        mr_new[38] = mr_old[29] # DBGDSCR_EXT,
+        mr_new[39] = mr_old[30] # DBGDTRTX_EXT,
+        #mr_new[] = mr_old[31] # DBGDRCR -> UNUSED,
+        mr_new[41] = mr_old[32] # DBGBVR,
+        mr_new[47] = mr_old[33] # DBGBCR,
+        #mr_new[] = mr_old[34] # DBGBVR_M -> UNUSED,
+        #mr_new[] = mr_old[35] # DBGBCR_M -> UNUSED,
+        mr_new[61] = mr_old[36] # DBGDRAR,
+        #mr_new[] = mr_old[37] # DBGBXVR_M -> UNUSED,
+        mr_new[64] = mr_old[38] # DBGOSLAR,
+        #mr_new[] = mr_old[39] # DBGOSSRR -> UNUSED,
+        mr_new[66] = mr_old[40] # DBGOSDLR,
+        mr_new[67] = mr_old[41] # DBGPRCR,
+        #mr_new[] = mr_old[42] # DBGPRSR -> UNUSED,
+        mr_new[68] = mr_old[43] # DBGDSAR,
+        #mr_new[] = mr_old[44] # DBGITCTRL -> UNUSED,
+        mr_new[69] = mr_old[45] # DBGCLAIMSET,
+        mr_new[70] = mr_old[46] # DBGCLAIMCLR,
+        mr_new[71] = mr_old[47] # DBGAUTHSTATUS,
+        mr_new[72] = mr_old[48] # DBGDEVID2,
+        mr_new[73] = mr_old[49] # DBGDEVID1,
+        mr_new[74] = mr_old[50] # DBGDEVID,
+        mr_new[77] = mr_old[51] # TEEHBR,
+        mr_new[109] = mr_old[52] # v7 SCTLR -> aarc32 SCTLR_NS
+        mr_new[189] = mr_old[53] # DCCISW,
+        mr_new[188] = mr_old[54] # DCCIMVAC,
+        mr_new[183] = mr_old[55] # DCCMVAC,
+        mr_new[271] = mr_old[56] # v7 CONTEXTIDR -> aarch32 CONTEXTIDR_NS,
+        mr_new[274] = mr_old[57] # v7 TPIDRURW -> aarch32 TPIDRURW_NS,
+        mr_new[277] = mr_old[58] # v7 TPIDRURO -> aarch32 TPIDRURO_NS,
+        mr_new[280] = mr_old[59] # v7 TPIDRPRW -> aarch32 TPIDRPRW_NS,
+        mr_new[170] = mr_old[60] # CP15ISB,
+        mr_new[185] = mr_old[61] # CP15DSB,
+        mr_new[186] = mr_old[62] # CP15DMB,
+        mr_new[114] = mr_old[63] # CPACR,
+        mr_new[101] = mr_old[64] # CLIDR,
+        mr_new[100] = mr_old[65] # CCSIDR,
+        mr_new[104] = mr_old[66] # v7 CSSELR -> aarch32 CSSELR_NS,
+        mr_new[163] = mr_old[67] # ICIALLUIS,
+        mr_new[168] = mr_old[68] # ICIALLU,
+        mr_new[169] = mr_old[69] # ICIMVAU,
+        mr_new[172] = mr_old[70] # BPIMVA,
+        mr_new[164] = mr_old[71] # BPIALLIS,
+        mr_new[171] = mr_old[72] # BPIALL,
+        mr_new[80] = mr_old[73] # MIDR,
+        mr_new[126] = mr_old[74] # v7 TTBR0 -> aarch32 TTBR0_NS,
+        mr_new[129] = mr_old[75] # v7 TTBR1 -> aarch32 TTBR1_NS,
+        mr_new[83] = mr_old[76] # TLBTR,
+        mr_new[137] = mr_old[77] # v7 DACR -> aarch32 DACR_NS,
+        mr_new[192] = mr_old[78] # TLBIALLIS,
+        mr_new[193] = mr_old[79] # TLBIMVAIS,
+        mr_new[194] = mr_old[80] # TLBIASIDIS,
+        mr_new[195] = mr_old[81] # TLBIMVAAIS,
+        mr_new[198] = mr_old[82] # ITLBIALL,
+        mr_new[199] = mr_old[83] # ITLBIMVA,
+        mr_new[200] = mr_old[84] # ITLBIASID,
+        mr_new[201] = mr_old[85] # DTLBIALL,
+        mr_new[202] = mr_old[86] # DTLBIMVA,
+        mr_new[203] = mr_old[87] # DTLBIASID,
+        mr_new[204] = mr_old[88] # TLBIALL,
+        mr_new[205] = mr_old[89] # TLBIMVA,
+        mr_new[206] = mr_old[90] # TLBIASID,
+        mr_new[207] = mr_old[91] # TLBIMVAA,
+        mr_new[140] = mr_old[92] # v7 DFSR -> aarch32 DFSR_NS,
+        mr_new[143] = mr_old[93] # v7 IFSR -> aarch32 IFSR_NS,
+        mr_new[155] = mr_old[94] # v7 DFAR -> aarch32 DFAR_NS,
+        mr_new[158] = mr_old[95] # v7 IFAR -> aarch32 IFAR_NS,
+        mr_new[84] = mr_old[96] # MPIDR,
+        mr_new[241] = mr_old[97] # v7 PRRR -> aarch32 PRRR_NS,
+        mr_new[247] = mr_old[98] # v7 NMRR -> aarch32 NMRR_NS,
+        mr_new[131] = mr_old[99] # TTBCR,
+        mr_new[86] = mr_old[100] # ID_PFR0,
+        mr_new[81] = mr_old[101] # CTR,
+        mr_new[115] = mr_old[102] # SCR,
+        # Set the non-secure bit
+        scr = int(mr_new[115])
+        scr = scr | 0x1
+        mr_new[115] = str(scr)
+        ###
+        mr_new[116] = mr_old[103] # SDER,
+        mr_new[165] = mr_old[104] # PAR,
+        mr_new[175] = mr_old[105] # V2PCWPR -> ATS1CPR,
+        mr_new[176] = mr_old[106] # V2PCWPW -> ATS1CPW,
+        mr_new[177] = mr_old[107] # V2PCWUR -> ATS1CUR,
+        mr_new[178] = mr_old[108] # V2PCWUW -> ATS1CUW,
+        mr_new[179] = mr_old[109] # V2POWPR -> ATS12NSOPR,
+        mr_new[180] = mr_old[110] # V2POWPW -> ATS12NSOPW,
+        mr_new[181] = mr_old[111] # V2POWUR -> ATS12NSOUR,
+        mr_new[182] = mr_old[112] # V2POWUW -> ATS12NWOUW,
+        mr_new[90] = mr_old[113] # ID_MMFR0,
+        mr_new[92] = mr_old[114] # ID_MMFR2,
+        mr_new[93] = mr_old[115] # ID_MMFR3,
+        mr_new[112] = mr_old[116] # v7 ACTLR -> aarch32 ACTLR_NS
+        mr_new[222] = mr_old[117] # PMCR,
+        mr_new[230] = mr_old[118] # PMCCNTR,
+        mr_new[223] = mr_old[119] # PMCNTENSET,
+        mr_new[224] = mr_old[120] # PMCNTENCLR,
+        mr_new[225] = mr_old[121] # PMOVSR,
+        mr_new[226] = mr_old[122] # PMSWINC,
+        mr_new[227] = mr_old[123] # PMSELR,
+        mr_new[228] = mr_old[124] # PMCEID0,
+        mr_new[229] = mr_old[125] # PMCEID1,
+        mr_new[231] = mr_old[126] # PMXEVTYPER,
+        mr_new[233] = mr_old[127] # PMXEVCNTR,
+        mr_new[234] = mr_old[128] # PMUSERENR,
+        mr_new[235] = mr_old[129] # PMINTENSET,
+        mr_new[236] = mr_old[130] # PMINTENCLR,
+        mr_new[94] = mr_old[131] # ID_ISAR0,
+        mr_new[95] = mr_old[132] # ID_ISAR1,
+        mr_new[96] = mr_old[133] # ID_ISAR2,
+        mr_new[97] = mr_old[134] # ID_ISAR3,
+        mr_new[98] = mr_old[135] # ID_ISAR4,
+        mr_new[99] = mr_old[136] # ID_ISAR5,
+        mr_new[20] = mr_old[137] # LOCKFLAG,
+        mr_new[19] = mr_old[138] # LOCKADDR,
+        mr_new[87] = mr_old[139] # ID_PFR1,
+        # Set up the processor features register
+        pfr = int(mr_new[87])
+        pfr = pfr | 0x1011
+        mr_new[87] = str(pfr)
+        ###
+        mr_new[238] = mr_old[140] # L2CTLR,
+        mr_new[82] = mr_old[141] # TCMTR
+        mr_new[88] = mr_old[142] # ID_DFR0,
+        mr_new[89] = mr_old[143] # ID_AFR0,
+        mr_new[91] = mr_old[144] # ID_MMFR1,
+        mr_new[102] = mr_old[145] # AIDR,
+        mr_new[146] = mr_old[146] # v7 ADFSR -> aarch32 ADFSR_NS,
+        mr_new[148] = mr_old[147] # AIFSR,
+        mr_new[173] = mr_old[148] # DCIMVAC,
+        mr_new[174] = mr_old[149] # DCISW,
+        mr_new[184] = mr_old[150] # MCCSW -> DCCSW,
+        mr_new[187] = mr_old[151] # DCCMVAU,
+        mr_new[117] = mr_old[152] # NSACR,
+        mr_new[262] = mr_old[153] # VBAR,
+        mr_new[265] = mr_old[154] # MVBAR,
+        mr_new[267] = mr_old[155] # ISR,
+        mr_new[269] = mr_old[156] # FCEIDR -> FCSEIDR,
+        #mr_new[] = mr_old[157] # L2LATENCY -> UNUSED,
+        #mr_new[] = mr_old[158] # CRN15 -> UNUSED,
+        mr_new[599] = mr_old[159] # NOP
+        mr_new[600] = mr_old[160] # RAZ,
+
+        # Set the new miscRegs structure
+        cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr_new))
+
+    cpu_prefix = {}
+    # Add in state for ITB/DTB
+    for sec in cpt.sections():
+        re_tlb_match = re.match('(^.*?sys.*?\.cpu(\d+)*)\.(dtb|itb)$', sec)
+        if not re_tlb_match:
+            continue
+
+        cpu_prefix[re_tlb_match.group(1)] = True # Save off prefix to add
+        # Set the non-secure bit (bit 9) to 1 for attributes
+        attr = int(cpt.get(sec, '_attr'))
+        attr = attr | 0x200
+        cpt.set(sec, '_attr', str(attr))
+        cpt.set(sec, 'haveLPAE', 'false')
+        cpt.set(sec, 'directToStage2', 'false')
+        cpt.set(sec, 'stage2Req', 'false')
+        cpt.set(sec, 'bootUncacheability', 'true')
+
+    # Add in extra state for the new TLB Entries
+    for sec in cpt.sections():
+        re_tlbentry_match = re.match('(^.*?sys.*?\.cpu(\d+)*)\.(dtb|itb).TlbEntry\d+$', sec)
+        if not re_tlbentry_match:
+            continue
+
+        # Add in the new entries
+        cpt.set(sec, 'longDescFormat', 'false')
+        cpt.set(sec, 'vmid', '0')
+        cpt.set(sec, 'isHyp', 'false')
+        valid = cpt.get(sec, 'valid')
+        if valid == 'true':
+            cpt.set(sec, 'ns', 'true')
+            cpt.set(sec, 'nstid', 'true')
+            cpt.set(sec, 'pxn', 'true')
+            cpt.set(sec, 'hap', '3')
+            # All v7 code used 2 level page tables
+            cpt.set(sec, 'lookupLevel', '2')
+            attr = int(cpt.get(sec, 'attributes'))
+            # set the non-secure bit (bit 9) to 1
+            # as no previous v7 code used secure code
+            attr = attr | 0x200
+            cpt.set(sec, 'attributes', str(attr))
+        else:
+            cpt.set(sec, 'ns', 'false')
+            cpt.set(sec, 'nstid', 'false')
+            cpt.set(sec, 'pxn', 'false')
+            cpt.set(sec, 'hap', '0')
+            cpt.set(sec, 'lookupLevel', '0')
+        cpt.set(sec, 'outerShareable', 'false')
+
+    # Add d/istage2_mmu and d/istage2_mmu.stage2_tlb
+    for key in cpu_prefix:
+        for suffix in ['.istage2_mmu', '.dstage2_mmu']:
+            new_sec = key + suffix
+            cpt.add_section(new_sec)
+            new_sec = key + suffix + ".stage2_tlb"
+            cpt.add_section(new_sec)
+            # Fill in tlb info with some defaults
+            cpt.set(new_sec, '_attr', '0')
+            cpt.set(new_sec, 'haveLPAE', 'false')
+            cpt.set(new_sec, 'directToStage2', 'false')
+            cpt.set(new_sec, 'stage2Req', 'false')
+            cpt.set(new_sec, 'bootUncacheability', 'false')
+            cpt.set(new_sec, 'num_entries', '0')
 
 
 migrations = []
@@ -239,6 +555,7 @@ migrations.append(from_4)
 migrations.append(from_5)
 migrations.append(from_6)
 migrations.append(from_7)
+migrations.append(from_8)
 
 verbose_print = False
 
diff --git a/util/m5/m5op_arm_A64.S b/util/m5/m5op_arm_A64.S
new file mode 100644
index 000000000..a422a3050
--- /dev/null
+++ b/util/m5/m5op_arm_A64.S
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2010-2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Ali Saidi
+ *          Chander Sudanthi
+ */
+
+#define m5_op 0xFF
+
+#include "m5ops.h"
+
+#define INST(op, ra, rb, func) \
+        .long (((op) << 24) | ((func) << 16) | ((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb))
+/*               m5ops           m5func             ra         coproc 1       op=1       rb   */
+
+#define LEAF(func)    \
+        .globl  func; \
+func:
+
+#define RET           \
+        RET
+
+#define END(func)     \
+
+#define SIMPLE_OP(_f, _o)       \
+        LEAF(_f)                \
+                _o;             \
+                RET;            \
+        END(_f)
+
+#define ARM INST(m5_op, 0, 0, arm_func)
+#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
+#define QUIESCENS INST(m5_op, 0, 0, quiescens_func)
+#define QUIESCECYC INST(m5_op, 0, 0, quiescecycle_func)
+#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
+#define RPNS INST(m5_op, 0, 0, rpns_func)
+#define WAKE_CPU INST(m5_op, 0, 0, wakecpu_func)
+#define M5EXIT INST(m5_op, 0, 0, exit_func)
+#define INITPARAM INST(m5_op, 0, 0, initparam_func)
+#define LOADSYMBOL INST(m5_op, 0, 0, loadsymbol_func)
+#define RESET_STATS INST(m5_op, 0, 0, resetstats_func)
+#define DUMP_STATS INST(m5_op, 0, 0, dumpstats_func)
+#define DUMPRST_STATS INST(m5_op, 0, 0, dumprststats_func)
+#define CHECKPOINT INST(m5_op, 0, 0, ckpt_func)
+#define READFILE INST(m5_op, 0, 0, readfile_func)
+#define WRITEFILE INST(m5_op, 0, 0, writefile_func)
+#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
+#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
+#define ADDSYMBOL INST(m5_op, 0, 0, addsymbol_func)
+#define PANIC INST(m5_op, 0, 0, panic_func)
+#define WORK_BEGIN INST(m5_op, 0, 0, work_begin_func)
+#define WORK_END INST(m5_op, 0, 0, work_end_func)
+
+#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func)
+#define AN_ESM INST(m5_op, an_esm, 0, annotate_func)
+#define AN_BEGIN INST(m5_op, an_begin, 0, annotate_func)
+#define AN_END INST(m5_op, an_end, 0, annotate_func)
+#define AN_Q INST(m5_op, an_q, 0, annotate_func)
+#define AN_RQ INST(m5_op, an_rq, 0, annotate_func)
+#define AN_DQ INST(m5_op, an_dq, 0, annotate_func)
+#define AN_WF INST(m5_op, an_wf, 0, annotate_func)
+#define AN_WE INST(m5_op, an_we, 0, annotate_func)
+#define AN_WS INST(m5_op, an_ws, 0, annotate_func)
+#define AN_SQ INST(m5_op, an_sq, 0, annotate_func)
+#define AN_AQ INST(m5_op, an_aq, 0, annotate_func)
+#define AN_PQ INST(m5_op, an_pq, 0, annotate_func)
+#define AN_L INST(m5_op, an_l, 0, annotate_func)
+#define AN_IDENTIFY INST(m5_op, an_identify, 0, annotate_func)
+#define AN_GETID INST(m5_op, an_getid, 0, annotate_func)
+
+.text
+
+SIMPLE_OP(arm, ARM)
+SIMPLE_OP(quiesce, QUIESCE)
+SIMPLE_OP(quiesceNs, QUIESCENS)
+SIMPLE_OP(quiesceCycle, QUIESCECYC)
+SIMPLE_OP(quiesceTime, QUIESCETIME)
+SIMPLE_OP(rpns, RPNS)
+SIMPLE_OP(wakeCPU, WAKE_CPU)
+SIMPLE_OP(m5_exit, M5EXIT)
+SIMPLE_OP(m5_initparam, INITPARAM)
+SIMPLE_OP(m5_loadsymbol, LOADSYMBOL)
+SIMPLE_OP(m5_reset_stats, RESET_STATS)
+SIMPLE_OP(m5_dump_stats, DUMP_STATS)
+SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS)
+SIMPLE_OP(m5_checkpoint, CHECKPOINT)
+SIMPLE_OP(m5_readfile, READFILE)
+SIMPLE_OP(m5_writefile, WRITEFILE)
+SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
+SIMPLE_OP(m5_switchcpu, SWITCHCPU)
+SIMPLE_OP(m5_addsymbol, ADDSYMBOL)
+SIMPLE_OP(m5_panic, PANIC)
+SIMPLE_OP(m5_work_begin, WORK_BEGIN)
+SIMPLE_OP(m5_work_end, WORK_END)
+
+SIMPLE_OP(m5a_bsm, AN_BSM)
+SIMPLE_OP(m5a_esm, AN_ESM)
+SIMPLE_OP(m5a_begin, AN_BEGIN)
+SIMPLE_OP(m5a_end, AN_END)
+SIMPLE_OP(m5a_q, AN_Q)
+SIMPLE_OP(m5a_rq, AN_RQ)
+SIMPLE_OP(m5a_dq, AN_DQ)
+SIMPLE_OP(m5a_wf, AN_WF)
+SIMPLE_OP(m5a_we, AN_WE)
+SIMPLE_OP(m5a_ws, AN_WS)
+SIMPLE_OP(m5a_sq, AN_SQ)
+SIMPLE_OP(m5a_aq, AN_AQ)
+SIMPLE_OP(m5a_pq, AN_PQ)
+SIMPLE_OP(m5a_l, AN_L)
+SIMPLE_OP(m5a_identify, AN_IDENTIFY)
+SIMPLE_OP(m5a_getid, AN_GETID)
+