diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:19 -0800 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:19 -0800 |
commit | 5592798865ece858bab2b444bc782d19121e2566 (patch) | |
tree | 80803048c903c424ed9f1200b5dc1a29ed3ff6b8 /util | |
parent | dc8018a5c3482008232e6faaa2d96cf20aed7485 (diff) | |
download | gem5-5592798865ece858bab2b444bc782d19121e2566.tar.xz |
style: fix missing spaces in control statements
Result of running 'hg m5style --skip-all --fix-control -a'.
Diffstat (limited to 'util')
-rw-r--r-- | util/statetrace/arch/amd64/tracechild.cc | 10 | ||||
-rw-r--r-- | util/statetrace/arch/arm/tracechild.cc | 12 | ||||
-rw-r--r-- | util/statetrace/arch/sparc/tracechild.cc | 6 | ||||
-rw-r--r-- | util/tlm/main.cc | 2 | ||||
-rw-r--r-- | util/tlm/sc_mm.cc | 4 | ||||
-rw-r--r-- | util/tlm/sc_port.cc | 12 | ||||
-rw-r--r-- | util/tlm/sc_target.cc | 12 |
7 files changed, 29 insertions, 29 deletions
diff --git a/util/statetrace/arch/amd64/tracechild.cc b/util/statetrace/arch/amd64/tracechild.cc index 1aec5ec97..d3f3886d1 100644 --- a/util/statetrace/arch/amd64/tracechild.cc +++ b/util/statetrace/arch/amd64/tracechild.cc @@ -271,7 +271,7 @@ AMD64TraceChild::outputStartState(ostream & os) highestInfo = cargv; os << obuf; sp += 8; - } while(cargv); + } while (cargv); //Output the envp pointers int envCount = 0; @@ -282,7 +282,7 @@ AMD64TraceChild::outputStartState(ostream & os) sp, envCount++, cenvp); os << obuf; sp += 8; - } while(cenvp); + } while (cenvp); uint64_t auxType, auxVal; do { auxType = ptrace(PTRACE_PEEKDATA, pid, sp, 0); @@ -292,7 +292,7 @@ AMD64TraceChild::outputStartState(ostream & os) sprintf(obuf, "0x%016lx: Auxiliary vector = {0x%016lx, 0x%016lx}\n", sp - 16, auxType, auxVal); os << obuf; - } while(auxType != 0 || auxVal != 0); + } while (auxType != 0 || auxVal != 0); //Print out the argument strings, environment strings, and file name. string current; uint64_t buf; @@ -329,7 +329,7 @@ AMD64TraceChild::findSyscall() for (int i = 0; i < sizeof(uint64_t); i++) { unsigned char byte = buf & 0xFF; if (!foundOpcode) { - if(!(byte == 0x66 || //operand override + if (!(byte == 0x66 || //operand override byte == 0x67 || //address override byte == 0x2E || //cs byte == 0x3E || //ds @@ -395,7 +395,7 @@ AMD64TraceChild::step() do { ptraceSingleStep(); newPC = getPC(); - } while(newPC == origPC); + } while (newPC == origPC); } } diff --git a/util/statetrace/arch/arm/tracechild.cc b/util/statetrace/arch/arm/tracechild.cc index 79670bc8b..d331a851e 100644 --- a/util/statetrace/arch/arm/tracechild.cc +++ b/util/statetrace/arch/arm/tracechild.cc @@ -183,12 +183,12 @@ ARMTraceChild::outputStartState(ostream & os) cargv = ptrace(PTRACE_PEEKDATA, pid, sp, 0); sprintf(obuf, "0x%08x: argv[%d] = 0x%08x\n", sp, argCount++, cargv); - if(cargv) - if(highestInfo < cargv) + if (cargv) + if (highestInfo < cargv) highestInfo = cargv; os << obuf; sp += 4; - } while(cargv); + } while (cargv); //Output the envp pointers int envCount = 0; @@ -199,7 +199,7 @@ ARMTraceChild::outputStartState(ostream & os) sp, envCount++, cenvp); os << obuf; sp += 4; - } while(cenvp); + } while (cenvp); uint32_t auxType, auxVal; do { auxType = ptrace(PTRACE_PEEKDATA, pid, sp, 0); @@ -209,7 +209,7 @@ ARMTraceChild::outputStartState(ostream & os) sprintf(obuf, "0x%08x: Auxiliary vector = {0x%08x, 0x%08x}\n", sp - 8, auxType, auxVal); os << obuf; - } while(auxType != 0 || auxVal != 0); + } while (auxType != 0 || auxVal != 0); //Print out the argument strings, environment strings, and file name. string current; uint32_t buf; @@ -231,7 +231,7 @@ ARMTraceChild::outputStartState(ostream & os) } sp += 4; clearedInitialPadding = clearedInitialPadding || buf != 0; - } while(!clearedInitialPadding || buf != 0 || sp <= highestInfo); + } while (!clearedInitialPadding || buf != 0 || sp <= highestInfo); return os; } diff --git a/util/statetrace/arch/sparc/tracechild.cc b/util/statetrace/arch/sparc/tracechild.cc index fad4a00d7..dc6017a9f 100644 --- a/util/statetrace/arch/sparc/tracechild.cc +++ b/util/statetrace/arch/sparc/tracechild.cc @@ -230,7 +230,7 @@ SparcTraceChild::getTargets(uint32_t inst, uint64_t pc, uint64_t npc, target1 = npc; target2 = npc + 4; return 2; - } else if(ba) { + } else if (ba) { //This branches immediately to the effective address of the branch //which we'll have to calculate. uint64_t disp = 0; @@ -249,7 +249,7 @@ SparcTraceChild::getTargets(uint32_t inst, uint64_t pc, uint64_t npc, //smart enough to turn this into a shift. disp *= 4; target1 = pc + disp; - } else if(bn) + } else if (bn) target1 = npc + 4; else target1 = npc; @@ -416,7 +416,7 @@ SparcTraceChild::outputStartState(ostream & os) sp, argCount++, cargv); os << obuf; sp += v8 ? 4 : 8; - } while(cargv); + } while (cargv); //Output the envp pointers int envCount = 0; uint64_t cenvp; diff --git a/util/tlm/main.cc b/util/tlm/main.cc index 8add0aeef..c06565603 100644 --- a/util/tlm/main.cc +++ b/util/tlm/main.cc @@ -249,7 +249,7 @@ SimControl::run() { GlobalSimLoopExitEvent *exit_event = NULL; - if(sim_end == 0) { + if (sim_end == 0) { exit_event = simulate(); } else { exit_event = simulate(sim_end); diff --git a/util/tlm/sc_mm.cc b/util/tlm/sc_mm.cc index 509d429c2..2a169a37a 100644 --- a/util/tlm/sc_mm.cc +++ b/util/tlm/sc_mm.cc @@ -47,7 +47,7 @@ MemoryManager::MemoryManager(): numberOfAllocations(0), numberOfFrees(0) MemoryManager::~MemoryManager() { - for(gp* payload: freePayloads) { + for (gp* payload: freePayloads) { delete payload; numberOfFrees++; } @@ -56,7 +56,7 @@ MemoryManager::~MemoryManager() gp* MemoryManager::allocate() { - if(freePayloads.empty()) { + if (freePayloads.empty()) { numberOfAllocations++; return new gp(this); } else { diff --git a/util/tlm/sc_port.cc b/util/tlm/sc_port.cc index 3f2798021..04efce87b 100644 --- a/util/tlm/sc_port.cc +++ b/util/tlm/sc_port.cc @@ -191,7 +191,7 @@ sc_transactor::recvTimingReq(PacketPtr packet) /* NOTE: normal tlm is blocking here. But in our case we return false * and tell gem5 when a retry can be done. This is the main difference * in the protocol: - * if(requestInProgress) + * if (requestInProgress) * { * wait(endRequestEvent); * } @@ -214,11 +214,11 @@ sc_transactor::recvTimingReq(PacketPtr packet) tlm::tlm_sync_enum status; status = iSocket->nb_transport_fw(*trans, phase, delay); /* Check returned value: */ - if(status == tlm::TLM_ACCEPTED) { + if (status == tlm::TLM_ACCEPTED) { sc_assert(phase == tlm::BEGIN_REQ); /* Accepted but is now blocking until END_REQ (exclusion rule)*/ blockingRequest = trans; - } else if(status == tlm::TLM_UPDATED) { + } else if (status == tlm::TLM_UPDATED) { /* The Timing annotation must be honored: */ sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP); @@ -226,7 +226,7 @@ sc_transactor::recvTimingReq(PacketPtr packet) pe = new payloadEvent<sc_transactor>(*this, &sc_transactor::pec, "PEQ"); pe->notify(*trans, phase, delay); - } else if(status == tlm::TLM_COMPLETED) { + } else if (status == tlm::TLM_COMPLETED) { /* Transaction is over nothing has do be done. */ sc_assert(phase == tlm::END_RESP); trans->release(); @@ -243,7 +243,7 @@ sc_transactor::pec( { sc_time delay; - if(phase == tlm::END_REQ || + if (phase == tlm::END_REQ || &trans == blockingRequest && phase == tlm::BEGIN_RESP) { sc_assert(&trans == blockingRequest); blockingRequest = NULL; @@ -254,7 +254,7 @@ sc_transactor::pec( iSocket.sendRetryReq(); } } - else if(phase == tlm::BEGIN_RESP) + else if (phase == tlm::BEGIN_RESP) { CAUGHT_UP; diff --git a/util/tlm/sc_target.cc b/util/tlm/sc_target.cc index 69025b387..bae1de126 100644 --- a/util/tlm/sc_target.cc +++ b/util/tlm/sc_target.cc @@ -84,12 +84,12 @@ Target::transport_dbg(tlm::tlm_generic_payload& trans) /* Load / Store the access: */ if ( cmd == tlm::TLM_READ_COMMAND ) { - if(debug) { + if (debug) { SC_REPORT_INFO("target", "tlm::TLM_READ_COMMAND"); } std::memcpy(ptr, mem_array_ptr, len); } else if ( cmd == tlm::TLM_WRITE_COMMAND ) { - if(debug) { + if (debug) { SC_REPORT_INFO("target", "tlm::TLM_WRITE_COMMAND"); } std::memcpy(mem_array_ptr, ptr, len); @@ -115,8 +115,8 @@ Target::peq_cb(tlm::tlm_generic_payload& trans, { sc_time delay; - if(phase == tlm::BEGIN_REQ) { - if(debug) SC_REPORT_INFO("target", "tlm::BEGIN_REQ"); + if (phase == tlm::BEGIN_REQ) { + if (debug) SC_REPORT_INFO("target", "tlm::BEGIN_REQ"); /* Increment the transaction reference count */ trans.acquire(); @@ -226,12 +226,12 @@ Target::execute_transaction(tlm::tlm_generic_payload& trans) /* Load / Store the access: */ if ( cmd == tlm::TLM_READ_COMMAND ) { - if(debug) { + if (debug) { SC_REPORT_INFO("target", "tlm::TLM_READ_COMMAND"); } std::memcpy(ptr, mem_array_ptr, len); } else if ( cmd == tlm::TLM_WRITE_COMMAND ) { - if(debug) { + if (debug) { SC_REPORT_INFO("target", "tlm::TLM_WRITE_COMMAND"); } std::memcpy(mem_array_ptr, ptr, len); |