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authorAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:12:32 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:12:32 -0400
commit9baa35ba802f2cfb9fb9ecdebf111f4cd793a428 (patch)
tree80f13a9816d592a550be1f7f582afe9dc6c2c781 /util
parentd7ad8dc608dd6de4ff9c930de79edcdc3bdf8d40 (diff)
downloadgem5-9baa35ba802f2cfb9fb9ecdebf111f4cd793a428.tar.xz
Mem: Separate the host and guest views of memory backing store
This patch moves all the memory backing store operations from the independent memory controllers to the global physical memory. The main reason for this patch is to allow address striping in a future set of patches, but at this point it already provides some useful functionality in that it is now possible to change the number of memory controllers and their address mapping in combination with checkpointing. Thus, the host and guest view of the memory backing store are now completely separate. With this patch, the individual memory controllers are far simpler as all responsibility for serializing/unserializing is moved to the physical memory. Currently, the functionality is more or less moved from AbstractMemory to PhysicalMemory without any major changes. However, in a future patch the physical memory will also resolve any ranges that are interleaved and properly assign the backing store to the memory controllers, and keep the host memory as a single contigous chunk per address range. Functionality for future extensions which involve CPU virtualization also enable the host to get pointers to the backing store.
Diffstat (limited to 'util')
-rwxr-xr-xutil/cpt_upgrader.py36
1 files changed, 32 insertions, 4 deletions
diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 76d61acf9..09e6ef194 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -61,11 +61,8 @@ import ConfigParser
import sys, os
import os.path as osp
-def from_0(cpt):
- pass
-
# An example of a translator
-def from_1(cpt):
+def from_0(cpt):
if cpt.get('root','isa') == 'arm':
for sec in cpt.sections():
import re
@@ -77,6 +74,37 @@ def from_1(cpt):
#mr.insert(26,0)
cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
+# The backing store supporting the memories in the system has changed
+# in that it is now stored globally per address range. As a result the
+# actual storage is separate from the memory controllers themselves.
+def from_1(cpt):
+ for sec in cpt.sections():
+ import re
+ # Search for a physical memory
+ if re.search('.*sys.*\.physmem$', sec):
+ # Add the number of stores attribute to the global physmem
+ cpt.set(sec, 'nbr_of_stores', '1')
+
+ # Get the filename and size as this is moving to the
+ # specific backing store
+ mem_filename = cpt.get(sec, 'filename')
+ mem_size = cpt.get(sec, '_size')
+ cpt.remove_option(sec, 'filename')
+ cpt.remove_option(sec, '_size')
+
+ # Get the name so that we can create the new section
+ system_name = str(sec).split('.')[0]
+ section_name = system_name + '.physmem.store0'
+ cpt.add_section(section_name)
+ cpt.set(section_name, 'store_id', '0')
+ cpt.set(section_name, 'range_size', mem_size)
+ cpt.set(section_name, 'filename', mem_filename)
+ elif re.search('.*sys.*\.\w*mem$', sec):
+ # Due to the lack of information about a start address,
+ # this migration only works if there is a single memory in
+ # the system, thus starting at 0
+ raise ValueError("more than one memory detected (" + sec + ")")
+
migrations = []
migrations.append(from_0)
migrations.append(from_1)