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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-24 11:52:49 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-24 11:52:49 -0500
commit0cd0a8fdd3dc1e329673e2c034e67c2694a6908e (patch)
tree3c7031ad4313e3b982c7d2294aad72538908f2f2 /util
parent77878d0a87ee18709ca4d6459b8ae436cc101fa7 (diff)
downloadgem5-0cd0a8fdd3dc1e329673e2c034e67c2694a6908e.tar.xz
MEM: Simplify cache ports preparing for master/slave split
This patch splits the two cache ports into a master (memory-side) and slave (cpu-side) subclass of port with slightly different functionality. For example, it is only the CPU-side port that blocks incoming requests, and only the memory-side port that schedules send events outside of what the transmit list dictates. This patch simplifies the two classes by relying further on SimpleTimingPort and also generalises the latter to better accommodate the changes (introducing trySendTiming and scheduleSend). The memory-side cache port overrides sendDeferredPacket to be able to not only send responses from the transmit list, but also send requests based on the MSHRs. A follow on patch further simplifies the SimpleTimingPort and the cache ports.
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