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-rw-r--r--src/cpu/base.cc23
-rw-r--r--src/cpu/base.hh38
-rw-r--r--src/cpu/checker/cpu.cc4
-rw-r--r--src/cpu/checker/cpu.hh12
-rw-r--r--src/cpu/inorder/cpu.cc2
-rw-r--r--src/cpu/inorder/cpu.hh8
-rw-r--r--src/cpu/o3/cpu.hh19
-rw-r--r--src/cpu/simple/atomic.hh25
-rw-r--r--src/cpu/simple/timing.hh10
9 files changed, 53 insertions, 88 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 36caea79a..de0f8b23b 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -312,7 +312,7 @@ BaseCPU::getMasterPort(const string &if_name, PortID idx)
// Get the right port based on name. This applies to all the
// subclasses of the base CPU and relies on their implementation
// of getDataPort and getInstPort. In all cases there methods
- // return a CpuPort pointer.
+ // return a MasterPort pointer.
if (if_name == "dcache_port")
return getDataPort();
else if (if_name == "icache_port")
@@ -585,24 +585,3 @@ BaseCPU::traceFunctionsInternal(Addr pc)
functionEntryTick = curTick();
}
}
-
-bool
-BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt)
-{
- panic("BaseCPU doesn't expect recvTiming!\n");
- return true;
-}
-
-void
-BaseCPU::CpuPort::recvRetry()
-{
- panic("BaseCPU doesn't expect recvRetry!\n");
-}
-
-void
-BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt)
-{
- // No internal storage to update (in the general case). A CPU with
- // internal storage, e.g. an LSQ that should be part of the
- // coherent memory has to check against stored data.
-}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 073050816..34e1f718c 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -117,38 +117,6 @@ class BaseCPU : public MemObject
/** Is the CPU switched out or active? */
bool _switchedOut;
- /**
- * Define a base class for the CPU ports (instruction and data)
- * that is refined in the subclasses. This class handles the
- * common cases, i.e. the functional accesses and the status
- * changes and address range queries. The default behaviour for
- * both atomic and timing access is to panic and the corresponding
- * subclasses have to override these methods.
- */
- class CpuPort : public MasterPort
- {
- public:
-
- /**
- * Create a CPU port with a name and a structural owner.
- *
- * @param _name port name including the owner
- * @param _name structural owner of this port
- */
- CpuPort(const std::string& _name, MemObject* _owner) :
- MasterPort(_name, _owner)
- { }
-
- protected:
-
- virtual bool recvTimingResp(PacketPtr pkt);
-
- virtual void recvRetry();
-
- virtual void recvFunctionalSnoop(PacketPtr pkt);
-
- };
-
public:
/**
@@ -157,7 +125,7 @@ class BaseCPU : public MemObject
*
* @return a reference to the data port
*/
- virtual CpuPort &getDataPort() = 0;
+ virtual MasterPort &getDataPort() = 0;
/**
* Purely virtual method that returns a reference to the instruction
@@ -165,7 +133,7 @@ class BaseCPU : public MemObject
*
* @return a reference to the instruction port
*/
- virtual CpuPort &getInstPort() = 0;
+ virtual MasterPort &getInstPort() = 0;
/** Reads this CPU's ID. */
int cpuId() { return _cpuId; }
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index f695c24df..c824121be 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -117,13 +117,13 @@ CheckerCPU::setSystem(System *system)
}
void
-CheckerCPU::setIcachePort(CpuPort *icache_port)
+CheckerCPU::setIcachePort(MasterPort *icache_port)
{
icachePort = icache_port;
}
void
-CheckerCPU::setDcachePort(CpuPort *dcache_port)
+CheckerCPU::setDcachePort(MasterPort *dcache_port)
{
dcachePort = dcache_port;
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 6bd2b7e31..19d3420ec 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -104,11 +104,11 @@ class CheckerCPU : public BaseCPU
void setSystem(System *system);
- void setIcachePort(CpuPort *icache_port);
+ void setIcachePort(MasterPort *icache_port);
- void setDcachePort(CpuPort *dcache_port);
+ void setDcachePort(MasterPort *dcache_port);
- CpuPort &getDataPort()
+ MasterPort &getDataPort()
{
// the checker does not have ports on its own so return the
// data port of the actual CPU core
@@ -116,7 +116,7 @@ class CheckerCPU : public BaseCPU
return *dcachePort;
}
- CpuPort &getInstPort()
+ MasterPort &getInstPort()
{
// the checker does not have ports on its own so return the
// data port of the actual CPU core
@@ -130,8 +130,8 @@ class CheckerCPU : public BaseCPU
System *systemPtr;
- CpuPort *icachePort;
- CpuPort *dcachePort;
+ MasterPort *icachePort;
+ MasterPort *dcachePort;
ThreadContext *tc;
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 1ba8e55b6..5c07621e3 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -84,7 +84,7 @@ using namespace ThePipeline;
InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit,
const std::string& name) :
- CpuPort(_cacheUnit->name() + name, _cacheUnit->cpu),
+ MasterPort(_cacheUnit->name() + name, _cacheUnit->cpu),
cacheUnit(_cacheUnit)
{ }
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 7ca4355de..e69c9d47b 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -112,10 +112,10 @@ class InOrderCPU : public BaseCPU
void verifyMemoryMode() const;
/** Return a reference to the data port. */
- virtual CpuPort &getDataPort() { return dataPort; }
+ virtual MasterPort &getDataPort() { return dataPort; }
/** Return a reference to the instruction port. */
- virtual CpuPort &getInstPort() { return instPort; }
+ virtual MasterPort &getInstPort() { return instPort; }
/** CPU ID */
int cpu_id;
@@ -158,7 +158,7 @@ class InOrderCPU : public BaseCPU
* CachePort class for the in-order CPU, interacting with a
* specific CacheUnit in the pipeline.
*/
- class CachePort : public CpuPort
+ class CachePort : public MasterPort
{
private:
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 719d38ef0..98a6972e9 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -129,7 +129,7 @@ class FullO3CPU : public BaseO3CPU
/**
* IcachePort class for instruction fetch.
*/
- class IcachePort : public CpuPort
+ class IcachePort : public MasterPort
{
protected:
/** Pointer to fetch. */
@@ -138,7 +138,7 @@ class FullO3CPU : public BaseO3CPU
public:
/** Default constructor. */
IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
- : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
+ : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
{ }
protected:
@@ -155,7 +155,7 @@ class FullO3CPU : public BaseO3CPU
/**
* DcachePort class for the load/store queue.
*/
- class DcachePort : public CpuPort
+ class DcachePort : public MasterPort
{
protected:
@@ -165,7 +165,7 @@ class FullO3CPU : public BaseO3CPU
public:
/** Default constructor. */
DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
- : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
+ : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
{ }
protected:
@@ -176,6 +176,11 @@ class FullO3CPU : public BaseO3CPU
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvTimingSnoopReq(PacketPtr pkt);
+ virtual void recvFunctionalSnoop(PacketPtr pkt)
+ {
+ // @todo: Is there a need for potential invalidation here?
+ }
+
/** Handles doing a retry of the previous send. */
virtual void recvRetry();
@@ -807,10 +812,10 @@ class FullO3CPU : public BaseO3CPU
}
/** Used by the fetch unit to get a hold of the instruction port. */
- virtual CpuPort &getInstPort() { return icachePort; }
+ virtual MasterPort &getInstPort() { return icachePort; }
/** Get the dcache port (used to find block size for translations). */
- virtual CpuPort &getDataPort() { return dcachePort; }
+ virtual MasterPort &getDataPort() { return dcachePort; }
/** Stat for total number of times the CPU is descheduled. */
Stats::Scalar timesIdled;
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index e3eafe8e0..9bb653bcc 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -116,15 +116,17 @@ class AtomicSimpleCPU : public BaseSimpleCPU
/**
* An AtomicCPUPort overrides the default behaviour of the
- * recvAtomic and ignores the packet instead of panicking.
+ * recvAtomicSnoop and ignores the packet instead of panicking. It
+ * also provides an implementation for the purely virtual timing
+ * functions and panics on either of these.
*/
- class AtomicCPUPort : public CpuPort
+ class AtomicCPUPort : public MasterPort
{
public:
AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
- : CpuPort(_name, _cpu)
+ : MasterPort(_name, _cpu)
{ }
protected:
@@ -135,6 +137,17 @@ class AtomicSimpleCPU : public BaseSimpleCPU
return 0;
}
+ bool recvTimingResp(PacketPtr pkt)
+ {
+ panic("Atomic CPU doesn't expect recvTimingResp!\n");
+ return true;
+ }
+
+ void recvRetry()
+ {
+ panic("Atomic CPU doesn't expect recvRetry!\n");
+ }
+
};
AtomicCPUPort icachePort;
@@ -151,10 +164,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU
protected:
/** Return a reference to the data port. */
- virtual CpuPort &getDataPort() { return dcachePort; }
+ virtual MasterPort &getDataPort() { return dcachePort; }
/** Return a reference to the instruction port. */
- virtual CpuPort &getInstPort() { return icachePort; }
+ virtual MasterPort &getInstPort() { return icachePort; }
public:
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 348129150..cab2057ea 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -152,12 +152,12 @@ class TimingSimpleCPU : public BaseSimpleCPU
* scheduling of handling of incoming packets in the following
* cycle.
*/
- class TimingCPUPort : public CpuPort
+ class TimingCPUPort : public MasterPort
{
public:
TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
- : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this)
+ : MasterPort(_name, _cpu), cpu(_cpu), retryEvent(this)
{ }
protected:
@@ -248,10 +248,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
/** Return a reference to the data port. */
- virtual CpuPort &getDataPort() { return dcachePort; }
+ virtual MasterPort &getDataPort() { return dcachePort; }
/** Return a reference to the instruction port. */
- virtual CpuPort &getInstPort() { return icachePort; }
+ virtual MasterPort &getInstPort() { return icachePort; }
public:
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 13:34:15 +0000