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-rw-r--r--src/arch/arm/table_walker.cc47
-rw-r--r--src/arch/arm/table_walker.hh5
-rw-r--r--src/cpu/base.cc10
-rw-r--r--src/cpu/o3/commit_impl.hh3
-rw-r--r--src/cpu/o3/cpu.cc15
-rw-r--r--src/cpu/o3/fetch_impl.hh7
-rw-r--r--src/cpu/o3/lsq_unit.hh5
-rw-r--r--src/cpu/simple/timing.cc4
-rw-r--r--src/dev/copy_engine.cc7
-rw-r--r--src/dev/dma_device.cc11
-rw-r--r--src/dev/i8254xGBe.cc9
-rw-r--r--src/mem/bus.cc3
-rw-r--r--src/mem/cache/base.cc2
-rw-r--r--src/mem/packet_queue.cc6
-rw-r--r--src/mem/port.cc12
-rw-r--r--src/mem/port.hh2
-rw-r--r--src/mem/ruby/system/RubyPort.cc5
-rw-r--r--src/sim/SConscript1
18 files changed, 117 insertions, 37 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index dfb406543..7dbe92d9b 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -43,6 +43,7 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Checkpoint.hh"
+#include "debug/Drain.hh"
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
#include "sim/system.hh"
@@ -51,7 +52,7 @@ using namespace ArmISA;
TableWalker::TableWalker(const Params *p)
: MemObject(p), port(this, params()->sys, params()->min_backoff,
- params()->max_backoff),
+ params()->max_backoff), drainEvent(NULL),
tlb(NULL), currState(NULL), pending(false),
masterId(p->sys->getMasterId(name())),
doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
@@ -64,20 +65,38 @@ TableWalker::~TableWalker()
;
}
+void
+TableWalker::completeDrain()
+{
+ if (drainEvent && stateQueueL1.empty() && stateQueueL2.empty() &&
+ pendingQueue.empty()) {
+ changeState(Drained);
+ DPRINTF(Drain, "TableWalker done draining, processing drain event\n");
+ drainEvent->process();
+ drainEvent = NULL;
+ }
+}
+
unsigned int
TableWalker::drain(Event *de)
{
- if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size())
- {
- changeState(Draining);
- DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n");
- return 1;
- }
- else
- {
+ unsigned int count = port.drain(de);
+
+ if (stateQueueL1.empty() && stateQueueL2.empty() &&
+ pendingQueue.empty()) {
changeState(Drained);
- DPRINTF(Checkpoint, "TableWalker free, no need to drain\n");
- return 0;
+ DPRINTF(Drain, "TableWalker free, no need to drain\n");
+
+ // table walker is drained, but its ports may still need to be drained
+ return count;
+ } else {
+ drainEvent = de;
+ changeState(Draining);
+ DPRINTF(Drain, "TableWalker not drained\n");
+
+ // return port drain count plus the table walker itself needs to drain
+ return count + 1;
+
}
}
@@ -86,8 +105,8 @@ TableWalker::resume()
{
MemObject::resume();
if ((params()->sys->getMemoryMode() == Enums::timing) && currState) {
- delete currState;
- currState = NULL;
+ delete currState;
+ currState = NULL;
}
}
@@ -667,6 +686,7 @@ TableWalker::doL1DescriptorWrapper()
doL1Descriptor();
stateQueueL1.pop_front();
+ completeDrain();
// Check if fault was generated
if (currState->fault != NoFault) {
currState->transState->finish(currState->fault, currState->req,
@@ -723,6 +743,7 @@ TableWalker::doL2DescriptorWrapper()
stateQueueL2.pop_front();
+ completeDrain();
pending = false;
nextWalk(currState->tc);
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index db6b01cd4..1b95182c8 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -364,6 +364,9 @@ class TableWalker : public MemObject
/** Port to issue translation requests from */
SnoopingDmaPort port;
+ /** If we're draining keep the drain event around until we're drained */
+ Event *drainEvent;
+
/** TLB that is initiating these table walks */
TLB *tlb;
@@ -389,6 +392,8 @@ class TableWalker : public MemObject
return dynamic_cast<const Params *>(_params);
}
+ /** Checks if all state is cleared and if so, completes drain */
+ void completeDrain();
virtual unsigned int drain(Event *de);
virtual void resume();
virtual MasterPort& getMasterPort(const std::string &if_name,
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 4017140a5..893b0e06b 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -385,8 +385,7 @@ void
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
assert(threadContexts.size() == oldCPU->threadContexts.size());
-
- _cpuId = oldCPU->cpuId();
+ assert(_cpuId == oldCPU->cpuId());
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
@@ -418,11 +417,13 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
assert(old_itb_port);
SlavePort &slavePort = old_itb_port->getSlavePort();
new_itb_port->bind(slavePort);
+ old_itb_port->unBind();
}
if (new_dtb_port && !new_dtb_port->isConnected()) {
assert(old_dtb_port);
SlavePort &slavePort = old_dtb_port->getSlavePort();
new_dtb_port->bind(slavePort);
+ old_dtb_port->unBind();
}
// Checker whether or not we have to transfer CheckerCPU
@@ -444,17 +445,20 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
assert(old_checker_itb_port);
SlavePort &slavePort = old_checker_itb_port->getSlavePort();;
new_checker_itb_port->bind(slavePort);
+ old_checker_itb_port->unBind();
}
if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
assert(old_checker_dtb_port);
SlavePort &slavePort = old_checker_dtb_port->getSlavePort();;
new_checker_dtb_port->bind(slavePort);
+ old_checker_dtb_port->unBind();
}
}
}
interrupts = oldCPU->interrupts;
interrupts->setCPU(this);
+ oldCPU->interrupts = NULL;
if (FullSystem) {
for (ThreadID i = 0; i < size; ++i)
@@ -469,10 +473,12 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
// CPU.
if (!getInstPort().isConnected()) {
getInstPort().bind(oldCPU->getInstPort().getSlavePort());
+ oldCPU->getInstPort().unBind();
}
if (!getDataPort().isConnected()) {
getDataPort().bind(oldCPU->getDataPort().getSlavePort());
+ oldCPU->getDataPort().unBind();
}
}
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 45f5bc02b..31398c3d9 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -631,7 +631,8 @@ DefaultCommit<Impl>::tick()
wroteToTimeBuffer = false;
_nextStatus = Inactive;
- if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
+ if (drainPending && cpu->instList.empty() && !iewStage->hasStoresToWB() &&
+ interrupt == NoFault) {
cpu->signalDrained();
drainPending = false;
return;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index e8fc968b7..64c54e26a 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -55,6 +55,7 @@
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "debug/Activity.hh"
+#include "debug/Drain.hh"
#include "debug/O3CPU.hh"
#include "debug/Quiesce.hh"
#include "enums/MemoryMode.hh"
@@ -260,7 +261,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
if (!deferRegistration) {
_status = Running;
} else {
- _status = Idle;
+ _status = SwitchedOut;
}
if (params->checker) {
@@ -1119,9 +1120,8 @@ FullO3CPU<Impl>::drain(Event *drain_event)
DPRINTF(O3CPU, "Switching out\n");
// If the CPU isn't doing anything, then return immediately.
- if (_status == Idle || _status == SwitchedOut) {
+ if (_status == SwitchedOut)
return 0;
- }
drainCount = 0;
fetch.drain();
@@ -1142,6 +1142,8 @@ FullO3CPU<Impl>::drain(Event *drain_event)
wakeCPU();
activityRec.activity();
+ DPRINTF(Drain, "CPU not drained\n");
+
return 1;
} else {
return 0;
@@ -1160,7 +1162,7 @@ FullO3CPU<Impl>::resume()
changeState(SimObject::Running);
- if (_status == SwitchedOut || _status == Idle)
+ if (_status == SwitchedOut)
return;
assert(system->getMemoryMode() == Enums::timing);
@@ -1183,6 +1185,7 @@ FullO3CPU<Impl>::signalDrained()
BaseCPU::switchOut();
if (drainEvent) {
+ DPRINTF(Drain, "CPU done draining, processing drain event\n");
drainEvent->process();
drainEvent = NULL;
}
@@ -1237,6 +1240,10 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
assert(!tickEvent.scheduled() || tickEvent.squashed());
+ FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
+ if (oldO3CPU)
+ globalSeqNum = oldO3CPU->globalSeqNum;
+
// @todo: Figure out how to properly select the tid to put onto
// the active threads list.
ThreadID tid = 0;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index b6eb25c08..81d70bd61 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -132,8 +132,10 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
// Get the size of an instruction.
instSize = sizeof(TheISA::MachInst);
- for (int i = 0; i < Impl::MaxThreads; i++)
+ for (int i = 0; i < Impl::MaxThreads; i++) {
+ cacheData[i] = NULL;
decoder[i] = new TheISA::Decoder(NULL);
+ }
}
template <class Impl>
@@ -346,7 +348,8 @@ DefaultFetch<Impl>::setIcache()
for (ThreadID tid = 0; tid < numThreads; tid++) {
// Create space to store a cache line.
- cacheData[tid] = new uint8_t[cacheBlkSize];
+ if (!cacheData[tid])
+ cacheData[tid] = new uint8_t[cacheBlkSize];
cacheDataPC[tid] = 0;
cacheDataValid[tid] = false;
}
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 7093b5fee..b886a2259 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -335,6 +335,11 @@ class LSQUnit {
std::memset(data, 0, sizeof(data));
}
+ ~SQEntry()
+ {
+ inst = NULL;
+ }
+
/** Constructs a store queue entry for a given instruction. */
SQEntry(DynInstPtr &_inst)
: inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index bae40eba4..6a9fe7efc 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -48,6 +48,7 @@
#include "cpu/simple/timing.hh"
#include "cpu/exetrace.hh"
#include "debug/Config.hh"
+#include "debug/Drain.hh"
#include "debug/ExecFaulting.hh"
#include "debug/SimpleCPU.hh"
#include "mem/packet.hh"
@@ -129,6 +130,7 @@ TimingSimpleCPU::drain(Event *drain_event)
} else {
changeState(SimObject::Draining);
drainEvent = drain_event;
+ DPRINTF(Drain, "CPU not drained\n");
return 1;
}
}
@@ -829,7 +831,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
void
TimingSimpleCPU::completeDrain()
{
- DPRINTF(Config, "Done draining\n");
+ DPRINTF(Drain, "CPU done draining, processing drain event\n");
changeState(SimObject::Drained);
drainEvent->process();
}
diff --git a/src/dev/copy_engine.cc b/src/dev/copy_engine.cc
index 809649718..bb15abab6 100644
--- a/src/dev/copy_engine.cc
+++ b/src/dev/copy_engine.cc
@@ -49,6 +49,7 @@
#include "base/cp_annotate.hh"
#include "base/trace.hh"
#include "debug/DMACopyEngine.hh"
+#include "debug/Drain.hh"
#include "dev/copy_engine.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
@@ -638,7 +639,7 @@ bool
CopyEngine::CopyEngineChannel::inDrain()
{
if (ce->getState() == SimObject::Draining) {
- DPRINTF(DMACopyEngine, "processing drain\n");
+ DPRINTF(Drain, "CopyEngine done draining, processing drain event\n");
assert(drainEvent);
drainEvent->process();
drainEvent = NULL;
@@ -655,7 +656,7 @@ CopyEngine::CopyEngineChannel::drain(Event *de)
unsigned int count = 1;
count += cePort.drain(de);
- DPRINTF(DMACopyEngine, "unable to drain, returning %d\n", count);
+ DPRINTF(Drain, "CopyEngineChannel not drained\n");
drainEvent = de;
return count;
}
@@ -673,7 +674,7 @@ CopyEngine::drain(Event *de)
else
changeState(Drained);
- DPRINTF(DMACopyEngine, "call to CopyEngine::drain() returning %d\n", count);
+ DPRINTF(Drain, "CopyEngine not drained\n");
return count;
}
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index ddc8e7386..5a2f52df1 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -43,6 +43,7 @@
#include "base/chunk_generator.hh"
#include "debug/DMA.hh"
+#include "debug/Drain.hh"
#include "dev/dma_device.hh"
#include "sim/system.hh"
@@ -103,7 +104,7 @@ DmaPort::recvTimingResp(PacketPtr pkt)
delete pkt->req;
delete pkt;
- if (pendingCount == 0 && drainEvent) {
+ if (pendingCount == 0 && transmitList.empty() && drainEvent) {
drainEvent->process();
drainEvent = NULL;
}
@@ -142,9 +143,10 @@ DmaDevice::drain(Event *de)
unsigned int
DmaPort::drain(Event *de)
{
- if (pendingCount == 0)
+ if (transmitList.empty() && pendingCount == 0)
return 0;
drainEvent = de;
+ DPRINTF(Drain, "DmaPort not drained\n");
return 1;
}
@@ -182,8 +184,6 @@ void
DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data, Tick delay, Request::Flags flag)
{
- assert(device->getState() == SimObject::Running);
-
DmaReqState *reqState = new DmaReqState(event, size, delay);
@@ -287,7 +287,8 @@ DmaPort::sendDma()
assert(pendingCount >= 0);
delete pkt;
- if (pendingCount == 0 && drainEvent) {
+ if (pendingCount == 0 && transmitList.empty() && drainEvent) {
+ DPRINTF(Drain, "DmaPort done draining, processing drain event\n");
drainEvent->process();
drainEvent = NULL;
}
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 1f2c92425..14d767288 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -44,6 +44,7 @@
#include "base/inet.hh"
#include "base/trace.hh"
+#include "debug/Drain.hh"
#include "debug/EthernetAll.hh"
#include "dev/i8254xGBe.hh"
#include "mem/packet.hh"
@@ -2072,12 +2073,12 @@ IGbE::drain(Event *de)
if (tickEvent.scheduled())
deschedule(tickEvent);
- if (count)
+ if (count) {
+ DPRINTF(Drain, "IGbE not drained\n");
changeState(Draining);
- else
+ } else
changeState(Drained);
- DPRINTF(EthernetSM, "got drain() returning %d", count);
return count;
}
@@ -2100,12 +2101,12 @@ IGbE::checkDrain()
if (!drainEvent)
return;
- DPRINTF(EthernetSM, "checkDrain() in drain\n");
txFifoTick = false;
txTick = false;
rxTick = false;
if (!rxDescCache.hasOutstandingEvents() &&
!txDescCache.hasOutstandingEvents()) {
+ DPRINTF(Drain, "IGbE done draining, processing drain event\n");
drainEvent->process();
drainEvent = NULL;
}
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index ab8b76594..583e60a15 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -52,6 +52,7 @@
#include "base/trace.hh"
#include "debug/Bus.hh"
#include "debug/BusAddrRanges.hh"
+#include "debug/Drain.hh"
#include "mem/bus.hh"
BaseBus::BaseBus(const BaseBusParams *p)
@@ -246,6 +247,7 @@ BaseBus::Layer<PortClass>::releaseLayer()
// we see a retry from the destination
retryWaiting();
} else if (drainEvent) {
+ DPRINTF(Drain, "Bus done draining, processing drain event\n");
//If we weren't able to drain before, do it now.
drainEvent->process();
// Clear the drain event once we're done with it.
@@ -498,6 +500,7 @@ BaseBus::Layer<PortClass>::drain(Event * de)
//waiting. We might be idle but have someone waiting if the device we
//contacted for a retry didn't actually retry.
if (!retryList.empty() || state != IDLE) {
+ DPRINTF(Drain, "Bus not drained\n");
drainEvent = de;
return 1;
}
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 4ae6376db..c175d5958 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -48,6 +48,7 @@
#include "cpu/base.hh"
#include "cpu/smt.hh"
#include "debug/Cache.hh"
+#include "debug/Drain.hh"
#include "mem/cache/base.hh"
#include "mem/cache/mshr.hh"
#include "sim/full_system.hh"
@@ -752,6 +753,7 @@ BaseCache::drain(Event *de)
drainEvent = de;
changeState(SimObject::Draining);
+ DPRINTF(Drain, "Cache not drained\n");
return count;
}
diff --git a/src/mem/packet_queue.cc b/src/mem/packet_queue.cc
index ab50fd567..77fba8883 100644
--- a/src/mem/packet_queue.cc
+++ b/src/mem/packet_queue.cc
@@ -41,6 +41,7 @@
* Andreas Hansson
*/
+#include "debug/Drain.hh"
#include "debug/PacketQueue.hh"
#include "mem/packet_queue.hh"
@@ -168,7 +169,9 @@ PacketQueue::scheduleSend(Tick time)
em.schedule(&sendEvent, std::max(nextReady, curTick() + 1));
} else {
// no more to send, so if we're draining, we may be done
- if (drainEvent && !sendEvent.scheduled()) {
+ if (drainEvent && transmitList.empty() && !sendEvent.scheduled()) {
+ DPRINTF(Drain, "PacketQueue done draining,"
+ "processing drain event\n");
drainEvent->process();
drainEvent = NULL;
}
@@ -201,6 +204,7 @@ PacketQueue::drain(Event *de)
{
if (transmitList.empty() && !sendEvent.scheduled())
return 0;
+ DPRINTF(Drain, "PacketQueue not drained\n");
drainEvent = de;
return 1;
}
diff --git a/src/mem/port.cc b/src/mem/port.cc
index 36ca6304a..3827994fb 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -82,6 +82,12 @@ MasterPort::getSlavePort() const
}
void
+MasterPort::unBind()
+{
+ _slavePort = NULL;
+}
+
+void
MasterPort::bind(SlavePort& slave_port)
{
// master port keeps track of the slave port
@@ -167,6 +173,12 @@ SlavePort::~SlavePort()
}
void
+SlavePort::unBind()
+{
+ _masterPort = NULL;
+}
+
+void
SlavePort::bind(MasterPort& master_port)
{
_masterPort = &master_port;
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 35f2993df..eac92791e 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -140,6 +140,7 @@ class MasterPort : public Port
PortID id = InvalidPortID);
virtual ~MasterPort();
+ void unBind();
void bind(SlavePort& slave_port);
SlavePort& getSlavePort() const;
bool isConnected() const;
@@ -297,6 +298,7 @@ class SlavePort : public Port
PortID id = InvalidPortID);
virtual ~SlavePort();
+ void unBind();
void bind(MasterPort& master_port);
MasterPort& getMasterPort() const;
bool isConnected() const;
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index a6eb4d22d..c829bf66e 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -41,6 +41,7 @@
#include "cpu/testers/rubytest/RubyTester.hh"
#include "debug/Config.hh"
+#include "debug/Drain.hh"
#include "debug/Ruby.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
@@ -524,8 +525,9 @@ RubyPort::testDrainComplete()
//If we weren't able to drain before, we might be able to now.
if (drainEvent != NULL) {
unsigned int drainCount = getDrainCount(drainEvent);
- DPRINTF(Config, "Drain count: %u\n", drainCount);
+ DPRINTF(Drain, "Drain count: %u\n", drainCount);
if (drainCount == 0) {
+ DPRINTF(Drain, "RubyPort done draining, processing drain event\n");
drainEvent->process();
// Clear the drain event once we're done with it.
drainEvent = NULL;
@@ -584,6 +586,7 @@ RubyPort::drain(Event *de)
if (count != 0) {
drainEvent = de;
+ DPRINTF(Drain, "RubyPort not drained\n");
changeState(SimObject::Draining);
return count;
}
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 25b965d59..9f76d6381 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -62,6 +62,7 @@ if env['TARGET_ISA'] != 'no':
DebugFlag('Checkpoint')
DebugFlag('Config')
+DebugFlag('Drain')
DebugFlag('Event')
DebugFlag('Fault')
DebugFlag('Flow')
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 20:23:51 +0000