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-rw-r--r--configs/common/FSConfig.py9
-rw-r--r--configs/test/fs.py12
-rw-r--r--src/python/m5/objects/BaseCPU.py28
-rw-r--r--src/python/m5/objects/O3CPU.py1
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt0
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr0
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout0
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt0
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr0
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout0
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt0
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr0
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout0
-rw-r--r--tests/quick/00.hello/test.py29
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini (renamed from tests/quick/eio1/ref/alpha/eio/detailed/config.ini)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/detailed/config.out (renamed from tests/quick/eio1/ref/alpha/eio/detailed/config.out)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt (renamed from tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr (renamed from tests/quick/eio1/ref/alpha/eio/detailed/stderr)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout (renamed from tests/quick/eio1/ref/alpha/eio/detailed/stdout)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini (renamed from tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out (renamed from tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt (renamed from tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr (renamed from tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout (renamed from tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini (renamed from tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out (renamed from tests/quick/eio1/ref/alpha/eio/simple-timing/config.out)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt (renamed from tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr (renamed from tests/quick/eio1/ref/alpha/eio/simple-timing/stderr)0
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout (renamed from tests/quick/eio1/ref/alpha/eio/simple-timing/stdout)0
-rw-r--r--tests/quick/20.eio-short/test.py30
-rw-r--r--tests/quick/eio1/test.py2
-rw-r--r--tests/run.py11
-rw-r--r--tests/simple-atomic.py4
-rw-r--r--tests/simple-timing.py14
-rwxr-xr-xtests/test-progs/hello/bin/alpha/linux/hello (renamed from configs/test/hello)bin312176 -> 312176 bytes
-rwxr-xr-xtests/test-progs/hello/bin/mips/linux/hello_mips (renamed from configs/test/hello_mips)bin837626 -> 837626 bytes
-rwxr-xr-xtests/test-progs/hello/bin/sparc/bin (renamed from configs/test/sparc_tests/hello_sparc)bin644149 -> 644149 bytes
37 files changed, 113 insertions, 27 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index c6ad8ce48..7d62297a9 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -31,7 +31,6 @@ from m5 import makeList
from m5.objects import *
from Benchmarks import *
from FullO3Config import *
-from Util import *
class CowIdeDisk(IdeDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
@@ -47,7 +46,7 @@ class BaseTsunami(Tsunami):
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
pci_func=0, pci_dev=0, pci_bus=0)
-def makeLinuxAlphaSystem(cpu, mem_mode, mdesc, icache=None, dcache=None, l2cache=None):
+def makeLinuxAlphaSystem(mem_mode, mdesc):
self = LinuxAlphaSystem()
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
@@ -72,13 +71,7 @@ def makeLinuxAlphaSystem(cpu, mem_mode, mdesc, icache=None, dcache=None, l2cache
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
- self.cpu = cpu
self.mem_mode = mem_mode
- connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
- for each_cpu in makeList(self.cpu):
- each_cpu.itb = AlphaITB()
- each_cpu.dtb = AlphaDTB()
- self.cpu.clock = '2GHz'
self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
self.kernel = binary('vmlinux')
self.pal = binary('ts_osfpal')
diff --git a/configs/test/fs.py b/configs/test/fs.py
index 8686cdb5b..4a3876b36 100644
--- a/configs/test/fs.py
+++ b/configs/test/fs.py
@@ -5,7 +5,6 @@ from m5.objects import *
m5.AddToPath('../common')
from FSConfig import *
from SysPaths import *
-from Util import *
from Benchmarks import *
parser = optparse.OptionParser()
@@ -50,12 +49,15 @@ if options.benchmark:
bm = Benchmarks[options.benchmark]
if len(bm) == 2:
- root = makeDualRoot(makeLinuxAlphaSystem(cpu, mem_mode, bm[0]),
- makeLinuxAlphaSystem(cpu2, mem_mode, bm[1]))
-
+ s1 = makeLinuxAlphaSystem(mem_mode, bm[0])
+ s2 = makeLinuxAlphaSystem(mem_mode, bm[1])
+ cpu.connectMemPorts(s1.membus)
+ cpu2.connectMemPorts(s2.membus)
+ root = makeDualRoot(s1, s2)
elif len(bm) == 1:
root = Root(clock = '1THz',
- system = makeLinuxAlphaSystem(cpu, mem_mode, bm[0]))
+ system = makeLinuxAlphaSystem(mem_mode, bm[0]))
+ cpu.connectMemPorts(root.system.membus)
else:
print "Error I don't know how to create more than 2 systems."
sys.exit(1)
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 5bf98be9c..4144397a6 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -1,5 +1,7 @@
from m5 import build_env
from m5.config import *
+from AlphaTLB import AlphaDTB, AlphaITB
+from Bus import Bus
class BaseCPU(SimObject):
type = 'BaseCPU'
@@ -8,8 +10,8 @@ class BaseCPU(SimObject):
system = Param.System(Parent.any, "system object")
if build_env['FULL_SYSTEM']:
- dtb = Param.AlphaDTB("Data TLB")
- itb = Param.AlphaITB("Instruction TLB")
+ dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
+ itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
cpu_id = Param.Int(-1, "CPU identifier")
else:
workload = VectorParam.Process("processes to run")
@@ -27,3 +29,25 @@ class BaseCPU(SimObject):
"defer registration with system (for sampling)")
clock = Param.Clock(Parent.clock, "clock speed")
+
+ _mem_ports = []
+
+ def connectMemPorts(self, bus):
+ for p in self._mem_ports:
+ exec('self.%s = bus.port' % p)
+
+ def addPrivateSplitL1Caches(self, ic, dc):
+ assert(len(self._mem_ports) == 2)
+ self.icache = ic
+ self.dcache = dc
+ self.icache_port = ic.cpu_side
+ self.dcache_port = dc.cpu_side
+ self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+
+ def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
+ self.addPrivateSplitL1Caches(ic, dc)
+ self.toL2Bus = Bus()
+ self.connectMemPorts(self.toL2Bus)
+ self.l2cache = l2c
+ self.l2cache.cpu_side = toL2Bus.port
+ self._mem_ports = ['l2cache.mem_side']
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 41208929a..900bbf28c 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -22,6 +22,7 @@ class DerivO3CPU(BaseCPU):
cachePorts = Param.Unsigned("Cache Ports")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
+ _mem_ports = ['icache_port', 'dcache_port']
decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
diff --git a/tests/quick/00.hello/test.py b/tests/quick/00.hello/test.py
new file mode 100644
index 000000000..fd8fd5abd
--- /dev/null
+++ b/tests/quick/00.hello/test.py
@@ -0,0 +1,29 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+root.system.cpu.workload = LiveProcess(file = binpath('hello'))
diff --git a/tests/quick/eio1/ref/alpha/eio/detailed/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini
index a442ec572..a442ec572 100644
--- a/tests/quick/eio1/ref/alpha/eio/detailed/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini
diff --git a/tests/quick/eio1/ref/alpha/eio/detailed/config.out b/tests/quick/20.eio-short/ref/alpha/eio/detailed/config.out
index c92557696..c92557696 100644
--- a/tests/quick/eio1/ref/alpha/eio/detailed/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/config.out
diff --git a/tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt
index 119cc8e9d..119cc8e9d 100644
--- a/tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt
diff --git a/tests/quick/eio1/ref/alpha/eio/detailed/stderr b/tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr
index 7ded22db8..7ded22db8 100644
--- a/tests/quick/eio1/ref/alpha/eio/detailed/stderr
+++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr
diff --git a/tests/quick/eio1/ref/alpha/eio/detailed/stdout b/tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout
index ee0eb672e..ee0eb672e 100644
--- a/tests/quick/eio1/ref/alpha/eio/detailed/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout
diff --git a/tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 4cbe1fce6..4cbe1fce6 100644
--- a/tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
diff --git a/tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
index 65a9f6f7f..65a9f6f7f 100644
--- a/tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
diff --git a/tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
index 29c0b91ac..29c0b91ac 100644
--- a/tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
diff --git a/tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr
index 4e444fa6b..4e444fa6b 100644
--- a/tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr
diff --git a/tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
index 80b37e259..80b37e259 100644
--- a/tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
diff --git a/tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index c4c381b93..c4c381b93 100644
--- a/tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
diff --git a/tests/quick/eio1/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
index 882db9c06..882db9c06 100644
--- a/tests/quick/eio1/ref/alpha/eio/simple-timing/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
diff --git a/tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index 5f7766bac..5f7766bac 100644
--- a/tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
diff --git a/tests/quick/eio1/ref/alpha/eio/simple-timing/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
index 4e444fa6b..4e444fa6b 100644
--- a/tests/quick/eio1/ref/alpha/eio/simple-timing/stderr
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
diff --git a/tests/quick/eio1/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index c14f4a3c9..c14f4a3c9 100644
--- a/tests/quick/eio1/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
diff --git a/tests/quick/20.eio-short/test.py b/tests/quick/20.eio-short/test.py
new file mode 100644
index 000000000..67e83d66e
--- /dev/null
+++ b/tests/quick/20.eio-short/test.py
@@ -0,0 +1,30 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+root.system.cpu.workload = EioProcess(file = binpath('anagram-vshort.eio.gz'))
+root.system.cpu.max_insts_any_thread = 500000
diff --git a/tests/quick/eio1/test.py b/tests/quick/eio1/test.py
deleted file mode 100644
index 40e1a4527..000000000
--- a/tests/quick/eio1/test.py
+++ /dev/null
@@ -1,2 +0,0 @@
-root.system.cpu.workload = EioProcess(file = tests_root + '/test-progs/anagram/bin/anagram-vshort.eio.gz')
-root.system.cpu.max_insts_any_thread = 500000
diff --git a/tests/run.py b/tests/run.py
index 0042b2b46..ae9d46258 100644
--- a/tests/run.py
+++ b/tests/run.py
@@ -33,12 +33,21 @@ import os, sys
# find path to directory containing this file
tests_root = os.path.dirname(__file__)
+test_progs = os.path.join(tests_root, 'test-progs')
+
+# generate path to binary file
+def binpath(app, file=None):
+ # executable has same name as app unless specified otherwise
+ if not file:
+ file = app
+ return os.path.join(test_progs, app, 'bin', isa, opsys, file)
# build configuration
execfile(os.path.join(tests_root, config + '.py'))
# set default maxtick... script can override
-maxtick = 1000000
+# -1 means run forever
+maxtick = -1
# tweak configuration for specific test
diff --git a/tests/simple-atomic.py b/tests/simple-atomic.py
index 78e87dc25..e3eb62ef0 100644
--- a/tests/simple-atomic.py
+++ b/tests/simple-atomic.py
@@ -7,8 +7,6 @@ system = System(cpu = AtomicSimpleCPU(),
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
-system.cpu.icache_port = system.membus.port
-system.cpu.dcache_port = system.membus.port
+system.cpu.connectMemPorts(system.membus)
root = Root(system = system)
-
diff --git a/tests/simple-timing.py b/tests/simple-timing.py
index 128cace3c..b3d11e069 100644
--- a/tests/simple-timing.py
+++ b/tests/simple-timing.py
@@ -11,11 +11,13 @@ class MyCache(BaseCache):
tgts_per_mshr = 5
cpu = TimingSimpleCPU()
-cpu.icache = MyCache(size = '128kB')
-cpu.dcache = MyCache(size = '256kB')
-cpu.l2cache = MyCache(size = '2MB')
+cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+ MyCache(size = '2MB'))
-cpu.icache_port = cpu.icache.cpu_side
-cpu.dcache_port = cpu.dcache.cpu_side
+system = System(cpu = cpu,
+ physmem = PhysicalMemory(),
+ membus = Bus())
+system.physmem.port = system.membus.port
+cpu.connectMemPorts(system.membus)
-root = makeSESystem(cpu)
+root = Root(system = system)
diff --git a/configs/test/hello b/tests/test-progs/hello/bin/alpha/linux/hello
index 59c0d195c..59c0d195c 100755
--- a/configs/test/hello
+++ b/tests/test-progs/hello/bin/alpha/linux/hello
Binary files differ
diff --git a/configs/test/hello_mips b/tests/test-progs/hello/bin/mips/linux/hello_mips
index a3db001ec..a3db001ec 100755
--- a/configs/test/hello_mips
+++ b/tests/test-progs/hello/bin/mips/linux/hello_mips
Binary files differ
diff --git a/configs/test/sparc_tests/hello_sparc b/tests/test-progs/hello/bin/sparc/bin
index e254ae33f..e254ae33f 100755
--- a/configs/test/sparc_tests/hello_sparc
+++ b/tests/test-progs/hello/bin/sparc/bin
Binary files differ