diff options
58 files changed, 307 insertions, 305 deletions
diff --git a/src/arch/alpha/process.hh b/src/arch/alpha/process.hh index cd45871b1..fcaa6539c 100644 --- a/src/arch/alpha/process.hh +++ b/src/arch/alpha/process.hh @@ -43,16 +43,17 @@ class AlphaLiveProcess : public LiveProcess AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile); void loadState(CheckpointIn &cp) override; - void initState(); + void initState() override; void argsInit(int intSize, int pageSize); public: - AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i); + AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override; /// Explicitly import the otherwise hidden getSyscallArg using LiveProcess::getSyscallArg; - void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val); - void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); + void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) override; + void setSyscallReturn(ThreadContext *tc, + SyscallReturn return_value) override; }; /* No architectural page table defined for this ISA */ diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh index f8ca54506..d0be46135 100644 --- a/src/arch/alpha/system.hh +++ b/src/arch/alpha/system.hh @@ -55,7 +55,7 @@ class AlphaSystem : public System /** * Initialise the state of the system. */ - virtual void initState(); + void initState() override; /** * Serialization stuff @@ -65,7 +65,7 @@ class AlphaSystem : public System /** Override startup() to provide a path to call setupFuncEvents() */ - virtual void startup(); + void startup() override; /** * Set the m5AlphaAccess pointer in the console @@ -121,7 +121,7 @@ class AlphaSystem : public System return addFuncEvent<T>(consoleSymtab, lbl); } - virtual Addr fixFuncEventAddr(Addr addr); + Addr fixFuncEventAddr(Addr addr) override; public: void setIntrFreq(Tick freq) { intrFreq = freq; } diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index a8bdf30e1..b9b6228e2 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -85,21 +85,21 @@ class TLB : public BaseTLB TLB(const Params *p); virtual ~TLB(); - void takeOverFrom(BaseTLB *otlb) {} + void takeOverFrom(BaseTLB *otlb) override {} - virtual void regStats(); + void regStats() override; int getsize() const { return table.size(); } TlbEntry &index(bool advance = true); void insert(Addr vaddr, TlbEntry &entry); - void flushAll(); + void flushAll() override; void flushProcesses(); void flushAddr(Addr addr, uint8_t asn); void - demapPage(Addr vaddr, uint64_t asn) + demapPage(Addr vaddr, uint64_t asn) override { assert(asn < (1 << 8)); flushAddr(vaddr, asn); diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 8af70075d..b960c320b 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -884,7 +884,7 @@ class TableWalker : public MemObject return dynamic_cast<const Params *>(_params); } - virtual void init(); + void init() override; bool haveLPAE() const { return _haveLPAE; } bool haveVirtualization() const { return _haveVirtualization; } @@ -892,12 +892,12 @@ class TableWalker : public MemObject /** Checks if all state is cleared and if so, completes drain */ void completeDrain(); DrainState drain() override; - virtual void drainResume() override; + void drainResume() override; - virtual BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + BaseMasterPort& getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID) override; - void regStats(); + void regStats() override; Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid, bool _isHyp, TLB::Mode mode, TLB::Translation *_trans, diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index f6776b0a9..1f9ec01ec 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -155,10 +155,10 @@ class TLB : public BaseTLB virtual ~TLB(); - void takeOverFrom(BaseTLB *otlb); + void takeOverFrom(BaseTLB *otlb) override; /// setup all the back pointers - virtual void init(); + void init() override; TableWalker *getTableWalker() { return tableWalker; } @@ -197,7 +197,7 @@ class TLB : public BaseTLB /** Reset the entire TLB. Used for CPU switching to prevent stale * translations after multiple switches */ - void flushAll() + void flushAll() override { flushAllSecurity(false, 0, true); flushAllSecurity(true, 0, true); @@ -230,14 +230,12 @@ class TLB : public BaseTLB void printTlb() const; - void demapPage(Addr vaddr, uint64_t asn) + void demapPage(Addr vaddr, uint64_t asn) override { // needed for x86 only panic("demapPage() is not implemented.\n"); } - static bool validVirtualAddress(Addr vaddr); - /** * Do a functional lookup on the TLB (for debugging) * and don't modify any internal state @@ -290,7 +288,7 @@ class TLB : public BaseTLB void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; - void regStats(); + void regStats() override; void regProbePoints() override; @@ -304,7 +302,7 @@ class TLB : public BaseTLB * * @return A pointer to the walker master port */ - virtual BaseMasterPort* getMasterPort(); + BaseMasterPort* getMasterPort() override; // Caching misc register values here. // Writing to misc registers needs to invalidate them. diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh index 0a7e78151..995fbfff4 100644 --- a/src/arch/generic/tlb.hh +++ b/src/arch/generic/tlb.hh @@ -123,7 +123,7 @@ class GenericTLB : public BaseTLB {} public: - void demapPage(Addr vaddr, uint64_t asn); + void demapPage(Addr vaddr, uint64_t asn) override; Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); void translateTiming(RequestPtr req, ThreadContext *tc, diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 554c4d754..87f27acca 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -189,7 +189,7 @@ class BaseCPU : public MemObject * @return a reference to the port with the given name */ BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; /** Get cpu task id */ uint32_t taskId() const { return _taskId; } @@ -303,9 +303,9 @@ class BaseCPU : public MemObject BaseCPU(Params *params, bool is_checker = false); virtual ~BaseCPU(); - virtual void init(); - virtual void startup(); - virtual void regStats(); + void init() override; + void startup() override; + void regStats() override; void regProbePoints() override; diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 14c0ad0b2..c77f964c0 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -98,7 +98,7 @@ class CheckerCPU : public BaseCPU, public ExecContext /** id attached to all issued requests */ MasterID masterId; public: - virtual void init(); + void init() override; typedef CheckerCPUParams Params; CheckerCPU(Params *p); @@ -110,7 +110,7 @@ class CheckerCPU : public BaseCPU, public ExecContext void setDcachePort(MasterPort *dcache_port); - MasterPort &getDataPort() + MasterPort &getDataPort() override { // the checker does not have ports on its own so return the // data port of the actual CPU core @@ -118,7 +118,7 @@ class CheckerCPU : public BaseCPU, public ExecContext return *dcachePort; } - MasterPort &getInstPort() + MasterPort &getInstPort() override { // the checker does not have ports on its own so return the // data port of the actual CPU core @@ -175,12 +175,12 @@ class CheckerCPU : public BaseCPU, public ExecContext TheISA::TLB* getITBPtr() { return itb; } TheISA::TLB* getDTBPtr() { return dtb; } - virtual Counter totalInsts() const + virtual Counter totalInsts() const override { return 0; } - virtual Counter totalOps() const + virtual Counter totalOps() const override { return 0; } @@ -194,8 +194,10 @@ class CheckerCPU : public BaseCPU, public ExecContext // These functions are only used in CPU models that split // effective address computation from the actual memory access. - void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } - Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); } + void setEA(Addr EA) override + { panic("CheckerCPU::setEA() not implemented\n"); } + Addr getEA() const override + { panic("CheckerCPU::getEA() not implemented\n"); } // The register accessor methods provide the index of the // instruction's operand (e.g., 0 or 1), not the architectural @@ -208,24 +210,25 @@ class CheckerCPU : public BaseCPU, public ExecContext // storage (which is pretty hard to imagine they would have reason // to do). - IntReg readIntRegOperand(const StaticInst *si, int idx) + IntReg readIntRegOperand(const StaticInst *si, int idx) override { return thread->readIntReg(si->srcRegIdx(idx)); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) override { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; return thread->readFloatReg(reg_idx); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, + int idx) override { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; return thread->readFloatRegBits(reg_idx); } - CCReg readCCRegOperand(const StaticInst *si, int idx) + CCReg readCCRegOperand(const StaticInst *si, int idx) override { int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; return thread->readCCReg(reg_idx); @@ -239,13 +242,15 @@ class CheckerCPU : public BaseCPU, public ExecContext result.push(instRes); } - void setIntRegOperand(const StaticInst *si, int idx, IntReg val) + void setIntRegOperand(const StaticInst *si, int idx, + IntReg val) override { thread->setIntReg(si->destRegIdx(idx), val); setResult<uint64_t>(val); } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, + FloatReg val) override { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; thread->setFloatReg(reg_idx, val); @@ -253,28 +258,28 @@ class CheckerCPU : public BaseCPU, public ExecContext } void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val) + FloatRegBits val) override { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; thread->setFloatRegBits(reg_idx, val); setResult<uint64_t>(val); } - void setCCRegOperand(const StaticInst *si, int idx, CCReg val) + void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override { int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; thread->setCCReg(reg_idx, val); setResult<uint64_t>(val); } - bool readPredicate() { return thread->readPredicate(); } - void setPredicate(bool val) + bool readPredicate() override { return thread->readPredicate(); } + void setPredicate(bool val) override { thread->setPredicate(val); } - TheISA::PCState pcState() const { return thread->pcState(); } - void pcState(const TheISA::PCState &val) + TheISA::PCState pcState() const override { return thread->pcState(); } + void pcState(const TheISA::PCState &val) override { DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", val, thread->pcState()); @@ -290,7 +295,7 @@ class CheckerCPU : public BaseCPU, public ExecContext return thread->readMiscRegNoEffect(misc_reg); } - MiscReg readMiscReg(int misc_reg) + MiscReg readMiscReg(int misc_reg) override { return thread->readMiscReg(misc_reg); } @@ -302,21 +307,21 @@ class CheckerCPU : public BaseCPU, public ExecContext return thread->setMiscRegNoEffect(misc_reg, val); } - void setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) override { DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); miscRegIdxs.push(misc_reg); return thread->setMiscReg(misc_reg, val); } - MiscReg readMiscRegOperand(const StaticInst *si, int idx) + MiscReg readMiscRegOperand(const StaticInst *si, int idx) override { int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; return thread->readMiscReg(reg_idx); } - void setMiscRegOperand( - const StaticInst *si, int idx, const MiscReg &val) + void setMiscRegOperand(const StaticInst *si, int idx, + const MiscReg &val) override { int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; return this->setMiscReg(reg_idx, val); @@ -343,18 +348,20 @@ class CheckerCPU : public BaseCPU, public ExecContext newPCState = val; } - void demapPage(Addr vaddr, uint64_t asn) + void demapPage(Addr vaddr, uint64_t asn) override { this->itb->demapPage(vaddr, asn); this->dtb->demapPage(vaddr, asn); } // monitor/mwait funtions - virtual void armMonitor(Addr address) { BaseCPU::armMonitor(0, address); } - bool mwait(PacketPtr pkt) { return BaseCPU::mwait(0, pkt); } - void mwaitAtomic(ThreadContext *tc) + void armMonitor(Addr address) override + { BaseCPU::armMonitor(0, address); } + bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } + void mwaitAtomic(ThreadContext *tc) override { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } - AddressMonitor *getAddrMonitor() { return BaseCPU::getCpuAddrMonitor(0); } + AddressMonitor *getAddrMonitor() override + { return BaseCPU::getCpuAddrMonitor(0); } void demapInstPage(Addr vaddr, uint64_t asn) { @@ -366,24 +373,26 @@ class CheckerCPU : public BaseCPU, public ExecContext this->dtb->demapPage(vaddr, asn); } - Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); + Fault readMem(Addr addr, uint8_t *data, unsigned size, + unsigned flags) override; Fault writeMem(uint8_t *data, unsigned size, - Addr addr, unsigned flags, uint64_t *res); + Addr addr, unsigned flags, uint64_t *res) override; - unsigned int readStCondFailures() const { + unsigned int readStCondFailures() const override { return thread->readStCondFailures(); } - void setStCondFailures(unsigned int sc_failures) + void setStCondFailures(unsigned int sc_failures) override {} ///////////////////////////////////////////////////// - Fault hwrei() { return thread->hwrei(); } - bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } + Fault hwrei() override { return thread->hwrei(); } + bool simPalCheck(int palFunc) override + { return thread->simPalCheck(palFunc); } void wakeup(ThreadID tid) override { } // Assume that the normal CPU's call to syscall was successful. // The checker's state would have already been updated by the syscall. - void syscall(int64_t callnum) { } + void syscall(int64_t callnum) override { } void handleError() { @@ -396,7 +405,7 @@ class CheckerCPU : public BaseCPU, public ExecContext void dumpAndExit(); - ThreadContext *tcBase() { return tc; } + ThreadContext *tcBase() override { return tc; } SimpleThread *threadBase() { return thread; } Result unverifiedResult; diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh index 5bfc3b29f..82dac6aa9 100644 --- a/src/cpu/minor/cpu.hh +++ b/src/cpu/minor/cpu.hh @@ -114,10 +114,10 @@ class MinorCPU : public BaseCPU protected: /** Return a reference to the data port. */ - MasterPort &getDataPort(); + MasterPort &getDataPort() override; /** Return a reference to the instruction port. */ - MasterPort &getInstPort(); + MasterPort &getInstPort() override; public: MinorCPU(MinorCPUParams *params); @@ -126,8 +126,8 @@ class MinorCPU : public BaseCPU public: /** Starting, waking and initialisation */ - void init(); - void startup(); + void init() override; + void startup() override; void wakeup(ThreadID tid) override; Addr dbg_vtophys(Addr addr); @@ -136,18 +136,18 @@ class MinorCPU : public BaseCPU Minor::MinorStats stats; /** Stats interface from SimObject (by way of BaseCPU) */ - void regStats(); + void regStats() override; /** Simple inst count interface from BaseCPU */ - Counter totalInsts() const; - Counter totalOps() const; + Counter totalInsts() const override; + Counter totalOps() const override; void serializeThread(CheckpointOut &cp, ThreadID tid) const override; void unserializeThread(CheckpointIn &cp, ThreadID tid) override; /** Serialize pipeline data */ - void serialize(CheckpointOut &cp) const; - void unserialize(CheckpointIn &cp); + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** Drain interface */ DrainState drain() override; @@ -155,15 +155,15 @@ class MinorCPU : public BaseCPU /** Signal from Pipeline that MinorCPU should signal that a drain * is complete and set its drainState */ void signalDrainDone(); - void memWriteback(); + void memWriteback() override; /** Switching interface from BaseCPU */ - void switchOut(); - void takeOverFrom(BaseCPU *old_cpu); + void switchOut() override; + void takeOverFrom(BaseCPU *old_cpu) override; /** Thread activation interface from BaseCPU. */ - void activateContext(ThreadID thread_id); - void suspendContext(ThreadID thread_id); + void activateContext(ThreadID thread_id) override; + void suspendContext(ThreadID thread_id) override; /** Interface for stages to signal that they have become active after * a callback or eventq event where the pipeline itself may have diff --git a/src/cpu/minor/func_unit.cc b/src/cpu/minor/func_unit.cc index 65dd1eefc..aeee5cc44 100644 --- a/src/cpu/minor/func_unit.cc +++ b/src/cpu/minor/func_unit.cc @@ -223,7 +223,7 @@ FUPipeline::findTiming(const StaticInstPtr &inst) "Found extra timing match (pattern %d '%s')" " %s %16x (type %s)\n", i, timing.description, inst->disassemble(0), mach_inst, - typeid(*inst).name()); + typeid(inst).name()); return &timing; } diff --git a/src/cpu/minor/pipeline.hh b/src/cpu/minor/pipeline.hh index 213def58e..2e1aa9921 100644 --- a/src/cpu/minor/pipeline.hh +++ b/src/cpu/minor/pipeline.hh @@ -124,7 +124,7 @@ class Pipeline : public Ticked /** A custom evaluate allows report in the right place (between * stages and pipeline advance) */ - void evaluate(); + void evaluate() override; void countCycles(Cycles delta) override { diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index bed61234a..09177d404 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -265,13 +265,13 @@ class FullO3CPU : public BaseO3CPU ~FullO3CPU(); /** Registers statistics. */ - void regStats(); + void regStats() override; ProbePointArg<PacketPtr> *ppInstAccessComplete; ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; /** Register probe points. */ - void regProbePoints(); + void regProbePoints() override; void demapPage(Addr vaddr, uint64_t asn) { @@ -295,9 +295,9 @@ class FullO3CPU : public BaseO3CPU void tick(); /** Initialize the CPU */ - void init(); + void init() override; - void startup(); + void startup() override; /** Returns the Number of Active Threads in the CPU */ int numActiveThreads() @@ -316,21 +316,21 @@ class FullO3CPU : public BaseO3CPU void removeThread(ThreadID tid); /** Count the Total Instructions Committed in the CPU. */ - virtual Counter totalInsts() const; + Counter totalInsts() const override; /** Count the Total Ops (including micro ops) committed in the CPU. */ - virtual Counter totalOps() const; + Counter totalOps() const override; /** Add Thread to Active Threads List. */ - void activateContext(ThreadID tid); + void activateContext(ThreadID tid) override; /** Remove Thread from Active Threads List */ - void suspendContext(ThreadID tid); + void suspendContext(ThreadID tid) override; /** Remove Thread from Active Threads List && * Remove Thread Context from CPU. */ - void haltContext(ThreadID tid); + void haltContext(ThreadID tid) override; /** Update The Order In Which We Process Threads. */ void updateThreadPriority(); @@ -364,12 +364,12 @@ class FullO3CPU : public BaseO3CPU void commitDrained(ThreadID tid); /** Switches out this CPU. */ - virtual void switchOut(); + void switchOut() override; /** Takes over from another CPU. */ - virtual void takeOverFrom(BaseCPU *oldCPU); + void takeOverFrom(BaseCPU *oldCPU) override; - void verifyMemoryMode() const; + void verifyMemoryMode() const override; /** Get the current instruction sequence number, and increment it. */ InstSeqNum getAndIncrementInstSeq() @@ -392,12 +392,6 @@ class FullO3CPU : public BaseO3CPU /** Halts the CPU. */ void halt() { panic("Halt not implemented!\n"); } - /** Check if this address is a valid instruction address. */ - bool validInstAddr(Addr addr) { return true; } - - /** Check if this address is a valid data address. */ - bool validDataAddr(Addr addr) { return true; } - /** Register accessors. Index refers to the physical register index. */ /** Reads a miscellaneous register. */ @@ -699,10 +693,10 @@ class FullO3CPU : public BaseO3CPU } /** Used by the fetch unit to get a hold of the instruction port. */ - virtual MasterPort &getInstPort() { return icachePort; } + MasterPort &getInstPort() override { return icachePort; } /** Get the dcache port (used to find block size for translations). */ - virtual MasterPort &getDataPort() { return dcachePort; } + MasterPort &getDataPort() override { return dcachePort; } /** Stat for total number of times the CPU is descheduled. */ Stats::Scalar timesIdled; diff --git a/src/cpu/pred/bpred_unit.hh b/src/cpu/pred/bpred_unit.hh index 1f26f1aac..bef8cb949 100644 --- a/src/cpu/pred/bpred_unit.hh +++ b/src/cpu/pred/bpred_unit.hh @@ -75,7 +75,7 @@ class BPredUnit : public SimObject /** * Registers statistics. */ - void regStats(); + void regStats() override; void regProbePoints() override; diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 372df7cbd..1a2f19949 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -55,7 +55,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU AtomicSimpleCPU(AtomicSimpleCPUParams *params); virtual ~AtomicSimpleCPU(); - virtual void init(); + void init() override; private: @@ -181,10 +181,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU protected: /** Return a reference to the data port. */ - virtual MasterPort &getDataPort() { return dcachePort; } + MasterPort &getDataPort() override { return dcachePort; } /** Return a reference to the instruction port. */ - virtual MasterPort &getInstPort() { return icachePort; } + MasterPort &getInstPort() override { return icachePort; } /** Perform snoop for other cpu-local thread contexts. */ void threadSnoop(PacketPtr pkt, ThreadID sender); @@ -194,20 +194,21 @@ class AtomicSimpleCPU : public BaseSimpleCPU DrainState drain() override; void drainResume() override; - void switchOut(); - void takeOverFrom(BaseCPU *oldCPU); + void switchOut() override; + void takeOverFrom(BaseCPU *oldCPU) override; - void verifyMemoryMode() const; + void verifyMemoryMode() const override; - virtual void activateContext(ThreadID thread_num); - virtual void suspendContext(ThreadID thread_num); + void activateContext(ThreadID thread_num) override; + void suspendContext(ThreadID thread_num) override; - Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); + Fault readMem(Addr addr, uint8_t *data, unsigned size, + unsigned flags) override; Fault writeMem(uint8_t *data, unsigned size, - Addr addr, unsigned flags, uint64_t *res); + Addr addr, unsigned flags, uint64_t *res) override; - virtual void regProbePoints(); + void regProbePoints() override; /** * Print state of address in memory system via PrintReq (for diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 72ac9bb4b..0ec9e502b 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -94,7 +94,7 @@ class BaseSimpleCPU : public BaseCPU BaseSimpleCPU(BaseSimpleCPUParams *params); virtual ~BaseSimpleCPU(); void wakeup(ThreadID tid) override; - virtual void init(); + void init() override; public: Trace::InstRecord *traceData; CheckerCPU *checker; @@ -134,13 +134,13 @@ class BaseSimpleCPU : public BaseCPU void postExecute(); void advancePC(const Fault &fault); - virtual void haltContext(ThreadID thread_num); + void haltContext(ThreadID thread_num) override; // statistics - virtual void regStats(); - virtual void resetStats(); + void regStats() override; + void resetStats() override; - virtual void startup(); + void startup() override; virtual Fault readMem(Addr addr, uint8_t* data, unsigned size, unsigned flags) = 0; @@ -149,8 +149,8 @@ class BaseSimpleCPU : public BaseCPU unsigned flags, uint64_t* res) = 0; void countInst(); - virtual Counter totalInsts() const; - virtual Counter totalOps() const; + Counter totalInsts() const override; + Counter totalOps() const override; void serializeThread(CheckpointOut &cp, ThreadID tid) const override; void unserializeThread(CheckpointIn &cp, ThreadID tid) override; diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index a6c7df988..36e01e9be 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -55,7 +55,7 @@ class TimingSimpleCPU : public BaseSimpleCPU TimingSimpleCPU(TimingSimpleCPUParams * params); virtual ~TimingSimpleCPU(); - virtual void init(); + void init() override; private: @@ -265,28 +265,29 @@ class TimingSimpleCPU : public BaseSimpleCPU protected: /** Return a reference to the data port. */ - virtual MasterPort &getDataPort() { return dcachePort; } + MasterPort &getDataPort() override { return dcachePort; } /** Return a reference to the instruction port. */ - virtual MasterPort &getInstPort() { return icachePort; } + MasterPort &getInstPort() override { return icachePort; } public: DrainState drain() override; void drainResume() override; - void switchOut(); - void takeOverFrom(BaseCPU *oldCPU); + void switchOut() override; + void takeOverFrom(BaseCPU *oldCPU) override; - void verifyMemoryMode() const; + void verifyMemoryMode() const override; - virtual void activateContext(ThreadID thread_num); - virtual void suspendContext(ThreadID thread_num); + void activateContext(ThreadID thread_num) override; + void suspendContext(ThreadID thread_num) override; - Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); + Fault readMem(Addr addr, uint8_t *data, unsigned size, + unsigned flags) override; Fault writeMem(uint8_t *data, unsigned size, - Addr addr, unsigned flags, uint64_t *res); + Addr addr, unsigned flags, uint64_t *res) override; void fetch(); void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc); diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh b/src/cpu/testers/traffic_gen/traffic_gen.hh index e5295bcf5..d57b613f3 100644 --- a/src/cpu/testers/traffic_gen/traffic_gen.hh +++ b/src/cpu/testers/traffic_gen/traffic_gen.hh @@ -192,12 +192,12 @@ class TrafficGen : public MemObject ~TrafficGen() {} - virtual BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + BaseMasterPort& getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID) override; - void init(); + void init() override; - void initState(); + void initState() override; DrainState drain() override; @@ -205,7 +205,7 @@ class TrafficGen : public MemObject void unserialize(CheckpointIn &cp) override; /** Register statistics */ - void regStats(); + void regStats() override; }; diff --git a/src/dev/alpha/backdoor.hh b/src/dev/alpha/backdoor.hh index 59d800863..7dd369aaf 100644 --- a/src/dev/alpha/backdoor.hh +++ b/src/dev/alpha/backdoor.hh @@ -107,13 +107,13 @@ class AlphaBackdoor : public BasicPioDevice return dynamic_cast<const Params *>(_params); } - virtual void startup(); + void startup() override; /** * memory mapped reads and writes */ - virtual Tick read(PacketPtr pkt); - virtual Tick write(PacketPtr pkt); + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; /** * standard serialization routines for checkpointing diff --git a/src/dev/alpha/tsunami.hh b/src/dev/alpha/tsunami.hh index 9972ecc95..c43f0e023 100644 --- a/src/dev/alpha/tsunami.hh +++ b/src/dev/alpha/tsunami.hh @@ -80,7 +80,7 @@ class Tsunami : public Platform int intr_sum_type[Tsunami::Max_CPUs]; int ipi_pending[Tsunami::Max_CPUs]; - void init(); + void init() override; public: typedef TsunamiParams Params; @@ -89,40 +89,40 @@ class Tsunami : public Platform /** * Cause the cpu to post a serial interrupt to the CPU. */ - virtual void postConsoleInt(); + void postConsoleInt() override; /** * Clear a posted CPU interrupt (id=55) */ - virtual void clearConsoleInt(); + void clearConsoleInt() override; /** * Cause the chipset to post a cpi interrupt to the CPU. */ - virtual void postPciInt(int line); + void postPciInt(int line) override; /** * Clear a posted PCI->CPU interrupt */ - virtual void clearPciInt(int line); + void clearPciInt(int line) override; - virtual Addr pciToDma(Addr pciAddr) const; + Addr pciToDma(Addr pciAddr) const override; /** * Calculate the configuration address given a bus/dev/func. */ - virtual Addr calcPciConfigAddr(int bus, int dev, int func); + Addr calcPciConfigAddr(int bus, int dev, int func) override; /** * Calculate the address for an IO location on the PCI bus. */ - virtual Addr calcPciIOAddr(Addr addr); + Addr calcPciIOAddr(Addr addr) override; /** * Calculate the address for a memory location on the PCI bus. */ - virtual Addr calcPciMemAddr(Addr addr); + Addr calcPciMemAddr(Addr addr) override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/dev/alpha/tsunami_cchip.hh b/src/dev/alpha/tsunami_cchip.hh index 45834f9ea..b6ddd49bd 100644 --- a/src/dev/alpha/tsunami_cchip.hh +++ b/src/dev/alpha/tsunami_cchip.hh @@ -92,9 +92,9 @@ class TsunamiCChip : public BasicPioDevice return dynamic_cast<const Params *>(_params); } - virtual Tick read(PacketPtr pkt); + Tick read(PacketPtr pkt) override; - virtual Tick write(PacketPtr pkt); + Tick write(PacketPtr pkt) override; /** * post an RTC interrupt to the CPU diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh index e1b05abe8..d7fac22e4 100644 --- a/src/dev/alpha/tsunami_io.hh +++ b/src/dev/alpha/tsunami_io.hh @@ -123,8 +123,8 @@ class TsunamiIO : public BasicPioDevice return dynamic_cast<const Params *>(_params); } - virtual Tick read(PacketPtr pkt); - virtual Tick write(PacketPtr pkt); + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; /** * Post an PIC interrupt to the CPU via the CChip @@ -144,7 +144,7 @@ class TsunamiIO : public BasicPioDevice /** * Start running. */ - virtual void startup(); + void startup() override; }; diff --git a/src/dev/alpha/tsunami_pchip.hh b/src/dev/alpha/tsunami_pchip.hh index e37292d57..68bd20e9a 100644 --- a/src/dev/alpha/tsunami_pchip.hh +++ b/src/dev/alpha/tsunami_pchip.hh @@ -86,8 +86,8 @@ class TsunamiPChip : public BasicPioDevice Addr calcIOAddr(Addr addr); Addr calcMemAddr(Addr addr); - virtual Tick read(PacketPtr pkt); - virtual Tick write(PacketPtr pkt); + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/dev/copy_engine.hh b/src/dev/copy_engine.hh index b33d1145d..797311be5 100644 --- a/src/dev/copy_engine.hh +++ b/src/dev/copy_engine.hh @@ -196,13 +196,13 @@ class CopyEngine : public PciDevice CopyEngine(const Params *params); ~CopyEngine(); - void regStats(); + void regStats() override; - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID) override; - virtual Tick read(PacketPtr pkt); - virtual Tick write(PacketPtr pkt); + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/dev/disk_image.hh b/src/dev/disk_image.hh index 01e32440d..fa25fc770 100644 --- a/src/dev/disk_image.hh +++ b/src/dev/disk_image.hh @@ -132,10 +132,10 @@ class CowDiskImage : public DiskImage void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; - virtual std::streampos size() const; + std::streampos size() const override; - virtual std::streampos read(uint8_t *data, std::streampos offset) const; - virtual std::streampos write(const uint8_t *data, std::streampos offset); + std::streampos read(uint8_t *data, std::streampos offset) const override; + std::streampos write(const uint8_t *data, std::streampos offset) override; }; void SafeRead(std::ifstream &stream, void *data, int count); diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh index 273b21e2b..782fe4648 100644 --- a/src/dev/dma_device.hh +++ b/src/dev/dma_device.hh @@ -134,8 +134,8 @@ class DmaPort : public MasterPort, public Drainable protected: - bool recvTimingResp(PacketPtr pkt); - void recvReqRetry() ; + bool recvTimingResp(PacketPtr pkt) override; + void recvReqRetry() override; void queueDma(PacketPtr pkt); @@ -175,12 +175,12 @@ class DmaDevice : public PioDevice bool dmaPending() const { return dmaPort.dmaPending(); } - virtual void init(); + void init() override; unsigned int cacheBlockSize() const { return sys->cacheLineSize(); } - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID) override; }; diff --git a/src/dev/etherlink.hh b/src/dev/etherlink.hh index 0012d0003..9d2a5fdf2 100644 --- a/src/dev/etherlink.hh +++ b/src/dev/etherlink.hh @@ -156,7 +156,7 @@ class EtherLink : public EtherObject return dynamic_cast<const Params *>(_params); } - virtual EtherInt *getEthPort(const std::string &if_name, int idx); + EtherInt *getEthPort(const std::string &if_name, int idx) override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/dev/ethertap.hh b/src/dev/ethertap.hh index b1fa08559..5755032a9 100644 --- a/src/dev/ethertap.hh +++ b/src/dev/ethertap.hh @@ -110,7 +110,7 @@ class EtherTap : public EtherObject return dynamic_cast<const Params *>(_params); } - virtual EtherInt *getEthPort(const std::string &if_name, int idx); + EtherInt *getEthPort(const std::string &if_name, int idx) override; virtual bool recvPacket(EthPacketPtr packet); virtual void sendDone(); diff --git a/src/dev/i2cbus.hh b/src/dev/i2cbus.hh index 2fe8052fd..7212a59fd 100644 --- a/src/dev/i2cbus.hh +++ b/src/dev/i2cbus.hh @@ -143,8 +143,8 @@ class I2CBus : public BasicPioDevice I2CBus(const I2CBusParams* p); - virtual Tick read(PacketPtr pkt); - virtual Tick write(PacketPtr pkt); + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh index 5b2d60916..f1802ab24 100644 --- a/src/dev/i8254xGBe.hh +++ b/src/dev/i8254xGBe.hh @@ -342,13 +342,13 @@ class IGbE : public EtherDevice class RxDescCache : public DescCache<iGbReg::RxDesc> { protected: - virtual Addr descBase() const { return igbe->regs.rdba(); } - virtual long descHead() const { return igbe->regs.rdh(); } - virtual long descLen() const { return igbe->regs.rdlen() >> 4; } - virtual long descTail() const { return igbe->regs.rdt(); } - virtual void updateHead(long h) { igbe->regs.rdh(h); } - virtual void enableSm(); - virtual void fetchAfterWb() { + Addr descBase() const override { return igbe->regs.rdba(); } + long descHead() const override { return igbe->regs.rdh(); } + long descLen() const override { return igbe->regs.rdlen() >> 4; } + long descTail() const override { return igbe->regs.rdt(); } + void updateHead(long h) override { igbe->regs.rdh(h); } + void enableSm() override; + void fetchAfterWb() override { if (!igbe->rxTick && igbe->drainState() == DrainState::Running) fetchDescriptors(); } @@ -391,7 +391,7 @@ class IGbE : public EtherDevice EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent; EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent; - virtual bool hasOutstandingEvents(); + bool hasOutstandingEvents() override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; @@ -403,14 +403,14 @@ class IGbE : public EtherDevice class TxDescCache : public DescCache<iGbReg::TxDesc> { protected: - virtual Addr descBase() const { return igbe->regs.tdba(); } - virtual long descHead() const { return igbe->regs.tdh(); } - virtual long descTail() const { return igbe->regs.tdt(); } - virtual long descLen() const { return igbe->regs.tdlen() >> 4; } - virtual void updateHead(long h) { igbe->regs.tdh(h); } - virtual void enableSm(); - virtual void actionAfterWb(); - virtual void fetchAfterWb() { + Addr descBase() const override { return igbe->regs.tdba(); } + long descHead() const override { return igbe->regs.tdh(); } + long descTail() const override { return igbe->regs.tdt(); } + long descLen() const override { return igbe->regs.tdlen() >> 4; } + void updateHead(long h) override { igbe->regs.tdh(h); } + void enableSm() override; + void actionAfterWb() override; + void fetchAfterWb() override { if (!igbe->txTick && igbe->drainState() == DrainState::Running) fetchDescriptors(); } @@ -497,7 +497,7 @@ class IGbE : public EtherDevice completionEnabled = enabled; } - virtual bool hasOutstandingEvents(); + bool hasOutstandingEvents() override; void nullCallback() { DPRINTF(EthernetDesc, "Completion writeback complete\n"); @@ -521,16 +521,16 @@ class IGbE : public EtherDevice IGbE(const Params *params); ~IGbE(); - virtual void init(); + void init() override; - virtual EtherInt *getEthPort(const std::string &if_name, int idx); + EtherInt *getEthPort(const std::string &if_name, int idx) override; Tick lastInterrupt; - virtual Tick read(PacketPtr pkt); - virtual Tick write(PacketPtr pkt); + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; - virtual Tick writeConfig(PacketPtr pkt); + Tick writeConfig(PacketPtr pkt) override; bool ethRxPkt(EthPacketPtr packet); void ethTxDone(); diff --git a/src/dev/ide_ctrl.hh b/src/dev/ide_ctrl.hh index 398cab299..0afa60e4a 100644 --- a/src/dev/ide_ctrl.hh +++ b/src/dev/ide_ctrl.hh @@ -146,13 +146,13 @@ class IdeController : public PciDevice void intrPost(); - Tick writeConfig(PacketPtr pkt); - Tick readConfig(PacketPtr pkt); + Tick writeConfig(PacketPtr pkt) override; + Tick readConfig(PacketPtr pkt) override; void setDmaComplete(IdeDisk *disk); - Tick read(PacketPtr pkt); - Tick write(PacketPtr pkt); + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/dev/ide_disk.hh b/src/dev/ide_disk.hh index e1ea7a27d..45b0dd149 100644 --- a/src/dev/ide_disk.hh +++ b/src/dev/ide_disk.hh @@ -276,7 +276,7 @@ class IdeDisk : public SimObject /** * Register Statistics */ - void regStats(); + void regStats() override; /** * Set the controller for this device diff --git a/src/dev/ns_gige.hh b/src/dev/ns_gige.hh index 0e6c1bd31..33a76ab62 100644 --- a/src/dev/ns_gige.hh +++ b/src/dev/ns_gige.hh @@ -353,12 +353,12 @@ class NSGigE : public EtherDevBase NSGigE(Params *params); ~NSGigE(); - virtual EtherInt *getEthPort(const std::string &if_name, int idx); + EtherInt *getEthPort(const std::string &if_name, int idx) override; - virtual Tick writeConfig(PacketPtr pkt); + Tick writeConfig(PacketPtr pkt) override; - virtual Tick read(PacketPtr pkt); - virtual Tick write(PacketPtr pkt); + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; bool cpuIntrPending() const; void cpuIntrAck() { cpuIntrClear(); } diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh index 2064de90e..284b64f09 100644 --- a/src/dev/pcidev.hh +++ b/src/dev/pcidev.hh @@ -76,9 +76,9 @@ class PciDevice : public DmaDevice protected: PciDevice *device; - virtual Tick recvAtomic(PacketPtr pkt); + Tick recvAtomic(PacketPtr pkt) override; - virtual AddrRangeList getAddrRanges() const; + AddrRangeList getAddrRanges() const override; Platform *platform; @@ -234,7 +234,7 @@ class PciDevice : public DmaDevice * * @return a list of non-overlapping address ranges */ - AddrRangeList getAddrRanges() const; + AddrRangeList getAddrRanges() const override; /** * Constructor for PCI Dev. This function copies data from the @@ -243,7 +243,7 @@ class PciDevice : public DmaDevice */ PciDevice(const Params *params); - virtual void init(); + void init() override; /** * Serialize this object to the given output stream. @@ -259,8 +259,8 @@ class PciDevice : public DmaDevice void unserialize(CheckpointIn &cp) override; - virtual BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) + BaseSlavePort &getSlavePort(const std::string &if_name, + PortID idx = InvalidPortID) override { if (if_name == "config") { return configPort; diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh index 96727b0ca..7dfc8b204 100644 --- a/src/dev/sinic.hh +++ b/src/dev/sinic.hh @@ -238,7 +238,7 @@ class Device : public Base public: bool recvPacket(EthPacketPtr packet); void transferDone(); - virtual EtherInt *getEthPort(const std::string &if_name, int idx); + EtherInt *getEthPort(const std::string &if_name, int idx) override; /** * DMA parameters @@ -269,8 +269,8 @@ class Device : public Base * Memory Interface */ public: - virtual Tick read(PacketPtr pkt); - virtual Tick write(PacketPtr pkt); + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; virtual void drainResume() override; void prepareIO(ContextID cpu, int index); @@ -290,8 +290,8 @@ class Device : public Base int _maxVnicDistance; public: - virtual void regStats(); - virtual void resetStats(); + void regStats() override; + void resetStats() override; /** * Serialization stuff diff --git a/src/dev/uart8250.hh b/src/dev/uart8250.hh index 367d57f73..ccccac1e9 100644 --- a/src/dev/uart8250.hh +++ b/src/dev/uart8250.hh @@ -97,14 +97,14 @@ class Uart8250 : public Uart } Uart8250(const Params *p); - virtual Tick read(PacketPtr pkt); - virtual Tick write(PacketPtr pkt); - virtual AddrRangeList getAddrRanges() const; + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; + AddrRangeList getAddrRanges() const override; /** * Inform the uart that there is data available. */ - virtual void dataAvailable(); + void dataAvailable() override; /** diff --git a/src/dev/virtio/fs9p.hh b/src/dev/virtio/fs9p.hh index 9fb53dd2d..ebff9fef7 100644 --- a/src/dev/virtio/fs9p.hh +++ b/src/dev/virtio/fs9p.hh @@ -220,7 +220,8 @@ class VirtIO9PProxy : public VirtIO9PBase void unserialize(CheckpointIn &cp) override; protected: - void recvTMsg(const P9MsgHeader &header, const uint8_t *data, size_t size); + void recvTMsg(const P9MsgHeader &header, const uint8_t *data, + size_t size) override; /** Notification of pending data from server */ void serverDataReady(); diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh index 6dbc79ea0..8ab28770d 100644 --- a/src/mem/abstract_mem.hh +++ b/src/mem/abstract_mem.hh @@ -197,7 +197,7 @@ class AbstractMemory : public MemObject /** * Initialise this memory. */ - void init(); + void init() override; /** * See if this is a null memory that should never store data and @@ -304,7 +304,7 @@ class AbstractMemory : public MemObject /** * Register Statistics */ - virtual void regStats(); + void regStats() override; }; diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 0ee0696d8..ec436201b 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -334,9 +334,9 @@ class Cache : public BaseCache PacketPtr cleanEvictBlk(CacheBlk *blk); - void memWriteback(); - void memInvalidate(); - bool isDirty() const; + void memWriteback() override; + void memInvalidate() override; + bool isDirty() const override; /** * Cache block visitor that writes back dirty cache blocks using @@ -410,11 +410,11 @@ class Cache : public BaseCache return tags->findBlock(addr, is_secure); } - bool inCache(Addr addr, bool is_secure) const { + bool inCache(Addr addr, bool is_secure) const override { return (tags->findBlock(addr, is_secure) != 0); } - bool inMissQueue(Addr addr, bool is_secure) const { + bool inMissQueue(Addr addr, bool is_secure) const override { return (mshrQueue.findMatch(addr, is_secure) != 0); } @@ -430,7 +430,7 @@ class Cache : public BaseCache /** Non-default destructor is needed to deallocate memory. */ virtual ~Cache(); - void regStats(); + void regStats() override; /** serialize the state of the caches * We currently don't support checkpointing cache state, so this panics. diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh index e415603d9..910d44b36 100644 --- a/src/mem/cache/tags/base_set_assoc.hh +++ b/src/mem/cache/tags/base_set_assoc.hh @@ -152,7 +152,7 @@ public: * @return The number of sets. */ unsigned - getNumSets() const + getNumSets() const override { return numSets; } @@ -162,7 +162,7 @@ public: * @return The number of ways. */ unsigned - getNumWays() const + getNumWays() const override { return assoc; } @@ -173,13 +173,13 @@ public: * @param way The way of the block. * @return The cache block. */ - CacheBlk *findBlockBySetAndWay(int set, int way) const; + CacheBlk *findBlockBySetAndWay(int set, int way) const override; /** * Invalidate the given block. * @param blk The block to invalidate. */ - void invalidate(CacheBlk *blk) + void invalidate(CacheBlk *blk) override { assert(blk); assert(blk->isValid()); @@ -203,7 +203,7 @@ public: * @return Pointer to the cache block if found. */ CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, - int context_src) + int context_src) override { Addr tag = extractTag(addr); int set = extractSet(addr); @@ -242,7 +242,7 @@ public: * @param asid The address space ID. * @return Pointer to the cache block if found. */ - CacheBlk* findBlock(Addr addr, bool is_secure) const; + CacheBlk* findBlock(Addr addr, bool is_secure) const override; /** * Find an invalid block to evict for the address provided. @@ -251,7 +251,7 @@ public: * @param addr The addr to a find a replacement candidate for. * @return The candidate block. */ - CacheBlk* findVictim(Addr addr) + CacheBlk* findVictim(Addr addr) override { BlkType *blk = NULL; int set = extractSet(addr); @@ -271,7 +271,7 @@ public: * @param pkt Packet holding the address to update * @param blk The block to update. */ - void insertBlock(PacketPtr pkt, CacheBlk *blk) + void insertBlock(PacketPtr pkt, CacheBlk *blk) override { Addr addr = pkt->getAddr(); MasterID master_id = pkt->req->masterId(); @@ -324,7 +324,7 @@ public: * Limit the allocation for the cache ways. * @param ways The maximum number of ways available for replacement. */ - virtual void setWayAllocationMax(int ways) + virtual void setWayAllocationMax(int ways) override { fatal_if(ways < 1, "Allocation limit must be greater than zero"); allocAssoc = ways; @@ -334,7 +334,7 @@ public: * Get the way allocation mask limit. * @return The maximum number of ways available for replacement. */ - virtual int getWayAllocationMax() const + virtual int getWayAllocationMax() const override { return allocAssoc; } @@ -344,7 +344,7 @@ public: * @param addr The address to get the tag from. * @return The tag of the address. */ - Addr extractTag(Addr addr) const + Addr extractTag(Addr addr) const override { return (addr >> tagShift); } @@ -354,7 +354,7 @@ public: * @param addr The address to get the set from. * @return The set index of the address. */ - int extractSet(Addr addr) const + int extractSet(Addr addr) const override { return ((addr >> setShift) & setMask); } @@ -375,7 +375,7 @@ public: * @param set The set of the block. * @return The block address. */ - Addr regenerateBlkAddr(Addr tag, unsigned set) const + Addr regenerateBlkAddr(Addr tag, unsigned set) const override { return ((tag << tagShift) | ((Addr)set << setShift)); } @@ -383,17 +383,17 @@ public: /** * Called at end of simulation to complete average block reference stats. */ - virtual void cleanupRefs(); + void cleanupRefs() override; /** * Print all tags used */ - virtual std::string print() const; + std::string print() const override; /** * Called prior to dumping stats to compute task occupancy */ - virtual void computeStats(); + void computeStats() override; /** * Visit each block in the tag store and apply a visitor to the diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 1728ee48a..2c34be08f 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -168,13 +168,13 @@ public: * Register the stats for this object. * @param name The name to prepend to the stats name. */ - void regStats(); + void regStats() override; /** * Invalidate a cache block. * @param blk The block to invalidate. */ - void invalidate(CacheBlk *blk); + void invalidate(CacheBlk *blk) override; /** * Access block and update replacement data. May not succeed, in which case @@ -195,7 +195,7 @@ public: * Just a wrapper of above function to conform with the base interface. */ CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, - int context_src); + int context_src) override; /** * Find the block in the cache, do not update the replacement data. @@ -204,16 +204,16 @@ public: * @param asid The address space ID. * @return Pointer to the cache block. */ - CacheBlk* findBlock(Addr addr, bool is_secure) const; + CacheBlk* findBlock(Addr addr, bool is_secure) const override; /** * Find a replacement block for the address provided. * @param pkt The request to a find a replacement candidate for. * @return The block to place the replacement in. */ - CacheBlk* findVictim(Addr addr); + CacheBlk* findVictim(Addr addr) override; - void insertBlock(PacketPtr pkt, CacheBlk *blk); + void insertBlock(PacketPtr pkt, CacheBlk *blk) override; /** * Return the block size of this cache. @@ -240,7 +240,7 @@ public: * @return The number of sets. */ unsigned - getNumSets() const + getNumSets() const override { return 1; } @@ -250,7 +250,7 @@ public: * @return The number of ways. */ unsigned - getNumWays() const + getNumWays() const override { return numBlocks; } @@ -261,7 +261,7 @@ public: * @param way The way of the block. * @return The cache block. */ - CacheBlk* findBlockBySetAndWay(int set, int way) const; + CacheBlk* findBlockBySetAndWay(int set, int way) const override; /** * Align an address to the block size. @@ -279,7 +279,7 @@ public: * @param addr The address to get the tag from. * @return The tag. */ - Addr extractTag(Addr addr) const + Addr extractTag(Addr addr) const override { return blkAlign(addr); } @@ -289,7 +289,7 @@ public: * @param addr The address to get the set from. * @return 0. */ - int extractSet(Addr addr) const + int extractSet(Addr addr) const override { return 0; } @@ -300,7 +300,7 @@ public: * @param set The set the block belongs to. * @return the block address. */ - Addr regenerateBlkAddr(Addr tag, unsigned set) const + Addr regenerateBlkAddr(Addr tag, unsigned set) const override { return (tag); } @@ -308,7 +308,7 @@ public: /** * @todo Implement as in lru. Currently not used */ - virtual std::string print() const { return ""; } + virtual std::string print() const override { return ""; } /** * Visit each block in the tag store and apply a visitor to the diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index a7f3e5602..617c94914 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -868,14 +868,14 @@ class DRAMCtrl : public AbstractMemory public: - void regStats(); + void regStats() override; DRAMCtrl(const DRAMCtrlParams* p); DrainState drain() override; virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; virtual void init() override; virtual void startup() override; diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh index 77486de88..e57479247 100644 --- a/src/mem/dramsim2.hh +++ b/src/mem/dramsim2.hh @@ -192,10 +192,10 @@ class DRAMSim2 : public AbstractMemory DrainState drain() override; virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; - virtual void init(); - virtual void startup(); + void init() override; + void startup() override; protected: diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index 7dcbbd65a..47c7c5491 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -211,14 +211,14 @@ class FuncPageTable : public PageTableBase ~FuncPageTable(); - void initState(ThreadContext* tc) + void initState(ThreadContext* tc) override { } void map(Addr vaddr, Addr paddr, int64_t size, - uint64_t flags = 0); - void remap(Addr vaddr, int64_t size, Addr new_vaddr); - void unmap(Addr vaddr, int64_t size); + uint64_t flags = 0) override; + void remap(Addr vaddr, int64_t size, Addr new_vaddr) override; + void unmap(Addr vaddr, int64_t size) override; /** * Check if any pages in a region are already allocated @@ -226,14 +226,14 @@ class FuncPageTable : public PageTableBase * @param size The length of the region. * @return True if no pages in the region are mapped. */ - bool isUnmapped(Addr vaddr, int64_t size); + bool isUnmapped(Addr vaddr, int64_t size) override; /** * Lookup function * @param vaddr The virtual address. * @return entry The page table entry corresponding to vaddr. */ - bool lookup(Addr vaddr, TheISA::TlbEntry &entry); + bool lookup(Addr vaddr, TheISA::TlbEntry &entry) override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py index 14c3f543c..4a957b66e 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py @@ -42,8 +42,6 @@ class NetworkLink_d(ClockedObject): "virtual channels per virtual network") virt_nets = Param.Int(Parent.number_of_virtual_networks, "number of virtual networks") - channel_width = Param.Int(Parent.bandwidth_factor, - "channel width == bw factor") class CreditLink_d(NetworkLink_d): type = 'CreditLink_d' diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc index 8d9acd433..60c7ca3f4 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc @@ -33,7 +33,7 @@ NetworkLink_d::NetworkLink_d(const Params *p) : ClockedObject(p), Consumer(this), m_id(p->link_id), - m_latency(p->link_latency), channel_width(p->channel_width), + m_latency(p->link_latency), linkBuffer(new flitBuffer_d()), link_consumer(nullptr), link_srcQueue(nullptr), m_link_utilized(0), m_vc_load(p->vcs_per_vnet * p->virt_nets) diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh index ad9fef2f4..be937f093 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh @@ -69,7 +69,6 @@ class NetworkLink_d : public ClockedObject, public Consumer private: const int m_id; const Cycles m_latency; - const int channel_width; flitBuffer_d *linkBuffer; Consumer *link_consumer; diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh index 75fe71dfb..cd777f5e7 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.hh +++ b/src/mem/ruby/structures/RubyMemoryControl.hh @@ -53,15 +53,15 @@ class RubyMemoryControl : public AbstractMemory, public Consumer public: typedef RubyMemoryControlParams Params; RubyMemoryControl(const Params *p); - void init(); + void init() override; void reset(); ~RubyMemoryControl(); virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; DrainState drain() override; - void wakeup(); + void wakeup() override; void setDescription(const std::string& name) { m_description = name; }; std::string getDescription() { return m_description; }; @@ -72,8 +72,8 @@ class RubyMemoryControl : public AbstractMemory, public Consumer void enqueueMemRef(MemoryNode *memRef); bool areNSlotsAvailable(int n) { return true; }; // infinite queue length - void print(std::ostream& out) const; - void regStats(); + void print(std::ostream& out) const override; + void regStats() override; const int getBank(const Addr addr) const; const int getRank(const Addr addr) const; diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh index 1d5451f6e..34f9be34c 100644 --- a/src/mem/ruby/system/DMASequencer.hh +++ b/src/mem/ruby/system/DMASequencer.hh @@ -60,7 +60,7 @@ class DMASequencer : public MemObject public: typedef DMASequencerParams Params; DMASequencer(const Params *); - void init(); + void init() override; RubySystem *m_ruby_system; public: @@ -95,7 +95,7 @@ class DMASequencer : public MemObject }; BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; /* external interface */ RequestStatus makeRequest(PacketPtr pkt); diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 98fab8c4e..58d2558dd 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -143,12 +143,12 @@ class RubyPort : public MemObject RubyPort(const Params *p); virtual ~RubyPort() {} - void init(); + void init() override; BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; virtual RequestStatus makeRequest(PacketPtr pkt) = 0; virtual int outstandingCount() const = 0; diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh index 23974e924..e396dce64 100644 --- a/src/mem/ruby/system/RubySystem.hh +++ b/src/mem/ruby/system/RubySystem.hh @@ -89,16 +89,16 @@ class RubySystem : public ClockedObject return m_profiler; } - void regStats() { m_profiler->regStats(name()); } + void regStats() override { m_profiler->regStats(name()); } void collateStats() { m_profiler->collateStats(); } - void resetStats(); + void resetStats() override; - void memWriteback(); + void memWriteback() override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; void drainResume() override; void process(); - void startup(); + void startup() override; bool functionalRead(Packet *ptr); bool functionalWrite(Packet *ptr); diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh index c5b932bf0..35d8aeafb 100644 --- a/src/mem/simple_mem.hh +++ b/src/mem/simple_mem.hh @@ -188,8 +188,8 @@ class SimpleMemory : public AbstractMemory DrainState drain() override; BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID); - void init(); + PortID idx = InvalidPortID) override; + void init() override; protected: diff --git a/src/sim/clock_domain.hh b/src/sim/clock_domain.hh index cc26d7bbd..71627434a 100644 --- a/src/sim/clock_domain.hh +++ b/src/sim/clock_domain.hh @@ -237,7 +237,7 @@ class SrcClockDomain : public ClockDomain return freqOpPoints[perf_level]; } - void startup(); + void startup() override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/sim/process.hh b/src/sim/process.hh index b3a33bcd9..df007c9f2 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -120,7 +120,7 @@ class Process : public SimObject // constructor Process(ProcessParams *params); - virtual void initState(); + void initState() override; DrainState drain() override; @@ -156,7 +156,7 @@ class Process : public SimObject void inheritFDArray(Process *p); // override of virtual SimObject method: register statistics - virtual void regStats(); + void regStats() override; // After getting registered with system object, tell process which // system-wide context id it is assigned. diff --git a/src/sim/root.hh b/src/sim/root.hh index 4d9c63a6b..7273a077b 100644 --- a/src/sim/root.hh +++ b/src/sim/root.hh @@ -110,7 +110,7 @@ class Root : public SimObject /** Schedule the timesync event at initState() when not unserializing */ - void initState(); + void initState() override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/sim/sim_events.hh b/src/sim/sim_events.hh index dbbc5174f..9a79a2e9d 100644 --- a/src/sim/sim_events.hh +++ b/src/sim/sim_events.hh @@ -88,9 +88,9 @@ class LocalSimLoopExitEvent : public Event const std::string getCause() const { return cause; } const int getCode() const { return code; } - void process(); // process event + void process() override; // process event - virtual const char *description() const; + const char *description() const override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; @@ -107,7 +107,7 @@ class CountedDrainEvent : public Event public: CountedDrainEvent(); - void process(); + void process() override; void setCount(int _count) { count = _count; } @@ -128,9 +128,9 @@ class CountedExitEvent : public Event public: CountedExitEvent(const std::string &_cause, int &_downCounter); - void process(); // process event + void process() override; // process event - virtual const char *description() const; + const char *description() const override; }; diff --git a/src/sim/system.hh b/src/sim/system.hh index be0538839..c67f70219 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -97,9 +97,9 @@ class System : public MemObject SystemPort(const std::string &_name, MemObject *_owner) : MasterPort(_name, _owner) { } - bool recvTimingResp(PacketPtr pkt) + bool recvTimingResp(PacketPtr pkt) override { panic("SystemPort does not receive timing!\n"); return false; } - void recvReqRetry() + void recvReqRetry() override { panic("SystemPort does not expect retry!\n"); } }; @@ -111,7 +111,7 @@ class System : public MemObject * After all objects have been created and all ports are * connected, check that the system port is connected. */ - virtual void init(); + void init() override; /** * Get a reference to the system port that can be used by @@ -127,7 +127,7 @@ class System : public MemObject * Additional function to return the Port of a memory object. */ BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + PortID idx = InvalidPortID) override; /** @{ */ /** @@ -335,7 +335,7 @@ class System : public MemObject return masterIds.size(); } - virtual void regStats(); + void regStats() override; /** * Called by pseudo_inst to track the number of work items started by this * system. @@ -487,7 +487,7 @@ class System : public MemObject System(Params *p); ~System(); - void initState(); + void initState() override; const Params *params() const { return (const Params *)_params; } diff --git a/src/sim/ticked_object.hh b/src/sim/ticked_object.hh index c3c6a0153..b21322670 100644 --- a/src/sim/ticked_object.hh +++ b/src/sim/ticked_object.hh @@ -198,7 +198,7 @@ class TickedObject : public ClockedObject, public Ticked using ClockedObject::unserialize; /** Pass on regStats, serialize etc. onto Ticked */ - void regStats(); + void regStats() override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; }; diff --git a/src/sim/voltage_domain.hh b/src/sim/voltage_domain.hh index d22556083..e7e4f8180 100644 --- a/src/sim/voltage_domain.hh +++ b/src/sim/voltage_domain.hh @@ -111,7 +111,7 @@ class VoltageDomain : public SimObject * Startup has all SrcClockDomains registered with this voltage domain, so * try to make sure that all perf level requests from them are met. */ - void startup(); + void startup() override; /** * Recomputes the highest (fastest, i.e., numerically lowest) requested @@ -126,7 +126,7 @@ class VoltageDomain : public SimObject */ bool sanitiseVoltages(); - void regStats(); + void regStats() override; void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; |