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-rw-r--r--configs/common/CpuConfig.py5
-rw-r--r--configs/common/Options.py2
-rw-r--r--src/cpu/o3/O3CPU.py1
-rw-r--r--src/cpu/o3/lsq_unit.hh1
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh9
5 files changed, 14 insertions, 4 deletions
diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 21dabdfa9..ec1f3692a 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -128,6 +128,11 @@ def config_scheme(cpu_cls, cpu_list, options):
else:
cpu.useIFT = False
+ if options.trackBranch:
+ cpu.trackBranch = True
+ else:
+ cpu.trackBranch = False
+
if len(options.scheme)!=0:
cpu.simulateScheme = options.scheme
else:
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 89a8eda04..6bdfe5250 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -319,6 +319,8 @@ def addCommonOptions(parser):
help="choose baseline or defense designs to evaluate")
parser.add_option("--useIFT", default=None, action="store", type="int",
help="Use information flow tracking.")
+ parser.add_option("--trackBranch", default=None, action="store", type="int",
+ help="Track tainted branches in information flow tracking.")
parser.add_option("--needsTSO", default=None, action="store", type="int",
help="Select TSO or RC. Set unzero to use TSO.")
parser.add_option("--allowSpecBuffHit", default=None, action="store",
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 1a97faced..11a2133e6 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -170,6 +170,7 @@ class DerivO3CPU(BaseCPU):
needsTSO = Param.Bool(False, "Enable TSO Memory model")
allowSpecBuffHit = Param.Bool(True, "Enable hit/reuse spec buffer entries")
useIFT = Param.Bool(False, "use IFT to filter")
+ trackBranch = Param.Bool(True, "Track tainted branches")
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index c512ef819..fbe5248f7 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -529,6 +529,7 @@ class LSQUnit {
bool isFuturistic;
bool allowSpecBuffHit;
bool useIFT;
+ bool trackBranch;
/* [mengjia] different schemes determine values of 4 variables. */
// Will also need how many read/write ports the Dcache has. Or keep track
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f22383506..9d71c2093 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -232,9 +232,10 @@ LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
needsTSO = params->needsTSO;
allowSpecBuffHit = params->allowSpecBuffHit;
useIFT = params->useIFT;
+ trackBranch = params->trackBranch;
cprintf("Info: simulation uses scheme: %s; "
- "needsTSO=%d; allowSpecBuffHit=%d; useIFT=%d\n",
- scheme, needsTSO, allowSpecBuffHit, useIFT);
+ "needsTSO=%d; allowSpecBuffHit=%d; useIFT=%d; trackBranch=%d\n",
+ scheme, needsTSO, allowSpecBuffHit, useIFT, trackBranch);
// [mengjia] end of setting configuration variables
resetState();
@@ -1033,7 +1034,7 @@ LSQUnit<Impl>::updateVisibleState()
/* set taint for dst registers */
inst->taintDestRegs(true, "unsafe load");
bool doSpecLoad = false;
- if (inst->afterTaintedBranch) {
+ if (trackBranch && inst->afterTaintedBranch) {
doSpecLoad = true;
DPRINTF(LSQUnit, "load inst [sn:%lli] %s is after a tainted branch.\n", inst->seqNum, inst->pcState());
} else if (inst->srcTainted()) {
@@ -1083,7 +1084,7 @@ LSQUnit<Impl>::updateVisibleState()
if (inst->needPostFetch()) {
doSpecLoad = true;
DPRINTF(LSQUnit, "load inst [sn:%lli] %s needs post fetch.\n", inst->seqNum, inst->pcState());
- } else if (inst->afterTaintedBranch) {
+ } else if (trackBranch && inst->afterTaintedBranch) {
doSpecLoad = true;
DPRINTF(LSQUnit, "load inst [sn:%lli] %s is after a tainted branch.\n", inst->seqNum, inst->pcState());
} else if (inst->srcTainted()) {