diff options
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 27 | ||||
| -rw-r--r-- | src/arch/arm/regfile/regfile.hh | 14 |
2 files changed, 21 insertions, 20 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index c9df79e1e..fa41918c1 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -40,16 +40,27 @@ def operand_types {{ 'df' : ('float', 64) }}; +let {{ + maybePCRead = ''' + ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) : + xc->%(func)s(this, %(op_idx)s)) + ''' + maybePCWrite = ''' + ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) : + xc->%(func)s(this, %(op_idx)s, %(final_val)s)) + ''' +}}; + def operands {{ #General Purpose Integer Reg Operands - 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), - 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2), - 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3), - 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4), + 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), + 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), + 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), + 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), #Destination register for load/store double instructions - 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4), - 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5), + 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), + 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6), 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7), @@ -57,8 +68,8 @@ def operands {{ 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9), #Register fields for microops - 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11), - 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12), + 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), + 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), #General Purpose Floating Point Reg Operands 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh index 7f4d21353..5a812fecf 100644 --- a/src/arch/arm/regfile/regfile.hh +++ b/src/arch/arm/regfile/regfile.hh @@ -122,22 +122,12 @@ namespace ArmISA IntReg readIntReg(int intReg) { - // In the Arm, reading from the PC for a generic instruction yields - // the current PC + 8, due to previous pipeline implementations - if (intReg == PCReg) - return intRegFile.readReg(intReg) + 8; - //return pc + 8; - else - return intRegFile.readReg(intReg); + return intRegFile.readReg(intReg); } void setIntReg(int intReg, const IntReg &val) { - // Have to trap writes to PC so that they update NPC instead - if (intReg == PCReg) - setNextPC(val); - else - intRegFile.setReg(intReg, val); + intRegFile.setReg(intReg, val); } protected: |