diff options
| -rw-r--r-- | src/cpu/BaseCPU.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 402831f5a..868f47015 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -167,7 +167,7 @@ class BaseCPU(MemObject): exec('self.%s = bus.port' % p) def addPrivateSplitL1Caches(self, ic, dc): - assert(len(self._mem_ports) < 6) + assert(len(self._mem_ports) < 8) self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side @@ -176,6 +176,8 @@ class BaseCPU(MemObject): if buildEnv['FULL_SYSTEM']: if buildEnv['TARGET_ISA'] in ['x86', 'arm']: self._mem_ports += ["itb.walker.port", "dtb.walker.port"] + if buildEnv['TARGET_ISA'] == 'x86': + self._mem_ports += ["interrupts.pio", "interrupts.int_port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) |