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-rwxr-xr-xsrc/arch/arm/stage2_lookup.cc2
-rwxr-xr-xsrc/arch/arm/stage2_lookup.hh2
-rwxr-xr-xsrc/arch/arm/stage2_mmu.cc4
-rwxr-xr-xsrc/arch/arm/stage2_mmu.hh2
-rw-r--r--src/cpu/checker/cpu.hh2
-rw-r--r--src/cpu/checker/cpu_impl.hh2
-rw-r--r--src/cpu/inorder/cpu.cc14
-rw-r--r--src/cpu/inorder/cpu.hh15
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.cc2
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.hh2
-rw-r--r--src/cpu/inorder/resource.hh2
-rw-r--r--src/cpu/inorder/resource_pool.cc2
-rw-r--r--src/cpu/inorder/resource_pool.hh2
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc2
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh2
-rw-r--r--src/cpu/inorder/resources/fetch_seq_unit.cc2
-rw-r--r--src/cpu/inorder/resources/fetch_seq_unit.hh2
-rw-r--r--src/cpu/inorder/resources/fetch_unit.cc2
-rw-r--r--src/cpu/inorder/resources/fetch_unit.hh2
-rw-r--r--src/cpu/minor/fetch1.cc4
-rw-r--r--src/cpu/minor/fetch1.hh4
-rw-r--r--src/cpu/minor/lsq.cc8
-rw-r--r--src/cpu/minor/lsq.hh12
-rw-r--r--src/cpu/o3/cpu.cc4
-rw-r--r--src/cpu/o3/cpu.hh4
-rw-r--r--src/cpu/o3/dyn_inst.hh2
-rw-r--r--src/cpu/o3/dyn_inst_impl.hh2
-rw-r--r--src/cpu/o3/fetch.hh4
-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rw-r--r--src/cpu/ozone/dyn_inst_impl.hh2
-rw-r--r--src/cpu/simple/base.cc2
-rw-r--r--src/cpu/simple/base.hh2
-rw-r--r--src/cpu/simple/timing.cc7
-rw-r--r--src/cpu/simple/timing.hh8
-rw-r--r--src/cpu/translation.hh4
-rw-r--r--src/sim/tlb.hh4
36 files changed, 71 insertions, 69 deletions
diff --git a/src/arch/arm/stage2_lookup.cc b/src/arch/arm/stage2_lookup.cc
index 1299ade68..59cacd527 100755
--- a/src/arch/arm/stage2_lookup.cc
+++ b/src/arch/arm/stage2_lookup.cc
@@ -171,7 +171,7 @@ Stage2LookUp::mergeTe(RequestPtr req, BaseTLB::Mode mode)
}
void
-Stage2LookUp::finish(Fault _fault, RequestPtr req,
+Stage2LookUp::finish(const Fault &_fault, RequestPtr req,
ThreadContext *tc, BaseTLB::Mode mode)
{
fault = _fault;
diff --git a/src/arch/arm/stage2_lookup.hh b/src/arch/arm/stage2_lookup.hh
index 3a1228f46..657392ea9 100755
--- a/src/arch/arm/stage2_lookup.hh
+++ b/src/arch/arm/stage2_lookup.hh
@@ -97,7 +97,7 @@ class Stage2LookUp : public BaseTLB::Translation
void markDelayed() {}
- void finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ void finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode);
};
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index 01451548c..98eeedb78 100755
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -114,8 +114,8 @@ Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent,
}
void
-Stage2MMU::Stage2Translation::finish(Fault _fault, RequestPtr req, ThreadContext *tc,
- BaseTLB::Mode mode)
+Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req,
+ ThreadContext *tc, BaseTLB::Mode mode)
{
fault = _fault;
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index d1812c4ed..37eca4f56 100755
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -78,7 +78,7 @@ class Stage2MMU : public SimObject
markDelayed() {}
void
- finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode);
void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index bf71dc30e..d684b142b 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -426,7 +426,7 @@ class Checker : public CheckerCPU
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
- void advancePC(Fault fault);
+ void advancePC(const Fault &fault);
void verify(DynInstPtr &inst);
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index b6ec4f77b..9743905c1 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -69,7 +69,7 @@ using namespace TheISA;
template <class Impl>
void
-Checker<Impl>::advancePC(Fault fault)
+Checker<Impl>::advancePC(const Fault &fault)
{
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index e966e8e83..c825f2979 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -128,8 +128,8 @@ InOrderCPU::TickEvent::description() const
}
InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
- Fault fault, ThreadID _tid, DynInstPtr inst,
- CPUEventPri event_pri)
+ const Fault &fault, ThreadID _tid,
+ DynInstPtr inst, CPUEventPri event_pri)
: Event(event_pri), cpu(_cpu)
{
setEvent(e_type, fault, _tid, inst);
@@ -910,7 +910,7 @@ InOrderCPU::getInterrupts()
}
void
-InOrderCPU::processInterrupts(Fault interrupt)
+InOrderCPU::processInterrupts(const Fault &interrupt)
{
// Check for interrupts here. For now can copy the code that
// exists within isa_fullsys_traits.hh. Also assume that thread 0
@@ -928,7 +928,7 @@ InOrderCPU::processInterrupts(Fault interrupt)
}
void
-InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
+InOrderCPU::trapContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay)
{
scheduleCpuEvent(Trap, fault, tid, inst, delay);
@@ -936,7 +936,7 @@ InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
}
void
-InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+InOrderCPU::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
fault->invoke(tcBase(tid), inst->staticInst);
removePipelineStalls(tid);
@@ -970,7 +970,7 @@ InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
}
void
-InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
+InOrderCPU::scheduleCpuEvent(CPUEventType c_event, const Fault &fault,
ThreadID tid, DynInstPtr inst,
Cycles delay, CPUEventPri event_pri)
{
@@ -1847,7 +1847,7 @@ InOrderCPU::wakeup()
}
void
-InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
+InOrderCPU::syscallContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay)
{
// Syscall must be non-speculative, so squash from last stage
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 0104cb95f..7efd5ae21 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -263,11 +263,11 @@ class InOrderCPU : public BaseCPU
public:
/** Constructs a CPU event. */
- CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
+ CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, const Fault &fault,
ThreadID _tid, DynInstPtr inst, CPUEventPri event_pri);
/** Set Type of Event To Be Scheduled */
- void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
+ void setEvent(CPUEventType e_type, const Fault &_fault, ThreadID _tid,
DynInstPtr _inst)
{
fault = _fault;
@@ -291,7 +291,8 @@ class InOrderCPU : public BaseCPU
};
/** Schedule a CPU Event */
- void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
+ void scheduleCpuEvent(CPUEventType cpu_event, const Fault &fault,
+ ThreadID tid,
DynInstPtr inst, Cycles delay = Cycles(0),
CPUEventPri event_pri = InOrderCPU_Pri);
@@ -471,7 +472,7 @@ class InOrderCPU : public BaseCPU
Fault getInterrupts();
/** Processes any an interrupt fault. */
- void processInterrupts(Fault interrupt);
+ void processInterrupts(const Fault &interrupt);
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
@@ -483,18 +484,18 @@ class InOrderCPU : public BaseCPU
bool validDataAddr(Addr addr) { return true; }
/** Schedule a syscall on the CPU */
- void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
+ void syscallContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay = Cycles(0));
/** Executes a syscall.*/
void syscall(int64_t callnum, ThreadID tid);
/** Schedule a trap on the CPU */
- void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
+ void trapContext(const Fault &fault, ThreadID tid, DynInstPtr inst,
Cycles delay = Cycles(0));
/** Perform trap to Handle Given Fault */
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
/** Schedule thread activation on the CPU */
void activateContext(ThreadID tid, Cycles delay = Cycles(0));
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index d0d308f7a..08f583338 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -298,7 +298,7 @@ InOrderDynInst::hwrei()
void
-InOrderDynInst::trap(Fault fault)
+InOrderDynInst::trap(const Fault &fault)
{
this->cpu->trap(fault, this->threadNumber, this);
}
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 759da4b04..7558df7d1 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -524,7 +524,7 @@ class InOrderDynInst : public ExecContext, public RefCounted
/** Calls hardware return from error interrupt. */
Fault hwrei();
/** Traps to handle specified fault. */
- void trap(Fault fault);
+ void trap(const Fault &fault);
bool simPalCheck(int palFunc);
short syscallNum;
diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index ef712d5c9..eaecc2824 100644
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -104,7 +104,7 @@ class Resource {
virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
/** Post-processsing for Trap Generated from this instruction */
- virtual void trap(Fault fault, ThreadID tid, DynInstPtr inst) { }
+ virtual void trap(const Fault &fault, ThreadID tid, DynInstPtr inst) { }
/** Request usage of this resource. Returns a ResourceRequest object
* with all the necessary resource information
diff --git a/src/cpu/inorder/resource_pool.cc b/src/cpu/inorder/resource_pool.cc
index c09f6c31d..e0f23235e 100644
--- a/src/cpu/inorder/resource_pool.cc
+++ b/src/cpu/inorder/resource_pool.cc
@@ -206,7 +206,7 @@ ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
}
void
-ResourcePool::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+ResourcePool::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
DPRINTF(Resource, "[tid:%i] Broadcasting Trap to all "
"resources.\n", tid);
diff --git a/src/cpu/inorder/resource_pool.hh b/src/cpu/inorder/resource_pool.hh
index 2720ed10a..9e3198e1e 100644
--- a/src/cpu/inorder/resource_pool.hh
+++ b/src/cpu/inorder/resource_pool.hh
@@ -193,7 +193,7 @@ class ResourcePool {
void instGraduated(InstSeqNum seq_num, ThreadID tid);
/** Broadcast trap to all resources */
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
/** The number of instructions available that a resource can
* can still process.
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index dea4f91fb..251369e01 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -405,7 +405,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
}
void
-CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+CacheUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
tlbBlocked[tid] = false;
}
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 9a7faf9cd..65f18eedb 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -113,7 +113,7 @@ class CacheUnit : public Resource
bool processSquash(CacheReqPacket *cache_pkt);
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
void recvRetry();
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc
index 03741b55c..ead4953fb 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc
@@ -304,7 +304,7 @@ FetchSeqUnit::suspendThread(ThreadID tid)
}
void
-FetchSeqUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+FetchSeqUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
pcValid[tid] = true;
pc[tid] = cpu->pcState(tid);
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.hh b/src/cpu/inorder/resources/fetch_seq_unit.hh
index 4cb18a1c7..a8db85b06 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.hh
+++ b/src/cpu/inorder/resources/fetch_seq_unit.hh
@@ -71,7 +71,7 @@ class FetchSeqUnit : public Resource {
InstSeqNum squash_seq_num, ThreadID tid);
/** Update to correct PC from a trap */
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
protected:
unsigned instSize;
diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc
index 49bd0434b..6892688b2 100644
--- a/src/cpu/inorder/resources/fetch_unit.cc
+++ b/src/cpu/inorder/resources/fetch_unit.cc
@@ -574,7 +574,7 @@ FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
}
void
-FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
+FetchUnit::trap(const Fault &fault, ThreadID tid, DynInstPtr inst)
{
//@todo: per thread?
decoder[tid]->reset();
diff --git a/src/cpu/inorder/resources/fetch_unit.hh b/src/cpu/inorder/resources/fetch_unit.hh
index d1c7b22c0..d72721009 100644
--- a/src/cpu/inorder/resources/fetch_unit.hh
+++ b/src/cpu/inorder/resources/fetch_unit.hh
@@ -87,7 +87,7 @@ class FetchUnit : public CacheUnit
/** Executes one of the commands from the "Command" enum */
void execute(int slot_num);
- void trap(Fault fault, ThreadID tid, DynInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, DynInstPtr inst);
TheISA::Decoder *decoder[ThePipeline::MaxThreads];
diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index 45dc5eddc..79a5d0a78 100644
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -204,8 +204,8 @@ Fetch1::FetchRequest::makePacket()
}
void
-Fetch1::FetchRequest::finish(
- Fault fault_, RequestPtr request_, ThreadContext *tc, BaseTLB::Mode mode)
+Fetch1::FetchRequest::finish(const Fault &fault_, RequestPtr request_,
+ ThreadContext *tc, BaseTLB::Mode mode)
{
fault = fault_;
diff --git a/src/cpu/minor/fetch1.hh b/src/cpu/minor/fetch1.hh
index 29a63d1f1..45977b310 100644
--- a/src/cpu/minor/fetch1.hh
+++ b/src/cpu/minor/fetch1.hh
@@ -163,8 +163,8 @@ class Fetch1 : public Named
/** Interface for ITLB responses. Populates self and then passes
* the request on to the ports' handleTLBResponse member
* function */
- void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
- BaseTLB::Mode mode);
+ void finish(const Fault &fault_, RequestPtr request_,
+ ThreadContext *tc, BaseTLB::Mode mode);
public:
FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index b05ae514c..0a473af89 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -226,8 +226,8 @@ LSQ::clearMemBarrier(MinorDynInstPtr inst)
}
void
-LSQ::SingleDataRequest::finish(Fault fault_, RequestPtr request_,
- ThreadContext *tc, BaseTLB::Mode mode)
+LSQ::SingleDataRequest::finish(const Fault &fault_, RequestPtr request_,
+ ThreadContext *tc, BaseTLB::Mode mode)
{
fault = fault_;
@@ -273,8 +273,8 @@ LSQ::SingleDataRequest::retireResponse(PacketPtr packet_)
}
void
-LSQ::SplitDataRequest::finish(Fault fault_, RequestPtr request_,
- ThreadContext *tc, BaseTLB::Mode mode)
+LSQ::SplitDataRequest::finish(const Fault &fault_, RequestPtr request_,
+ ThreadContext *tc, BaseTLB::Mode mode)
{
fault = fault_;
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index 183986826..7da2fd694 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -268,8 +268,8 @@ class LSQ : public Named
{
protected:
/** TLB interace */
- void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
- BaseTLB::Mode mode)
+ void finish(const Fault &fault_, RequestPtr request_,
+ ThreadContext *tc, BaseTLB::Mode mode)
{ }
public:
@@ -329,8 +329,8 @@ class LSQ : public Named
{
protected:
/** TLB interace */
- void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
- BaseTLB::Mode mode);
+ void finish(const Fault &fault_, RequestPtr request_,
+ ThreadContext *tc, BaseTLB::Mode mode);
/** Has my only packet been sent to the memory system but has not
* yet been responded to */
@@ -415,8 +415,8 @@ class LSQ : public Named
protected:
/** TLB response interface */
- void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
- BaseTLB::Mode mode);
+ void finish(const Fault &fault_, RequestPtr request_,
+ ThreadContext *tc, BaseTLB::Mode mode);
public:
SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2055d63b6..fdbbd5c14 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1095,7 +1095,7 @@ FullO3CPU<Impl>::getInterrupts()
template <class Impl>
void
-FullO3CPU<Impl>::processInterrupts(Fault interrupt)
+FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
{
// Check for interrupts here. For now can copy the code that
// exists within isa_fullsys_traits.hh. Also assume that thread 0
@@ -1112,7 +1112,7 @@ FullO3CPU<Impl>::processInterrupts(Fault interrupt)
template <class Impl>
void
-FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
+FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, StaticInstPtr inst)
{
// Pass the thread's TC into the invoke method.
fault->invoke(this->threadContexts[tid], inst);
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index f5f9897e7..cfed216c3 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -498,7 +498,7 @@ class FullO3CPU : public BaseO3CPU
{ return globalSeqNum++; }
/** Traps to handle given fault. */
- void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
+ void trap(const Fault &fault, ThreadID tid, StaticInstPtr inst);
/** HW return from error interrupt. */
Fault hwrei(ThreadID tid);
@@ -509,7 +509,7 @@ class FullO3CPU : public BaseO3CPU
Fault getInterrupts();
/** Processes any an interrupt fault. */
- void processInterrupts(Fault interrupt);
+ void processInterrupts(const Fault &interrupt);
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 52ea1101a..ea961092d 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -230,7 +230,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
/** Calls hardware return from error interrupt. */
Fault hwrei();
/** Traps to handle specified fault. */
- void trap(Fault fault);
+ void trap(const Fault &fault);
bool simPalCheck(int palFunc);
/** Emulates a syscall. */
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 4e1492077..e51054f8d 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -225,7 +225,7 @@ BaseO3DynInst<Impl>::hwrei()
template <class Impl>
void
-BaseO3DynInst<Impl>::trap(Fault fault)
+BaseO3DynInst<Impl>::trap(const Fault &fault)
{
this->cpu->trap(fault, this->threadNumber, this->staticInst);
}
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 4d01610d9..968d94029 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -100,7 +100,7 @@ class DefaultFetch
{}
void
- finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode)
{
assert(mode == BaseTLB::Execute);
@@ -294,7 +294,7 @@ class DefaultFetch
* @return Any fault that occured.
*/
bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
- void finishTranslation(Fault fault, RequestPtr mem_req);
+ void finishTranslation(const Fault &fault, RequestPtr mem_req);
/** Check if an interrupt is pending and that we need to handle
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index fb933b8ca..b9e3b78c5 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -633,7 +633,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
template <class Impl>
void
-DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
+DefaultFetch<Impl>::finishTranslation(const Fault &fault, RequestPtr mem_req)
{
ThreadID tid = mem_req->threadId();
Addr fetchBufferBlockPC = mem_req->getVaddr();
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 7c0bd7a02..2e0c383ac 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -255,7 +255,7 @@ OzoneDynInst<Impl>::hwrei()
template <class Impl>
void
-OzoneDynInst<Impl>::trap(Fault fault)
+OzoneDynInst<Impl>::trap(const Fault &fault)
{
fault->invoke(this->thread->getTC());
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index f022d05e0..5130e2960 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -555,7 +555,7 @@ BaseSimpleCPU::postExecute()
}
void
-BaseSimpleCPU::advancePC(Fault fault)
+BaseSimpleCPU::advancePC(const Fault &fault)
{
const bool branching(thread->pcState().branching());
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 3755a94a9..43d96fbeb 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -168,7 +168,7 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
void setupFetchRequest(Request *req);
void preExecute();
void postExecute();
- void advancePC(Fault fault);
+ void advancePC(const Fault &fault);
virtual void deallocateContext(ThreadID thread_num);
virtual void haltContext(ThreadID thread_num);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index f572fc268..9c8f8b57a 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -328,7 +328,7 @@ TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
}
void
-TimingSimpleCPU::translationFault(Fault fault)
+TimingSimpleCPU::translationFault(const Fault &fault)
{
// fault may be NoFault in cases where a fault is suppressed,
// for instance prefetches.
@@ -576,7 +576,8 @@ TimingSimpleCPU::fetch()
void
-TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
+TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
+ ThreadContext *tc)
{
if (fault == NoFault) {
DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
@@ -608,7 +609,7 @@ TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
void
-TimingSimpleCPU::advanceInst(Fault fault)
+TimingSimpleCPU::advanceInst(const Fault &fault)
{
if (_status == Faulting)
return;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 4a5a20429..a7ea57c67 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -123,7 +123,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
}
void
- finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode)
{
cpu->sendFetch(fault, req, tc);
@@ -135,7 +135,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
uint8_t *data, bool read);
- void translationFault(Fault fault);
+ void translationFault(const Fault &fault);
void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
@@ -280,10 +280,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
Addr addr, unsigned flags, uint64_t *res);
void fetch();
- void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
+ void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
void completeIfetch(PacketPtr );
void completeDataAccess(PacketPtr pkt);
- void advanceInst(Fault fault);
+ void advanceInst(const Fault &fault);
/** This function is used by the page table walker to determine if it could
* translate the a pending request or if the underlying request has been
diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh
index 46c96a0d4..f870a9c11 100644
--- a/src/cpu/translation.hh
+++ b/src/cpu/translation.hh
@@ -111,7 +111,7 @@ class WholeTranslationState
* request to make it easier to access them later on.
*/
bool
- finish(Fault fault, int index)
+ finish(const Fault &fault, int index)
{
assert(outstanding);
faults[index] = fault;
@@ -249,7 +249,7 @@ class DataTranslation : public BaseTLB::Translation
* translation is complete if the state says so.
*/
void
- finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode)
{
assert(state);
diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index 397d6e0f2..6296602a0 100644
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -104,8 +104,8 @@ class BaseTLB : public SimObject
* be responsible for cleaning itself up which will happen in this
* function. Once it's called, the object is no longer valid.
*/
- virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
- Mode mode) = 0;
+ virtual void finish(const Fault &fault, RequestPtr req,
+ ThreadContext *tc, Mode mode) = 0;
/** This function is used by the page table walker to determine if it
* should translate the a pending request or if the underlying request