diff options
| -rw-r--r-- | src/arch/alpha/faults.hh | 5 | ||||
| -rw-r--r-- | src/arch/alpha/tlb.cc | 11 | ||||
| -rw-r--r-- | src/arch/arm/faults.hh | 5 | ||||
| -rw-r--r-- | src/arch/mips/faults.hh | 5 | ||||
| -rw-r--r-- | src/arch/power/faults.hh | 7 | ||||
| -rw-r--r-- | src/arch/sparc/faults.hh | 7 | ||||
| -rw-r--r-- | src/arch/x86/faults.hh | 5 | ||||
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 5 | ||||
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 10 |
9 files changed, 19 insertions, 41 deletions
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh index edac1cda6..3da97ccb4 100644 --- a/src/arch/alpha/faults.hh +++ b/src/arch/alpha/faults.hh @@ -84,11 +84,6 @@ class AlignmentFault : public AlphaFault bool isAlignmentFault() const {return true;} }; -static inline Fault genMachineCheckFault() -{ - return new MachineCheckFault; -} - class ResetFault : public AlphaFault { private: diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index fbe188973..b211c4923 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -36,6 +36,7 @@ #include "arch/alpha/faults.hh" #include "arch/alpha/pagetable.hh" #include "arch/alpha/tlb.hh" +#include "arch/generic/debugfaults.hh" #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" @@ -434,8 +435,9 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) } // check that the physical address is ok (catch bad physical addresses) - if (req->getPaddr() & ~PAddrImplMask) - return genMachineCheckFault(); + if (req->getPaddr() & ~PAddrImplMask) { + return new MachineCheckFault(); + } return checkCacheability(req, true); @@ -562,8 +564,9 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) } // check that the physical address is ok (catch bad physical addresses) - if (req->getPaddr() & ~PAddrImplMask) - return genMachineCheckFault(); + if (req->getPaddr() & ~PAddrImplMask) { + return new MachineCheckFault(); + } return checkCacheability(req); } diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index fe1258a16..2d025cc94 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -242,11 +242,6 @@ class FlushPipe : public ArmFaultVals<FlushPipe> StaticInstPtr inst = StaticInst::nullStaticInstPtr); }; -static inline Fault genMachineCheckFault() -{ - return new Reset(); -} - // A fault that flushes the pipe, excluding the faulting instructions class ArmSev : public ArmFaultVals<ArmSev> { diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh index e78abbb43..89b6924c6 100644 --- a/src/arch/mips/faults.hh +++ b/src/arch/mips/faults.hh @@ -128,11 +128,6 @@ class MachineCheckFault : public MipsFault<MachineCheckFault> bool isMachineCheckFault() { return true; } }; -static inline Fault genMachineCheckFault() -{ - return new MachineCheckFault; -} - class ResetFault : public MipsFault<ResetFault> { public: diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh index 6aedd7e00..a99ae7b30 100644 --- a/src/arch/power/faults.hh +++ b/src/arch/power/faults.hh @@ -85,13 +85,6 @@ class AlignmentFault : public PowerFault } }; - -static inline Fault -genMachineCheckFault() -{ - return new MachineCheckFault(); -} - } // namespace PowerISA #endif // __ARCH_POWER_FAULTS_HH__ diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index 31209440f..88c269d66 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -287,13 +287,6 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction> #endif }; -static inline Fault -genMachineCheckFault() -{ - return new InternalProcessorError; -} - - } // namespace SparcISA #endif // __SPARC_FAULTS_HH__ diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh index 2e8889404..fba2a26b5 100644 --- a/src/arch/x86/faults.hh +++ b/src/arch/x86/faults.hh @@ -363,11 +363,6 @@ namespace X86ISA {} }; - static inline Fault genMachineCheckFault() - { - return new MachineCheck; - } - class SIMDFloatingPointFault : public X86Fault { public: diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index af926759c..3c1af4533 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -38,6 +38,7 @@ #include <queue> #include "arch/faults.hh" +#include "arch/generic/debugfaults.hh" #include "arch/isa_traits.hh" #include "arch/locked_mem.hh" #include "arch/mmapped_ipr.hh" @@ -568,7 +569,9 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, delete sreqLow; delete sreqHigh; } - return TheISA::genMachineCheckFault(); + return new GenericISA::M5PanicFault( + "Uncachable load [sn:%llx] PC %s\n", + load_inst->seqNum, load_inst->pcState()); } // Check the SQ for any previous stores that might lead to forwarding diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 77ce705bc..acef6ec9d 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -41,6 +41,7 @@ * Korey Sewell */ +#include "arch/generic/debugfaults.hh" #include "arch/locked_mem.hh" #include "base/str.hh" #include "config/the_isa.hh" @@ -539,7 +540,10 @@ LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) ++lsqMemOrderViolation; - return TheISA::genMachineCheckFault(); + return new GenericISA::M5PanicFault( + "Detected fault with inst [sn:%lli] and " + "[sn:%lli] at address %#x\n", + inst->seqNum, ld_inst->seqNum, ld_eff_addr1); } } @@ -563,7 +567,9 @@ LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) ++lsqMemOrderViolation; - return TheISA::genMachineCheckFault(); + return new GenericISA::M5PanicFault("Detected fault with " + "inst [sn:%lli] and [sn:%lli] at address %#x\n", + inst->seqNum, ld_inst->seqNum, ld_eff_addr1); } } |