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-rw-r--r--arch/alpha/ev5.cc2
-rw-r--r--arch/alpha/faults.cc20
-rw-r--r--arch/alpha/faults.hh9
-rw-r--r--cpu/exec_context.cc2
-rw-r--r--cpu/exec_context.hh2
-rw-r--r--cpu/simple/cpu.cc4
-rw-r--r--cpu/simple/cpu.hh2
-rw-r--r--sim/faults.hh5
8 files changed, 40 insertions, 6 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 349c2930f..23546bbe2 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -166,7 +166,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
}
void
-ExecContext::ev5_trap(Fault fault)
+ExecContext::ev5_temp_trap(Fault fault)
{
DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
cpu->recordEvent(csprintf("Fault %s", fault->name()));
diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index 99365f8d2..2eedfedbd 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -27,6 +27,7 @@
*/
#include "arch/alpha/faults.hh"
+#include "cpu/exec_context.hh"
namespace AlphaISA
{
@@ -97,6 +98,25 @@ FaultName IntegerOverflowFault::_name = "intover";
FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_stat;
+#if FULL_SYSTEM
+
+void AlphaFault::ev5_trap(ExecContext * xc)
+{
+ xc->ev5_temp_trap(this);
+}
+
+void AlphaMachineCheckFault::ev5_trap(ExecContext * xc)
+{
+ xc->ev5_temp_trap(this);
+}
+
+void AlphaAlignmentFault::ev5_trap(ExecContext * xc)
+{
+ xc->ev5_temp_trap(this);
+}
+
+#endif
+
} // namespace AlphaISA
/*Fault * ListOfFaults[] = {
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index f8cb44017..7c52738c1 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -45,6 +45,9 @@ class AlphaFault : public FaultBase
static FaultVect _vect;
static FaultStat _stat;
public:
+#if FULL_SYSTEM
+ void ev5_trap(ExecContext * xc);
+#endif
FaultName name() {return _name;}
virtual FaultVect vect() {return _vect;}
virtual FaultStat & stat() {return _stat;}
@@ -56,6 +59,9 @@ class AlphaMachineCheckFault : public MachineCheckFault
static FaultVect _vect;
static FaultStat _stat;
public:
+#if FULL_SYSTEM
+ void ev5_trap(ExecContext * xc);
+#endif
FaultVect vect() {return _vect;}
FaultStat & stat() {return _stat;}
};
@@ -66,6 +72,9 @@ class AlphaAlignmentFault : public AlignmentFault
static FaultVect _vect;
static FaultStat _stat;
public:
+#if FULL_SYSTEM
+ void ev5_trap(ExecContext * xc);
+#endif
FaultVect vect() {return _vect;}
FaultStat & stat() {return _stat;}
};
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index cf0ced7b0..7e8b81e18 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -227,7 +227,7 @@ ExecContext::trap(Fault fault)
/** @todo: Going to hack it for now. Do a true fixup later. */
#if FULL_SYSTEM
- ev5_trap(fault);
+ fault->ev5_trap(this);
#else
fatal("fault (%d) detected @ PC 0x%08p", fault, readPC());
#endif
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 834eacec8..e23370d0b 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -425,7 +425,7 @@ class ExecContext
void setIntrFlag(int val) { regs.intrflag = val; }
Fault hwrei();
bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
- void ev5_trap(Fault fault);
+ void ev5_temp_trap(Fault fault);
bool simPalCheck(int palFunc);
#endif
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 4b0eda386..1f362876f 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -688,7 +688,7 @@ SimpleCPU::tick()
if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) {
ipr[IPR_ISR] = summary;
ipr[IPR_INTID] = ipl;
- xc->ev5_trap(new InterruptFault);
+ (new InterruptFault)->ev5_trap(xc);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
ipr[IPR_IPLR], ipl, summary);
@@ -812,7 +812,7 @@ SimpleCPU::tick()
if (fault != NoFault) {
#if FULL_SYSTEM
- xc->ev5_trap(fault);
+ fault->ev5_trap(xc);
#else // !FULL_SYSTEM
fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
#endif // FULL_SYSTEM
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index ed7b1e29b..c58b3c5ba 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -334,7 +334,7 @@ class SimpleCPU : public BaseCPU
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }
bool inPalMode() { return xc->inPalMode(); }
- void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
+ void ev5_trap(Fault fault) { fault->ev5_trap(xc); }
bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
#else
void syscall() { xc->syscall(); }
diff --git a/sim/faults.hh b/sim/faults.hh
index d0bf78815..69e592485 100644
--- a/sim/faults.hh
+++ b/sim/faults.hh
@@ -31,7 +31,9 @@
#include "base/refcnt.hh"
#include "sim/stats.hh"
+#include "config/full_system.hh"
+class ExecContext;
class FaultBase;
typedef RefCountingPtr<FaultBase> Fault;
@@ -53,6 +55,9 @@ class FaultBase : public RefCounted
return "none";
}
virtual FaultStat & stat() = 0;
+#if FULL_SYSTEM
+ virtual void ev5_trap(ExecContext * xc) = 0;
+#endif
template<typename T>
bool isA() {return dynamic_cast<T *>(this);}
virtual bool isMachineCheckFault() {return false;}