summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--configs/common/Caches.py6
-rw-r--r--configs/common/FSConfig.py4
-rw-r--r--src/mem/cache/cache_builder.cc6
-rw-r--r--src/python/m5/objects/BaseCache.py3
-rw-r--r--tests/configs/memtest.py4
-rw-r--r--tests/configs/o3-timing-mp.py4
-rw-r--r--tests/configs/o3-timing.py2
-rw-r--r--tests/configs/simple-atomic-mp.py4
-rw-r--r--tests/configs/simple-timing-mp.py4
-rw-r--r--tests/configs/simple-timing.py4
-rw-r--r--tests/configs/tsunami-simple-atomic-dual.py43
-rw-r--r--tests/configs/tsunami-simple-atomic.py43
-rw-r--r--tests/configs/tsunami-simple-timing-dual.py44
-rw-r--r--tests/configs/tsunami-simple-timing.py44
14 files changed, 184 insertions, 31 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 4692ef537..4bff2c8a4 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -32,7 +32,7 @@ from m5.objects import *
class L1Cache(BaseCache):
assoc = 2
block_size = 64
- latency = 1
+ latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
protocol = CoherenceProtocol(protocol='moesi')
@@ -40,7 +40,7 @@ class L1Cache(BaseCache):
class L2Cache(BaseCache):
assoc = 8
block_size = 64
- latency = 10
+ latency = '10ns'
mshrs = 20
tgts_per_mshr = 12
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 289a7a5f4..593baf169 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -61,7 +61,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
- self.bridge = Bridge(fix_partial_write_b=True)
+ self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
self.bridge.side_a = self.iobus.port
self.bridge.side_b = self.membus.port
@@ -94,7 +94,7 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
- self.bridge = Bridge()
+ self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 318b57d50..e887f711e 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -134,7 +134,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
Param<bool> prefetch_cache_check_push;
Param<bool> prefetch_use_cpu_id;
Param<bool> prefetch_data_accesses_only;
- Param<int> hit_latency;
END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
@@ -190,8 +189,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
- INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false),
- INIT_PARAM_DFLT(hit_latency, "Hit Latecny for a succesful access", 1)
+ INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
END_INIT_SIM_OBJECT_PARAMS(BaseCache)
@@ -211,7 +209,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
BUILD_NULL_PREFETCHER(TAGS); \
} \
Cache<TAGS, c>::Params params(tags, mq, coh, base_params, \
- pf, prefetch_access, hit_latency, \
+ pf, prefetch_access, latency, \
true, \
store_compressed, \
adaptive_compression, \
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
index 773a11bea..7df5215e4 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/python/m5/objects/BaseCache.py
@@ -9,7 +9,7 @@ class BaseCache(MemObject):
"Use an adaptive compression scheme")
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
- latency = Param.Int("Latency")
+ latency = Param.Latency("Latency")
compressed_bus = Param.Bool(False,
"This cache connects to a compressed memory")
compression_latency = Param.Latency('0ns',
@@ -59,6 +59,5 @@ class BaseCache(MemObject):
"Use the CPU ID to seperate calculations of prefetches")
prefetch_data_accesses_only = Param.Bool(False,
"Only prefetch on data not on instruction accesses")
- hit_latency = Param.Int(1,"Hit Latency of the cache")
cpu_side = Port("Port on side closer to CPU")
mem_side = Port("Port on side closer to MEM")
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index f56edef4a..15a4f8f05 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -34,7 +34,7 @@ from m5.objects import *
# ====================
class L1(BaseCache):
- latency = 1
+ latency = '1ns'
block_size = 64
mshrs = 12
tgts_per_mshr = 8
@@ -46,7 +46,7 @@ class L1(BaseCache):
class L2(BaseCache):
block_size = 64
- latency = 10
+ latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 1e414294c..1ac9bd2e4 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -35,7 +35,7 @@ m5.AddToPath('../configs/common')
# ====================
class L1(BaseCache):
- latency = 1
+ latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
@@ -47,7 +47,7 @@ class L1(BaseCache):
class L2(BaseCache):
block_size = 64
- latency = 100
+ latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index d20a7e0c8..366a3eb0d 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -33,7 +33,7 @@ m5.AddToPath('../configs/common')
class MyCache(BaseCache):
assoc = 2
block_size = 64
- latency = 1
+ latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index e8000cd0a..de0793d1c 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -34,7 +34,7 @@ from m5.objects import *
# ====================
class L1(BaseCache):
- latency = 1
+ latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
@@ -46,7 +46,7 @@ class L1(BaseCache):
class L2(BaseCache):
block_size = 64
- latency = 100
+ latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index a263bcf57..1fd0e8c3c 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -34,7 +34,7 @@ from m5.objects import *
# ====================
class L1(BaseCache):
- latency = 1
+ latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
@@ -46,7 +46,7 @@ class L1(BaseCache):
class L2(BaseCache):
block_size = 64
- latency = 100
+ latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 6c4b8232f..0ed985a17 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -32,13 +32,13 @@ from m5.objects import *
class MyCache(BaseCache):
assoc = 2
block_size = 64
- latency = 1
+ latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
cpu = TimingSimpleCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
- MyCache(size = '2MB'))
+ MyCache(size = '2MB', latency='10ns'))
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 7ed854f44..131095055 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -31,12 +31,49 @@ from m5.objects import *
m5.AddToPath('../configs/common')
import FSConfig
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ protocol = CoherenceProtocol(protocol='moesi')
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+#cpu
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
+#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
+
system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
for c in cpus:
- c.connectMemPorts(system.membus)
+ c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+ # connect cpu level-1 caches to shared level-2 cache
+ c.connectMemPorts(system.toL2Bus)
+ c.clock = '2GHz'
root = Root(system=system)
-
-m5.ticks.setGlobalFrequency('2GHz')
+m5.ticks.setGlobalFrequency('1THz')
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 4859f30cf..595b1aeda 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -31,10 +31,49 @@ from m5.objects import *
m5.AddToPath('../configs/common')
import FSConfig
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ protocol = CoherenceProtocol(protocol='moesi')
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+#cpu
cpu = AtomicSimpleCPU(cpu_id=0)
+#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
+
system.cpu = cpu
-cpu.connectMemPorts(system.membus)
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectMemPorts(system.toL2Bus)
+cpu.clock = '2GHz'
root = Root(system=system)
-m5.ticks.setGlobalFrequency('2GHz')
+m5.ticks.setGlobalFrequency('1THz')
+
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 0c8c3d523..47fba30ff 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -31,11 +31,51 @@ from m5.objects import *
m5.AddToPath('../configs/common')
import FSConfig
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ protocol = CoherenceProtocol(protocol='moesi')
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+#cpu
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
+#the system
system = FSConfig.makeLinuxAlphaSystem('timing')
+
system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
for c in cpus:
- c.connectMemPorts(system.membus)
+ c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+ # connect cpu level-1 caches to shared level-2 cache
+ c.connectMemPorts(system.toL2Bus)
+ c.clock = '2GHz'
root = Root(system=system)
-m5.ticks.setGlobalFrequency('2GHz')
+m5.ticks.setGlobalFrequency('1THz')
+
+
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 9f532e3ae..999bde087 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -31,10 +31,50 @@ from m5.objects import *
m5.AddToPath('../configs/common')
import FSConfig
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ protocol = CoherenceProtocol(protocol='moesi')
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+#cpu
cpu = TimingSimpleCPU(cpu_id=0)
+#the system
system = FSConfig.makeLinuxAlphaSystem('timing')
+
system.cpu = cpu
-cpu.connectMemPorts(system.membus)
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectMemPorts(system.toL2Bus)
+cpu.clock = '2GHz'
root = Root(system=system)
-m5.ticks.setGlobalFrequency('2GHz')
+m5.ticks.setGlobalFrequency('1THz')
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 23:15:10 +0000