diff options
| -rw-r--r-- | src/mem/packet.hh | 3 | ||||
| -rw-r--r-- | src/python/m5/objects/BaseCPU.py | 1 | ||||
| -rw-r--r-- | tests/configs/simple-timing.py | 2 |
3 files changed, 5 insertions, 1 deletions
diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 068fea678..5d8308df7 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -266,6 +266,7 @@ class Packet result(Unknown) { flags = 0; + time = curTick; } /** Alternate constructor if you are trying to create a packet with @@ -280,6 +281,7 @@ class Packet result(Unknown) { flags = 0; + time = curTick; } /** Destructor. */ @@ -295,6 +297,7 @@ class Packet assert(req->validPaddr); addr = req->paddr; size = req->size; + time = req->time; addrSizeValid = true; result = Unknown; if (dynamicData) { diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 81e09c94c..41e90b12b 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -43,6 +43,7 @@ class BaseCPU(SimObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] +# self.mem = dc def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 9a5b20e88..7bb76db0e 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -40,7 +40,7 @@ cpu = TimingSimpleCPU() cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) cpu.mem = cpu.dcache - +cpu.mem = cpu.dcache system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) |