diff options
105 files changed, 6487 insertions, 256 deletions
@@ -11,6 +11,8 @@ Nathan L. Binkert * Tru64 support * Ethernet (Link, NSGIGE, Sinic) device support * PCI device support +* Checkpoint framework +* Configuration system Steven K. Reinhardt ----------------------- @@ -23,6 +25,7 @@ Steven K. Reinhardt * PC sampling * Deprecated detailed CPU * Binary Loading +* Configuration system Ali G. Saidi ----------------------- @@ -51,30 +54,33 @@ Ronald G. Dreslinski Jr Lisa R. Hsu ----------------------- * DP83820 NIC device model -* Kernel stats stuff -* Linux Dist disk image building +* Kernel stats +* Linux Dist disk image building (current) Gabriel Black ----------------------- * Multiple ISA support -* Alpha support reorgization +* SPARC ISA support +* Alpha support reorganization * SPARC SE support Korey L. Sewell ----------------------- * O3CPU SMT support -* MIPS support +* MIPS ISA support +* Multiple ISA support in O3CPU Andrew L. Schultz ----------------------- * IDE controller/disk model * PCI devices interface -* Linux Dist disk image building +* Linux Dist disk image building (deprecated) Erik G. Hallnor ----------------------- * Caches * Trace reader support +* Checkpoint framework Steve E. Raasch ----------------------- diff --git a/SConstruct b/SConstruct index fd912fc03..642d012db 100644 --- a/SConstruct +++ b/SConstruct @@ -302,8 +302,6 @@ sticky_opts.AddOptions( # Non-sticky options only apply to the current build. nonsticky_opts = Options(args=ARGUMENTS) nonsticky_opts.AddOptions( - ListOption('TEST_CPU_MODELS', 'CPU models to test if regression is being run', '', - env['ALL_CPU_LIST']), BoolOption('update_ref', 'Update test reference outputs', False) ) @@ -498,7 +496,7 @@ for build_path in build_paths: # Set up the regression tests for each build. for e in envList: SConscript('tests/SConscript', - build_dir = os.path.join(build_path, 'test', e.Label), + build_dir = os.path.join(build_path, 'tests', e.Label), exports = { 'env' : e }, duplicate = False) Help(help_text) diff --git a/configs/boot/devtime.rcS b/configs/boot/devtime.rcS index 91fddc20d..22a5469b8 100644 --- a/configs/boot/devtime.rcS +++ b/configs/boot/devtime.rcS @@ -1,3 +1,6 @@ +echo "switching cpus" +m5 switchcpu +echo "done" insmod /modules/devtime.ko dataAddr=0x9000004 count=100 rmmod devtime insmod /modules/devtime.ko dataAddr=0x1a0000300 count=100 diff --git a/configs/boot/iscsi-client.rcS b/configs/boot/iscsi-client.rcS index 51ed5a284..cfa87652e 100644 --- a/configs/boot/iscsi-client.rcS +++ b/configs/boot/iscsi-client.rcS @@ -59,7 +59,7 @@ node.cnx[0].iscsi.MaxRecvDataSegmentLength = 65536 #discovery.sendtargets.auth.password = aloha EOF -mount -t sysfs none /sys +#mount -t sysfs none /sys echo "" > /var/log/iscsi.log chmod 0600 /var/log/iscsi.log @@ -74,8 +74,10 @@ echo "/sbin/hotplug" > /proc/sys/kernel/hotplug echo "Starting iscsid..." /iscsi/iscsid -f & +sleep 1 + echo "Waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 echo "Attaching target..." /iscsi/iscsiadm -m discovery -t st -p 192.168.0.1 @@ -92,7 +94,7 @@ sleep 5 #PARAMS="-n 16 -s 32 -r 1 -c 50" # stable ~1.5 Gbps #PARAMS="-n 50 -s 32 -r 1 -c 50" # stable ~1.5 Gbps PARAMS="-n 50 -s 8 -r .666 -c 50" -COMMAND="/benchmarks/aio_bench/aio-bench $PARAMS -i 1000000 -C 50000 /dev/sda" +COMMAND="/benchmarks/aio-bench $PARAMS -i 1000000 -C 50000 /dev/sda" echo "Starting aio benchmark..." echo $COMMAND diff --git a/configs/boot/iscsi-server.rcS b/configs/boot/iscsi-server.rcS index 904368a4b..210f4eaef 100644 --- a/configs/boot/iscsi-server.rcS +++ b/configs/boot/iscsi-server.rcS @@ -49,8 +49,10 @@ echo -n "start enterprise target..." /iscsi/ietd -f & echo "done." +sleep 3 + echo "notifying client..." -echo "server ready" | /usr/bin/netcat -c 192.168.0.10 8000 +echo "server ready" | netcat -c 192.168.0.10 8000 echo "done" echo "starting bash shell..." diff --git a/configs/boot/micro_memlat.rcS b/configs/boot/micro_memlat.rcS index 50ee8efb3..3bf6b6b2b 100644 --- a/configs/boot/micro_memlat.rcS +++ b/configs/boot/micro_memlat.rcS @@ -1,3 +1,4 @@ -/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd 512 64 +m5 checkpoint 1 999999999 +/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd 64 m5 exit diff --git a/configs/boot/micro_stream.rcS b/configs/boot/micro_stream.rcS index 7b4c445c6..1cf3a7dc3 100644 --- a/configs/boot/micro_stream.rcS +++ b/configs/boot/micro_stream.rcS @@ -1,3 +1,3 @@ -/benchmarks/micros/stream +/benchmarks/micros/simstream m5 exit diff --git a/configs/boot/micro_tlblat.rcS b/configs/boot/micro_tlblat.rcS index ab05fd9ff..fd5fd53c1 100644 --- a/configs/boot/micro_tlblat.rcS +++ b/configs/boot/micro_tlblat.rcS @@ -1,3 +1,3 @@ -/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd_2MB 2 8192 +/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd_2MB 20 8192 m5 exit diff --git a/configs/boot/nat-netperf-maerts-client.rcS b/configs/boot/nat-netperf-maerts-client.rcS index ab66b7d4a..863766a6b 100644 --- a/configs/boot/nat-netperf-maerts-client.rcS +++ b/configs/boot/nat-netperf-maerts-client.rcS @@ -23,9 +23,9 @@ echo "262143" > /proc/sys/net/core/optmem_max echo "100000" > /proc/sys/net/core/netdev_max_backlog echo -n "waiting for natbox..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 -BINARY=/benchmarks/netperf/netperf +BINARY=/benchmarks/netperf-bin/netperf TEST="TCP_MAERTS" SHORT_ARGS="-l -100k" LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144" diff --git a/configs/boot/nat-netperf-server.rcS b/configs/boot/nat-netperf-server.rcS index 61b4bea7a..23b99a13a 100644 --- a/configs/boot/nat-netperf-server.rcS +++ b/configs/boot/nat-netperf-server.rcS @@ -21,11 +21,11 @@ echo "262143" > /proc/sys/net/core/optmem_max echo "100000" > /proc/sys/net/core/netdev_max_backlog echo "running netserver..." -/benchmarks/netperf/netserver +/benchmarks/netperf-bin/netserver echo -n "signal natbox to begin..." sleep 5 -echo "server ready" | /usr/bin/netcat -c $NATBOX 8000 +echo "server ready" | netcat -c $NATBOX 8000 echo "done." echo "starting bash..." diff --git a/configs/boot/nat-netperf-stream-client.rcS b/configs/boot/nat-netperf-stream-client.rcS index e37b8e565..f20e92c5c 100644 --- a/configs/boot/nat-netperf-stream-client.rcS +++ b/configs/boot/nat-netperf-stream-client.rcS @@ -24,9 +24,9 @@ echo "modifying route table" route add default gw 10.0.0.1 echo -n "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 -BINARY=/benchmarks/netperf/netperf +BINARY=/benchmarks/netperf-bin/netperf TEST="TCP_STREAM" SHORT_ARGS="-l -100k" LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144" diff --git a/configs/boot/nat-spec-surge-client.rcS b/configs/boot/nat-spec-surge-client.rcS index 67c831eb0..d26e38378 100644 --- a/configs/boot/nat-spec-surge-client.rcS +++ b/configs/boot/nat-spec-surge-client.rcS @@ -38,7 +38,7 @@ echo "changing route table..." route add default gw 10.0.0.1 echo "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 echo -n "running surge client..." /bin/bash -c "cd /benchmarks/surge && ./spec-m5 1 20 1 $SERVER 5 40000 1000000000 1000" diff --git a/configs/boot/nat-spec-surge-server.rcS b/configs/boot/nat-spec-surge-server.rcS index 279cd5652..0f462568c 100755 --- a/configs/boot/nat-spec-surge-server.rcS +++ b/configs/boot/nat-spec-surge-server.rcS @@ -49,7 +49,7 @@ echo "done." echo "notifying natbox..." sleep 5 -echo "server ready" | /usr/bin/netcat -c $NATBOX 8000 +echo "server ready" | netcat -c $NATBOX 8000 echo "done" echo -n "starting bash shell..." diff --git a/configs/boot/natbox-netperf.rcS b/configs/boot/natbox-netperf.rcS index 32a7371a0..e6384757e 100644 --- a/configs/boot/natbox-netperf.rcS +++ b/configs/boot/natbox-netperf.rcS @@ -24,7 +24,7 @@ echo "100000" > /proc/sys/net/core/netdev_max_backlog echo "1" > /proc/sys/net/ipv4/ip_forward echo "waiting for netserver..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 echo "setting up iptables..." IPTABLES=/sbin/iptables @@ -47,7 +47,7 @@ $IPTABLES -t nat -A POSTROUTING -o $EXTIF -j MASQUERADE echo "informing client..." sleep 5 -echo "server ready" | /usr/bin/netcat -c $CLIENT 8000 +echo "server ready" | netcat -c $CLIENT 8000 echo "starting bash..." exec /bin/bash diff --git a/configs/boot/natbox-spec-surge.rcS b/configs/boot/natbox-spec-surge.rcS index 8b84b1a35..4346a6229 100644 --- a/configs/boot/natbox-spec-surge.rcS +++ b/configs/boot/natbox-spec-surge.rcS @@ -27,7 +27,7 @@ echo "1" > /proc/sys/net/ipv4/ip_forward echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max echo "waiting for netserver..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 echo "setting up iptables..." IPTABLES=/sbin/iptables @@ -50,7 +50,7 @@ $IPTABLES -t nat -A POSTROUTING -o $EXTIF -j MASQUERADE echo "informing client..." sleep 5 -echo "server ready" | /usr/bin/netcat -c $CLIENT 8000 +echo "server ready" | netcat -c $CLIENT 8000 echo "starting bash..." exec /bin/bash diff --git a/configs/boot/netperf-rr.rcS b/configs/boot/netperf-rr.rcS index 8c5ea050c..1467c1f67 100644 --- a/configs/boot/netperf-rr.rcS +++ b/configs/boot/netperf-rr.rcS @@ -19,9 +19,9 @@ echo "262143" > /proc/sys/net/core/optmem_max echo "100000" > /proc/sys/net/core/netdev_max_backlog echo -n "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 -BINARY=/benchmarks/netperf/netperf +BINARY=/benchmarks/netperf-bin/netperf TEST="TCP_RR" SHORT_ARGS="-l -1k" LONG_ARGS="-k10000,0 -K10000,0" diff --git a/configs/boot/netperf-server.rcS b/configs/boot/netperf-server.rcS index c75d918a2..95a4ac4cf 100644 --- a/configs/boot/netperf-server.rcS +++ b/configs/boot/netperf-server.rcS @@ -19,11 +19,11 @@ echo "262143" > /proc/sys/net/core/optmem_max echo "100000" > /proc/sys/net/core/netdev_max_backlog echo "running netserver..." -/benchmarks/netperf/netserver +/benchmarks/netperf-bin/netserver echo -n "signal client to begin..." sleep 1 -echo "server ready" | /usr/bin/netcat -c $CLIENT 8000 +echo "server ready" | netcat -c $CLIENT 8000 echo "done." echo "starting bash..." diff --git a/configs/boot/netperf-stream-client.rcS b/configs/boot/netperf-stream-client.rcS index 430ac265c..9a2cc0ec1 100644 --- a/configs/boot/netperf-stream-client.rcS +++ b/configs/boot/netperf-stream-client.rcS @@ -19,9 +19,9 @@ echo "262143" > /proc/sys/net/core/optmem_max echo "100000" > /proc/sys/net/core/netdev_max_backlog echo -n "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 -BINARY=/benchmarks/netperf/netperf +BINARY=/benchmarks/netperf-bin/netperf TEST="TCP_STREAM" SHORT_ARGS="-l -100k" LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144" diff --git a/configs/boot/netperf-stream-nt-client.rcS b/configs/boot/netperf-stream-nt-client.rcS index 6664cd024..568115525 100644 --- a/configs/boot/netperf-stream-nt-client.rcS +++ b/configs/boot/netperf-stream-nt-client.rcS @@ -19,9 +19,9 @@ echo "262143" > /proc/sys/net/core/optmem_max echo "100000" > /proc/sys/net/core/netdev_max_backlog echo -n "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 -BINARY=/benchmarks/netperf/netperf +BINARY=/benchmarks/netperf-bin/netperf TEST="TCP_STREAM" SHORT_ARGS="-l -100k" LONG_ARGS="-- -m 65536 -M 65536 -s 262144 -S 262144" @@ -34,23 +34,12 @@ echo "starting test..." echo "netperf warmup" echo $SHORT eval $SHORT -NUMCLNTS=`/sbin/m5 initparam` -[ "$NUMCLNTS" -eq "0" ] && NUMCLNTS=1 - -echo "netperf benchmark... starting $NUMCLNTS..." -lcv=0 - -while [ "$lcv" -lt "$NUMCLNTS" ] -do - echo $LONG - eval $LONG & - ((lcv += 1)) -done - -ckpt=200000000 -((ckpt = ckpt * 12/3 + 1000000000)) - -echo "configuring checkpointing at $ckpt..." -/sbin/m5 checkpoint $ckpt 2000000000 -echo "done configuring checkpointing..." -sleep 100000 + +echo "netperf benchmark" +echo $LONG +/sbin/m5 ivlb 1 +/sbin/m5 resetstats +/sbin/m5 dumpresetstats 200000000 2000000000 +/sbin/m5 checkpoint 200000000 2000000000 +eval $LONG +/sbin/m5 exit diff --git a/configs/boot/nfs-client-nhfsstone.rcS b/configs/boot/nfs-client-nhfsstone.rcS index 6a9650d38..c59655a47 100755 --- a/configs/boot/nfs-client-nhfsstone.rcS +++ b/configs/boot/nfs-client-nhfsstone.rcS @@ -36,7 +36,7 @@ echo -n "starting nfs client..." echo "done." echo -n "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 echo -n "mounting remote share..." mkdir /nfs @@ -44,6 +44,6 @@ mount 10.0.0.1:/nfs /nfs echo "done." /sbin/m5 checkpoint 8000000000 2000000000 -/benchmarks/nfs/nhfsstone -l 300 -t 50 -p 14 -m /benchmarks/nfs/nfs.mix2 /nfs +/sbin/nhfsstone /nfs /sbin/m5 exit diff --git a/configs/boot/nfs-client-tcp-smallb.rcS b/configs/boot/nfs-client-tcp-smallb.rcS index eeb6aaadd..b71ca0bf1 100755 --- a/configs/boot/nfs-client-tcp-smallb.rcS +++ b/configs/boot/nfs-client-tcp-smallb.rcS @@ -36,13 +36,13 @@ echo -n "starting nfs client..." echo "done." echo -n "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 echo -n "mounting remote share..." mkdir /nfs mount -o rsize=1460,wsize=1460,tcp 10.0.0.1:/nfs /nfs echo "done." -/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /nfs +/usr/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /nfs /sbin/m5 exit diff --git a/configs/boot/nfs-client-tcp.rcS b/configs/boot/nfs-client-tcp.rcS index 319281385..e707ef257 100755 --- a/configs/boot/nfs-client-tcp.rcS +++ b/configs/boot/nfs-client-tcp.rcS @@ -36,13 +36,13 @@ echo -n "starting nfs client..." echo "done." echo -n "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 echo -n "mounting remote share..." mkdir /nfs mount -o tcp 10.0.0.1:/nfs /nfs echo "done." -/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /nfs +/usr/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /nfs /sbin/m5 exit diff --git a/configs/boot/nfs-client.rcS b/configs/boot/nfs-client.rcS index feae55d58..f3fbe0467 100755 --- a/configs/boot/nfs-client.rcS +++ b/configs/boot/nfs-client.rcS @@ -36,13 +36,13 @@ echo -n "starting nfs client..." echo "done." echo -n "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 echo -n "mounting remote share..." mkdir /nfs mount 10.0.0.1:/nfs /nfs echo "done." -/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /nfs +/usr/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /nfs /sbin/m5 exit diff --git a/configs/boot/nfs-server-nhfsstone.rcS b/configs/boot/nfs-server-nhfsstone.rcS index 222ba309e..7fa44a5f2 100755 --- a/configs/boot/nfs-server-nhfsstone.rcS +++ b/configs/boot/nfs-server-nhfsstone.rcS @@ -59,7 +59,7 @@ echo "Exporting shares..." echo -n "signal client to mount..." sleep 5 -echo "server ready" | /usr/bin/netcat -c 10.0.0.2 8000 +echo "server ready" | netcat -c 10.0.0.2 8000 echo "done." echo -n "starting bash shell..." diff --git a/configs/boot/nfs-server.rcS b/configs/boot/nfs-server.rcS index ecd4d8317..7314d06c3 100755 --- a/configs/boot/nfs-server.rcS +++ b/configs/boot/nfs-server.rcS @@ -28,17 +28,24 @@ echo "524287" > /proc/sys/net/core/wmem_max echo "524287" > /proc/sys/net/core/optmem_max echo "300000" > /proc/sys/net/core/netdev_max_backlog echo "131072" > /proc/sys/fs/file-max -echo "10" > /proc/sys/vm/dirty_writeback_centisecs echo "done." -echo "load scsi_debug kernel module..." +#if [ ! -x /dev/sda ] +#then +# mknod /dev/sda b 8 0 +# mknod /dev/sda1 b 8 1 +#fi + /sbin/insmod /modules/scsi_debug.ko dev_size_mb=768 echo -n "creating partition and formatting..." +#echo "1,767,L" > /tmp/sfdisk.run +#/usr/sbin/sfdisk -uM --force /dev/sda < /tmp/sfdisk.run /sbin/mke2fs -F /dev/sda mkdir /nfs -/bin/mount /dev/sda /nfs +/bin/mount /dev/sda /nfs chmod a+rwx /nfs +#/usr/sbin/sfdisk -uM -l /dev/sda echo "done." echo "/nfs 10.0.0.0/255.0.0.0(rw,sync,no_root_squash)" > /etc/exports @@ -54,7 +61,7 @@ echo "Exporting shares..." /sbin/exportfs -r -v echo -n "signal client to mount..." -echo "server ready" | /usr/bin/netcat -c 10.0.0.2 8000 +echo "server ready" | netcat -c 10.0.0.2 8000 echo "done." echo -n "starting bash shell..." diff --git a/configs/boot/ping-client.rcS b/configs/boot/ping-client.rcS index 3f0ded75e..260ff42e0 100644 --- a/configs/boot/ping-client.rcS +++ b/configs/boot/ping-client.rcS @@ -19,7 +19,7 @@ echo "262143" > /proc/sys/net/core/optmem_max echo "100000" > /proc/sys/net/core/netdev_max_backlog echo -n "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 ping $SERVER /sbin/m5 exit diff --git a/configs/boot/ping-server.rcS b/configs/boot/ping-server.rcS index 5dab6effb..311c80212 100644 --- a/configs/boot/ping-server.rcS +++ b/configs/boot/ping-server.rcS @@ -19,7 +19,7 @@ echo "262143" > /proc/sys/net/core/optmem_max echo "100000" > /proc/sys/net/core/netdev_max_backlog echo -n "signal client to begin..." -echo "server ready" | /usr/bin/netcat -c $CLIENT 8000 +echo "server ready" | netcat -c $CLIENT 8000 echo "done." echo "starting bash..." diff --git a/configs/boot/spec-surge-client.rcS b/configs/boot/spec-surge-client.rcS index f42d6045f..03f25986c 100644 --- a/configs/boot/spec-surge-client.rcS +++ b/configs/boot/spec-surge-client.rcS @@ -32,10 +32,10 @@ echo "131072" > /proc/sys/fs/file-max echo "done." echo "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 echo -n "running surge client..." -/bin/bash -c "cd /benchmarks/surge && ./spec-m5 1 20 1 192.168.0.1 5 40000 1000000000 1000" +/bin/bash -c "cd /benchmarks/specsurge && ./spec-m5 1 20 1 192.168.0.1 5 40000 1000000000 1000" echo "done." echo -n "halting machine" diff --git a/configs/boot/spec-surge-server.rcS b/configs/boot/spec-surge-server.rcS index e2d0a58d7..89a3fb4f5 100755 --- a/configs/boot/spec-surge-server.rcS +++ b/configs/boot/spec-surge-server.rcS @@ -40,13 +40,13 @@ mount /dev/hdb1 /z/htdocs echo "done." echo -n "starting httpd..." -/benchmarks/apache2/bin/apachectl start +/usr/sbin/apache2 -f /etc/apache2/httpd.conf -k start sleep 2 -cat /benchmarks/apache2/logs/error_log +cat /usr/share/apache2/logs/error_log echo "done." echo "notifying client..." -echo "server ready" | /usr/bin/netcat -c 192.168.0.10 8000 +echo "server ready" | netcat -c 192.168.0.10 8000 echo "done" echo -n "starting bash shell..." diff --git a/configs/boot/surge-client.rcS b/configs/boot/surge-client.rcS index c63cc93f0..ba7d87f66 100755 --- a/configs/boot/surge-client.rcS +++ b/configs/boot/surge-client.rcS @@ -31,10 +31,10 @@ echo "131072" > /proc/sys/fs/file-max echo "done." echo "waiting for server..." -/usr/bin/netcat -c -l -p 8000 +netcat -c -l -p 8000 echo -n "running surge client..." -/bin/bash -c "cd /benchmarks/surge && ./Surge 2 100 1 192.168.0.1 5" +/bin/bash -c "cd /benchmarks/specsurge && ./Surge 2 100 1 192.168.0.1 5" echo "done." echo -n "halting machine" diff --git a/configs/boot/surge-server.rcS b/configs/boot/surge-server.rcS index 234514bd9..140c02fb3 100755 --- a/configs/boot/surge-server.rcS +++ b/configs/boot/surge-server.rcS @@ -41,12 +41,12 @@ mount /dev/hdb1 /z/htdocs echo "done." echo -n "starting httpd..." -/benchmarks/apache2/bin/apachectl start +/usr/sbin/apache2 -f /etc/apache2/httpd.conf -k start sleep 2 -cat /benchmarks/apache2/logs/error_log +cat /usr/share/apache2/logs/error_log echo "done." -echo "server ready" | /usr/bin/netcat -c 192.168.10 8000 +echo "server ready" | netcat -c 192.168.10 8000 echo -n "starting bash shell..." /bin/bash diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index e86cc05f5..193d3a5e5 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -83,14 +83,15 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): return self -def makeDualRoot(testSystem, driveSystem): +def makeDualRoot(testSystem, driveSystem, dumpfile): self = Root() self.testsys = testSystem self.drivesys = driveSystem - - self.etherdump = EtherDump(file='ethertrace') self.etherlink = EtherLink(int1 = Parent.testsys.tsunami.etherint[0], - int2 = Parent.drivesys.tsunami.etherint[0], - dump = Parent.etherdump) + int2 = Parent.drivesys.tsunami.etherint[0]) + if dumpfile: + self.etherdump = EtherDump(file=dumpfile) + self.etherlink.dump = Parent.etherdump + self.clock = '1THz' return self diff --git a/configs/example/fs.py b/configs/example/fs.py index 92d2e29e6..312a96d38 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -47,6 +47,9 @@ parser.add_option("-b", "--benchmark", action="store", type="string", dest="benchmark", help="Specify the benchmark to run. Available benchmarks: %s"\ % DefinedBenchmarks) +parser.add_option("--etherdump", action="store", type="string", dest="etherdump", + help="Specify the filename to dump a pcap capture of the ethernet" + "traffic") (options, args) = parser.parse_args() @@ -87,36 +90,37 @@ if len(bm) == 2: s1 = makeLinuxAlphaSystem(mem_mode, bm[0]) s1.cpu = cpu cpu.connectMemPorts(s1.membus) + cpu.mem = s1.physmem s2 = makeLinuxAlphaSystem(mem_mode, bm[1]) s2.cpu = cpu2 cpu2.connectMemPorts(s2.membus) - root = makeDualRoot(s1, s2) + cpu2.mem = s2.physmem + root = makeDualRoot(s1, s2, options.etherdump) elif len(bm) == 1: root = Root(clock = '1THz', system = makeLinuxAlphaSystem(mem_mode, bm[0])) root.system.cpu = cpu cpu.connectMemPorts(root.system.membus) + cpu.mem = root.system.physmem else: print "Error I don't know how to create more than 2 systems." sys.exit(1) m5.instantiate(root) -#exit_event = m5.simulate(2600000000000) -#if exit_event.getCause() != "user interrupt received": -# m5.checkpoint(root, 'cpt') -# exit_event = m5.simulate(300000000000) -# if exit_event.getCause() != "user interrupt received": -# m5.checkpoint(root, 'cptA') - - if options.maxtick: - exit_event = m5.simulate(options.maxtick) + maxtick = options.maxtick elif options.maxtime: simtime = int(options.maxtime * root.clock.value) print "simulating for: ", simtime - exit_event = m5.simulate(simtime) + maxtick = simtime else: - exit_event = m5.simulate() + maxtick = -1 + +exit_event = m5.simulate(maxtick) + +while exit_event.getCause() == "checkpoint": + m5.checkpoint(root, "cpt.%d") + exit_event = m5.simulate(maxtick - m5.curTick()) print 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause() diff --git a/src/SConscript b/src/SConscript index f14ba490c..260aca25c 100644 --- a/src/SConscript +++ b/src/SConscript @@ -94,6 +94,7 @@ base_sources = Split(''' mem/bridge.cc mem/bus.cc + mem/dram.cc mem/mem_object.cc mem/packet.cc mem/physical.cc diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 312b7fc71..304c97f2f 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -679,9 +679,9 @@ decode OP default Unknown::unknown() 0x0: Trap::tcci({{ if(passesCondition(Ccr<3:0>, COND2)) { +#if FULL_SYSTEM int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); -#if FULL_SYSTEM fault = new TrapInstruction(lTrapNum); #else DPRINTF(Sparc, "The syscall number is %d\n", R1); @@ -692,9 +692,9 @@ decode OP default Unknown::unknown() 0x2: Trap::tccx({{ if(passesCondition(Ccr<7:4>, COND2)) { +#if FULL_SYSTEM int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); -#if FULL_SYSTEM fault = new TrapInstruction(lTrapNum); #else DPRINTF(Sparc, "The syscall number is %d\n", R1); diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 70c7e719f..150664148 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -249,7 +249,10 @@ SparcLiveProcess::argsInit(int intSize, int pageSize) Addr envp_array_base = auxv_array_base - envp_array_size; Addr argv_array_base = envp_array_base - argv_array_size; Addr argc_base = argv_array_base - argc_size; +#ifndef NDEBUG + // only used in DPRINTF Addr window_save_base = argc_base - window_save_size; +#endif DPRINTF(Sparc, "The addresses of items on the initial stack:\n"); DPRINTF(Sparc, "0x%x - aux data\n", aux_data_base); diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 8978fef02..a172847df 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -200,8 +200,7 @@ BaseCache::CacheEvent::process() } //Response //Know the packet to send, no need to mark in service (must succed) - bool success = cachePort->sendTiming(pkt); - assert(success); + assert(cachePort->sendTiming(pkt)); } const char * diff --git a/src/mem/dram.cc b/src/mem/dram.cc new file mode 100644 index 000000000..d7b955975 --- /dev/null +++ b/src/mem/dram.cc @@ -0,0 +1,2746 @@ +/* + * Copyright (c) 2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Ron Dreslinski + */ + +/* + Copyright (c) 2000 Computer Engineering and Communication Networks Lab (TIK) + Swiss Federal Institute of Technology (ETH) Zurich, Switzerland + + All rights reserved. + Permission is hereby granted, without written agreement and without + license or royalty fees, to use, copy, modify, and distribute this + software and its documentation for any purpose, provided that the above + copyright notice and the following two paragraphs appear in all copies + of this software. + + IN NO EVENT SHALL THE TIK OR THE ETH ZURICH BE LIABLE TO ANY PARTY + FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES + ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + THE TIK OR THE ETH ZURICH HAVE BEEN ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + + THE TIK AND THE ETH ZURICH SPECIFICALLY DISCLAIM ANY WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE + PROVIDED HEREUNDER IS ON AN "AS IS" BASIS, AND TIK AND THE ETH ZURICH + HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, + ENHANCEMENTS, OR MODIFICATIONS. +*/ + +/* authors: Andreas Romer 4/99 - 7/99 + Matthias Gries 4/99 - 2/01 + + +References: http://www.tik.ee.ethz.ch/ +====================================== +-> Publications http://www.tik.ee.ethz.ch/db/tik/publications/form_search_publications.php3 + + +Matthias Gries: A Survey of Synchronous RAM Architectures. +TIK Report Nr. 71, Computer Engineering and Networks Lab (TIK), +Swiss Federal Institute of Technology (ETH) Zurich, April, 1999 + +-> DRAM survey + + +Matthias Gries, Andreas Romer: Performance Evaluation of Recent +DRAM Architectures for Embedded Systems. +TIK Report Nr. 82, Computer Engineering and Networks Lab (TIK), +Swiss Federal Institute of Technology (ETH) Zurich, November, 1999. + +-> description of the DRAM and controller models for SimpleScalar in the appendix +(note that the current software version additionally supports overlapping in + closed-page mode with slightly modified timing) + + +Matthias Gries: The Impact of Recent DRAM Architectures on Embedded Systems Performance. +Euromicro2000, Symposium on Digital Systems Design, IEEE Computer, Maastricht, Netherlands, +Vol. 1, pages 282-289, September, 2000. + +-> performance study with SimpleScalar + + +Matthias Gries: Modeling a Memory Subsystem with Petri Nets: a Case Study. +A. Yakovlev, L. Gomes, and L. Lavagno (Eds), Hardware Design and Petri Nets, +Kluwer Academic, pages 291-310, March, 2000. + +-> SDRAM + controller performance model as a high-level Petri net +*/ + +/** + * @file + * Definition of a DRAM like main memory. + */ + + +#include "mem/dram.hh" +#include "sim/builder.hh" + +#include <string> + +extern int maxThreadsPerCPU; + +/* SDRAM system: PC100/PC133 2-2-2 DIMM timing according to + PC SDRAM Specification, Rev. 1.7, Intel Corp, Nov. 1999. + + 64 bit DIMM consists of four 16x organized 256 Mbit SDRAMs, 128 MByte of main memory in total.*/ +/* the settings above must be changed if another memory is used */ +/* DRDRAM system: 16 bit channel, four chips (single RIMM), 128 MByte of main memory in total. + Timing: Rambus Inc, Direct RDRAM, preliminary information, 256/288Mbit: 40-800 timing */ + + +#define DR_STACK_BASE 0x8000000 /* total size of memory: 128 Mbyte */ +#define DR_BANK_SIZE 0x100000 /* size of a bank : 1 Mbyte */ +#define DR_ROW_SIZE 0x800 /* size of a row : 2 Kbyte */ +#define DR_NUM_BANKS (DR_STACK_BASE/DR_BANK_SIZE) /* number of banks : 128 */ +#define DR_NUM_ROWS (DR_BANK_SIZE/DR_ROW_SIZE) /* number of rows per bank: 512 */ +#define DR_DATA_BASE 0x4000000 /* Size of textsegment : 64 Mbyte */ +#define DR_NUM_BYTE_MEM 16 /* data packet capacity: 16 byte */ +#define DR_NUM_DEVS 4 /* number of devices along channel */ +#define DR_BANK_SAMP 16 /* 16 banks are together in one group in each device: bank 15 and 16 have no shared SAMPs */ +#define DR_T_PACKET 4 /* number of cycles (in 400 MHz) the memory needs to deliver a data packet */ +#define DR_T_RCD 7 /* RAS to CAS delay */ +#define DR_T_CAC 8 /* read access delay: number of cylces from read to data (trailing to leading edge of packet!) */ +#define DR_T_CWD 6 /* Write delay: number of cylces from write to write data (trailing to leading edge of packet!) */ +#define DR_T_RP 8 /* row precharge delay */ +#define DR_T_RTR 8 /* retire delay*/ +#define DR_T_RDP 4 /* min delay from read to precharge in cycles */ +#define DR_T_PP 8 /* precharge to precharge time to any bank in the same device */ +#define DR_T_RAS 20 /* minimal row active time */ +/*the settings above need to be changed if the memory is altered*/ +#define DR_DYNAMIC_SIZE (DR_STACK_BASE - DR_DATA_BASE) /* size of the heap and stack at most: 64 Mbyte */ +// #define DR_NUM_BANKS (DR_STACK_BASE/DR_BANK_SIZE) /* number of banks : 128 */ +// #define DR_NUM_ROWS (DR_BANK_SIZE/DR_ROW_SIZE) /* number of rows per bank: 512 */ +#define DR_T_OWR (DR_T_CWD + DR_T_PACKET - DR_T_RTR) /* overlap after write retire */ +#define DR_T_HELP (DR_T_CAC+DR_T_PACKET-DR_T_RDP+DR_T_PACKET) /* used for read after read with precharge */ +/*delays until data is ready/written to the memory for the DRDRAM*/ +#define DR_T_READ_READ_SROW (DR_T_CAC + DR_T_PACKET) /* RAR, row hit, current bank */ +#define DR_T_READ_WRITE_SROW (DR_T_CAC + DR_T_PACKET) /* RAW, row hit, current bank */ +#define DR_T_WRITE_READ_SROW (DR_T_CWD + DR_T_PACKET) /* WAR, row hit, current bank */ +#define DR_T_WRITE_WRITE_SROW (DR_T_CWD + DR_T_PACKET) /* WAW, row hit, current bank */ +#define DR_T_READ_READ_SBANK (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET) /* RAR, row miss, current bank */ +#define DR_T_READ_WRITE_SBANK (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET) /* RAW, row miss, current bank */ +#define DR_T_WRITE_READ_SBANK (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET) /* WAR, row miss, current bank */ +#define DR_T_WRITE_WRITE_SBANK (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET) /* WAR, row miss, current bank */ +#define DR_T_READ_READ_OBANK (DR_T_PP+DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET) /* RAR, row miss, another bank */ +#define DR_T_READ_WRITE_OBANK (DR_T_PP+DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET) /* RAW, row miss, another bank */ +#define DR_T_WRITE_READ_OBANK (DR_T_PP+DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET) /* WAR, row miss, another bank */ +#define DR_T_WRITE_WRITE_OBANK (DR_T_PP+DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET) /* WAR, row miss, another bank */ +/* best-case latencies (due to overlap / row hits in another bank) */ +#define DR_BEST_T_READ_READ_SROW 0 /* RAR, row hit, current bank */ +#define DR_BEST_T_READ_WRITE_SROW (DR_T_CAC+DR_T_PACKET-DR_T_OWR) /* RAW, row hit, current bank */ +#define DR_BEST_T_WRITE_READ_SROW 0 /* WAR, row hit, current bank */ +#define DR_BEST_T_WRITE_WRITE_SROW (DR_T_CWD+DR_T_PACKET-DR_T_OWR) /* WAR, row hit, current bank */ +#define DR_BEST_T_READ_READ_SBANK (DR_T_RCD + DR_T_CAC) /* RAR, row miss, current bank */ +#define DR_BEST_T_READ_WRITE_SBANK (DR_T_RP-DR_T_OWR+DR_T_RCD+DR_T_CAC+DR_T_PACKET) /* RAW, row miss, current bank */ +#define DR_BEST_T_WRITE_READ_SBANK (DR_T_RCD+DR_T_CWD) /* WAR, row miss, current bank */ +#define DR_BEST_T_WRITE_WRITE_SBANK (DR_T_RP-DR_T_OWR+DR_T_RCD+DR_T_CWD+DR_T_PACKET) /* WAW, row miss, current bank */ +#define DR_BEST_T_READ_READ_OBANK 0 /* RAR, row miss/hit, another bank */ +#define DR_BEST_T_READ_WRITE_OBANK (DR_T_PACKET+DR_T_CAC-DR_T_OWR) /* RAW, row miss/hit, another bank */ +#define DR_BEST_T_WRITE_READ_OBANK 0 /* WAR, row miss/hit, another bank */ +#define DR_BEST_T_WRITE_WRITE_OBANK 0 /* WAW, row miss/hit, another bank */ +#define DR_BEST_T_READ_WRITE_ODEV (DR_T_CAC-DR_T_CWD) /* RAW, row miss/hit, another device */ + + +#define MIN(a,b) ((a<b) ? a : b) +#define SD_ROW_SIZE 0x1000 /* size of a row : 4 Kbyte */ + + + +DRAMMemory::DRAMMemory(Params *p) + : PhysicalMemory(p), cpu_ratio(p->cpu_ratio), bus_width(p->bus_width), + mem_type(p->mem_type), mem_actpolicy(p->mem_actpolicy), + memctrladdr_type(p->memctrladdr_type), act_lat(p->act_lat), + cas_lat(p->cas_lat), war_lat(p->war_lat), + pre_lat(p->pre_lat), dpl_lat(p->dpl_lat), + trc_lat(p->trc_lat), num_banks(p->num_banks), + num_cpus(p->num_cpus), last_dev(DR_NUM_DEVS+1), + lastCmdIsRead(true), precharge(0), same_row_read_access(0), srr_after_read(0), + srr_after_write(0), same_row_write_access(0), srw_after_read(0), + srw_after_write(0), same_bank_read_access(0), sbr_after_read(0), + sbr_after_write(0), same_bank_write_access(0), sbw_after_read(0), + sbw_after_write(0), other_bank_read_access_hit(0), obr_after_read_hit(0), + obr_after_write_hit(0), other_bank_write_access_hit(0), + obw_after_read_hit(0), obw_after_write_hit(0), obr_after_read_miss(0), + obr_after_write_miss(0), + obw_after_read_miss(0), obw_after_write_miss(0), total_access(0), + adjacent_access(0), adjacent_read(0), adjacent_write(0), + command_overlapping(0), best_case(0), in_between_case(0), worst_case(0), + full_overlapping(0), partial_overlapping(0), mem_access_details(false), + memctrlpipe_enable(false), time_last_access(0) +{ + warn("This DRAM module has not been tested with the new memory system at all!"); + bank_size = (params()->addrRange.size() + 1) / num_banks; + num_rows = bank_size / SD_ROW_SIZE; /* 0x1000 size of row 4Kbtye */ + active_row = new int[num_banks]; + last_bank = num_banks+1; + last_row = num_rows; + busy_until = new Tick[num_banks]; + memset(busy_until,0,sizeof(Tick)*num_banks); /* initiliaze */ + +} + +void +DRAMMemory::regStats() +{ + using namespace Stats; + + accesses + .init(maxThreadsPerCPU) + .name(name() + ".accesses") + .desc("total number of accesses") + .flags(total) + ; + + bytesRequested + .init(maxThreadsPerCPU) + .name(name() + ".bytes_requested") + .desc("total number of bytes requested") + .flags(total) + ; + + bytesSent + .init(maxThreadsPerCPU) + .name(name() + ".bytes_sent") + .desc("total number of bytes sent") + .flags(total) + ; + + compressedAccesses + .init(maxThreadsPerCPU) + .name(name() + ".compressed_responses") + .desc("total number of accesses that are compressed") + .flags(total) + ; + + // stats for power modelling + cycles_nCKE + .init(1) + .name(name() + ".cycles_nCKE") + .desc("cycles when CKE is low") + .flags(total) + ; + + cycles_all_precharge_CKE + .init(1) + .name(name() + ".cycles_all_precharge_CKE") + .desc("cycles when all banks precharged") + .flags(total) + ; + + cycles_all_precharge_nCKE + .init(1) + .name(name() + ".cycles_all_precharge_nCKE") + .desc("cycles when all banks precharged and CKE is low") + .flags(total) + ; + + cycles_bank_active_nCKE + .init(1) + .name(name() + ".cycles_bank_active_nCKE") + .desc("cycles when banks active and CKE low") + .flags(total) + ; + + // we derive this from other stats later + // so DR TODO for now this counter is unused + cycles_avg_ACT + .init(1) + .name(name() + ".cycles_avg_ACT") + .desc("avg cycles between ACT commands") + .flags(total) + ; + + cycles_read_out + .init(1) + .name(name() + ".cycles_read_out") + .desc("cycles outputting read data") + .flags(total) + ; + + cycles_write_in + .init(1) + .name(name() + ".cycles_write_in") + .desc("cycles inputting write data") + .flags(total) + ; + + cycles_between_misses + .init(1) + .name(name() + ".cycles_between_misses") + .desc("cycles between open page misses") + .flags(total) + ; + + other_bank_read_access_miss + .init(1) + .name(name() + ".other_bank_read_access_miss") + .desc("read miss count") + .flags(total) + ; + + other_bank_write_access_miss + .init(1) + .name(name() + ".other_bank_write_access_miss") + .desc("write miss count") + .flags(total) + ; + + // DR TODO for now, only output stats which are involved in power equations + total_latency + .name(name() + ".total_latency") + .desc("total DRAM latency") + ; + + total_arb_latency + .name(name() + ".total_arb_latency") + .desc("total arbitration latency") + ; + + avg_latency + .name(name() + ".avg_latency") + .desc("average DRAM latency") + ; + + avg_arb_latency + .name(name() + ".avg_arb_latency") + .desc("average arbitration DRAM latency") + ; + + bank_access_profile + .init(num_banks,num_cpus) + .name(name() + "[cpu][bank]") + .desc("DRAM bank access profile") + ; + + total_icache_req + .name(name() + ".total_icache_req") + .desc("total number of requests from icache") + ; + + avg_latency = total_latency / accesses; + avg_arb_latency = total_arb_latency / accesses; +} + + + + +// DR DEBUG: assume we have a 500 MHz CPU and 100 MHz RAM +// static float cpu_ratio = 5; // ratio between CPU speed and memory bus speed +// DR TODO: get this parameter from the simulation + +static char *mem_access_output=NULL; + /* latency of access [CPU cycles]*/ +Tick +DRAMMemory::calculateLatency(Packet *pkt) +{ + + bool cmdIsRead = pkt->isRead(); + + int lat=0, temp=0, current_bank=0; + int current_row=0, current_device=0; + + int was_miss = 0; // determines if there was an active row miss this access + + //md_addr_t physic_address; /* linear memory address to be accessed */ + Addr physic_address; /* linear memory address to be accessed */ + + int num_blocks=0; + int corrected_overlap, /* overlap of consecutive accesses [CPU cycles] */ + overlap=0; /* overlap of consecutive accesses [mem bus cycles] */ + int adjacent=0; /* 1 indicates that current bank is adjacent to the last accessed one*/ + + int chunks = (pkt->getSize() + (bus_width - 1)) / bus_width; // burst length + assert(chunks >0); + physic_address = pkt->getAddr(); + + /////////////////////////////////////////////////////////////////////////// + // DR added more stats for power modelling + // NOTE: + // for DRAM closed-page, automatic precharge after read or write, + // i.e. whenever idle + + + // count number of cycles where dram is not busy, use for CKE low signal + // calculate as percentage of all clock cycles + // if busy, do not add to idle count. Else add cycles since last access +/* #define SD_NUM_BANKS (SD_STACK_BASE/SD_BANK_SIZE) */ /* number of banks */ +/* #define SD_NUM_ROWS (SD_BANK_SIZE/SD_ROW_SIZE) */ /* number of rows per bank */ +/*delays until data is ready/written to the memory for the SDRAM*/ + int SD_T_READ_READ_SROW = cas_lat; /* RAR, row hit, current bank */ + int SD_T_READ_WRITE_SROW = cas_lat; /* RAW, row hit, current bank */ + int SD_T_WRITE_READ_SROW = war_lat-1; /* WAR, row hit, current bank */ + int SD_T_WRITE_WRITE_SROW = 0; /* WAW, row hit, current bank */ + int SD_T_READ_READ_SBANK = (pre_lat+act_lat+cas_lat); /* RAR, row miss, current bank */ + int SD_T_READ_WRITE_SBANK = (pre_lat+act_lat+cas_lat+(dpl_lat-1)); /* RAW, row miss, current bank */ + int SD_T_WRITE_READ_SBANK = (pre_lat+act_lat); /* WAR, row miss, current bank */ + int SD_T_WRITE_WRITE_SBANK = (pre_lat+act_lat+(dpl_lat-1)); /* WAW, row miss, current bank */ + int SD_T_READ_READ_OBANK = (pre_lat+act_lat+cas_lat); /* RAR, row miss, another bank */ + int SD_T_READ_WRITE_OBANK = (pre_lat+act_lat+cas_lat); /* RAW, row miss, another bank */ + int SD_T_WRITE_READ_OBANK = (pre_lat+act_lat); /* WAR, row miss, another bank */ + int SD_T_WRITE_WRITE_OBANK = (pre_lat+act_lat); /* WAW, row miss, another bank */ +/* best-case latencies (due to overlap / row hits in another bank) */ + int SD_BEST_T_READ_READ_SROW = 0; /* RAR, row hit, current bank */ + int SD_BEST_T_READ_READ_SBANK = (act_lat+cas_lat); /* RAR, row miss, current bank */ + int SD_BEST_T_WRITE_READ_SBANK = (act_lat); /* WAR, row miss, current bank */ + int SD_BEST_T_READ_READ_OBANK = 0; /* RAR, row miss/hit, another bank */ + int SD_BEST_T_READ_WRITE_OBANK = cas_lat; /* RAW, row miss/hit, another bank */ + int SD_BEST_T_WRITE_READ_OBANK = (war_lat -1); /* WAR, row miss/hit, another bank */ + int SD_BEST_T_WRITE_WRITE_OBANK = 0; /* WAW, row miss/hit, another bank */ + + Tick time_since_last_access = curTick-time_last_access; + Tick time_last_miss = 0; // used for keeping track of times between activations (page misses) + //int was_idle = (curTick > busy_until); + bool srow_flag = false; + int timing_correction = 0; + + int was_idle = (curTick > busy_until[current_bank]); + cycles_nCKE[0] += was_idle ? MIN(curTick-busy_until[current_bank], time_since_last_access) : 0; + + // bank is precharged + //active_row[current_bank] == DR_NUM_ROWS + int all_precharged = 1; + int bank_max = num_banks; + int row_max = num_rows; + + if( (mem_type == "SDRAM") && (mem_actpolicy == "closed") ) { + // SDRAM does not use the active_row array in closed_page mode + // TODO: handle closed page operation + + } else { // DRDRAM uses the active_row array + for( int i = 0; i < bank_max; i++ ) { + if( (active_row[current_bank] != row_max)) all_precharged = 0; + } + } + + if(all_precharged) { + if(was_idle) { + cycles_all_precharge_nCKE[0] += MIN(curTick-busy_until[current_bank], time_since_last_access); + cycles_all_precharge_CKE[0] += MIN(0, busy_until[current_bank]-time_last_access); + } + else { + cycles_all_precharge_CKE[0] += time_since_last_access; + } + } else { // some bank is active + if(was_idle) { + cycles_bank_active_nCKE[0] += MIN(curTick-busy_until[current_bank], time_since_last_access); + } + else { + } + } + + if( cmdIsRead ) { + cycles_read_out[0] += chunks; + } else { + cycles_write_in[0] += chunks; + } + + + time_last_access = curTick; + //////////////////////////////////////////////////////////////////////////// + + if ((mem_type == "SDRAM") && (mem_actpolicy == "open")) + { + /* Split transaction on m5 makes it challenging to */ + /* model the DRAM. A single cycle latency is assumed */ + /* for dequeueing an address bus request. In response to */ + /* that, the current DRAM implementation assumes that a */ + /* seperate DRAM command generator / controller exists per */ + /* bank and the dequeued addresses are queued to these */ + /* controllers. We can view this as an ideal scenario for */ + /* a shared DRAM command generator / controller with */ + /* support for overlapping DRAM commands. */ + /* Compare DRAM PRE,ACT,CAS etc. latencies, DRAM clock */ + /* frequency and the number of banks to determine whether */ + /* the ideal scenario with a shared DRAM command generator */ + /* is equivalent to having multiple DRAM command generators */ + /* per bank */ + if ((memctrladdr_type != "interleaved"))/* i.e. mc_type is linear */ + { + current_bank=physic_address/bank_size; + temp=physic_address-current_bank*bank_size;/*address in bank*/ + current_row=temp/SD_ROW_SIZE; + } + else/* mc_type interleaved */ + /* This memory controller maps the addresses differently + * depending on the row_size, every row is mapped to another + * bank. Thus, the text segment uses half of every bank, the heap + * the next quarter of each bank, and the stack the rest. + */ + + { + num_blocks = physic_address/SD_ROW_SIZE; /* row number */ + current_bank=num_blocks%num_banks; + current_row=num_blocks/num_banks; + } + + if (mem_access_details == true) + { + // DR TODO + //fprintf(mem_accessfd," %09u %4d %3d\n",physic_address,current_row,current_bank); + } + else + { + if (mem_access_output!=0) + { + //fprintf(mem_accessfd,"\n"); + } + } + total_access++; + + if (memctrlpipe_enable == true) + { + overlap=(int)(busy_until[current_bank] - curTick); + } + else overlap = 0; + + if (cpu_ratio < 1.0) + { + corrected_overlap = overlap*((int)(1/cpu_ratio)); /* floor */ + } + else + { + corrected_overlap = (int) (overlap/cpu_ratio); + } + + /*fprintf(stderr,"%10.0f %10.0f %4d %4d ",(double)busy_until, (double)curTick, overlap, corrected_overlap); debugging*/ + + if (cmdIsRead == lastCmdIsRead)/*same command*/ + { + if (current_bank == last_bank)/*same bank*/ + { + if (current_row == last_row)/*same row*/ + { + /* Page Hit */ + if (cmdIsRead) + { + if (corrected_overlap > 0)/*overlapping*/ + { + /*best case*/ + if (corrected_overlap >= cas_lat) + { + lat=SD_BEST_T_READ_READ_SROW; + srow_flag = true; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = cas_lat-corrected_overlap; + srow_flag = true; + in_between_case++; + partial_overlapping++; + } + } + else + { + /*worst case*/ + lat = SD_T_READ_READ_SROW; + srow_flag = true; + worst_case++; + } + same_row_read_access++; + srr_after_read++; + } + else/*write*/ + {/*no option case*/ + lat = SD_T_WRITE_WRITE_SROW; + srow_flag = true; + same_row_write_access++; + srw_after_write++; + worst_case++; + } + } + else /*other row in same bank*/ + { + /* Page miss */ + if (cmdIsRead) + { + if (corrected_overlap > 0)/*overlapping*/ + { + if (corrected_overlap >= pre_lat)/*best case*/ + { + lat = SD_BEST_T_READ_READ_SBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = SD_T_READ_READ_SBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = SD_T_READ_READ_SBANK; + worst_case++; + } + same_bank_read_access++; + sbr_after_read++; + } + else/*write*/ + {/*no option case*/ + lat = SD_T_WRITE_WRITE_SBANK; + same_bank_write_access++; + sbw_after_write++; + worst_case++; + } + } + } + else /*other bank*/ + { + if (cmdIsRead) + { + /* Page empty */ + if (current_row == active_row[current_bank])/*row is still active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= pre_lat)/*best case*/ + { + lat = SD_BEST_T_READ_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = SD_T_READ_READ_OBANK - corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*in between case*/ + { + lat = SD_T_READ_READ_OBANK; + in_between_case++; + } + other_bank_read_access_hit++; + obr_after_read_hit++; + } + else/*row is not active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= SD_T_READ_READ_OBANK )/*best case*/ + { + lat = SD_BEST_T_READ_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = SD_T_READ_READ_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = SD_T_READ_READ_OBANK; + worst_case++; + } + + // DR keep track of time between misses + was_miss = 1; + + other_bank_read_access_miss[0]++; + obr_after_read_miss++; + } + } + else/*write*/ + { + if (current_row == active_row[current_bank])/*row is still active*/ + { /*best_case*/ + lat = SD_BEST_T_WRITE_WRITE_OBANK; + best_case++; + other_bank_write_access_hit++; + obw_after_write_hit++; + } + else/*row is not active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >=SD_T_WRITE_WRITE_OBANK)/*best case*/ + { + lat = SD_BEST_T_WRITE_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = SD_T_WRITE_WRITE_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = SD_T_WRITE_WRITE_OBANK; + worst_case++; + } + + // DR keep track of time between misses + was_miss = 1; + + other_bank_write_access_miss[0]++; + obw_after_write_miss++; + + } + } + } + } + else /*lastCmdIsRead != cmdIsRead*/ + { + if (current_bank == last_bank)/*same bank*/ + { + if (current_row == last_row)/*same row*/ + { + /* Page Hit */ + if (cmdIsRead) + {/*worst case*/ + lat = SD_T_READ_WRITE_SROW; + srow_flag = true; + same_row_read_access++; + srr_after_write++; + worst_case++; + } + else/*write*/ + {/*worst case*/ + lat = SD_T_WRITE_READ_SROW; + srow_flag = true; + same_row_write_access++; + srw_after_read++; + worst_case++; + } + } + else /*other row in same bank*/ + { + /* Page Miss */ + if (cmdIsRead) + {/*worst case*/ + lat = SD_T_READ_WRITE_SBANK; + same_bank_read_access++; + sbr_after_write++; + worst_case++; + } + else/*write*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if (corrected_overlap >= pre_lat)/*best case*/ + { + lat = SD_BEST_T_WRITE_READ_SBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = SD_T_WRITE_READ_SBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = SD_T_WRITE_READ_OBANK; + worst_case++; + } + same_bank_write_access++; + sbw_after_read++; + } + } + } + else /*other bank*/ + { + /* Page empty */ + if (cmdIsRead) + { + if (current_row == active_row[current_bank])/*row is still active*/ + { /*best case*/ + lat = SD_BEST_T_READ_WRITE_OBANK; + best_case++; + other_bank_read_access_hit++; + obr_after_write_hit++; + } + else/*row is not active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (pre_lat+act_lat))/*best case*/ + { + lat = SD_BEST_T_READ_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = SD_T_READ_WRITE_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = SD_T_READ_WRITE_OBANK; + worst_case++; + } + // DR keep track of time between misses + was_miss = 1; + + other_bank_read_access_miss[0]++; + obr_after_write_miss++; + } + } + else/*write*/ + { + if (current_row == active_row[current_bank])/*row is still active*/ + { /*best case*/ + lat = SD_BEST_T_WRITE_READ_OBANK; + best_case++; + other_bank_write_access_hit++; + obw_after_read_hit++; + } + else/*row is not active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if (corrected_overlap >= (SD_T_WRITE_READ_OBANK-SD_BEST_T_WRITE_READ_OBANK))/*best case*/ + {/*best case*/ + lat = SD_BEST_T_WRITE_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = SD_T_WRITE_READ_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = SD_T_WRITE_READ_OBANK; + worst_case++; + } + + // DR keep track of time between misses + was_miss = 1; + + other_bank_write_access_miss[0]++; + obw_after_read_miss++; + } + } + } + } + /*fprintf(stderr,"%4d %4d ",lat,active_row[current_bank]);debugging*/ + + lat += chunks; /* burst length added*/ + if(srow_flag == false) + timing_correction = cpu_ratio*(trc_lat - pre_lat - act_lat - cas_lat - 1); + + + /*fprintf(stderr,"%4d ",lat);debugging*/ + + active_row[current_bank]=current_row; /* open-page (hit) register */ + lastCmdIsRead = cmdIsRead; + last_bank = current_bank; + last_row = current_row; + + if (cpu_ratio < 1.0) + { + lat = (lat+((int)(1/cpu_ratio)-1))/(int)(1/cpu_ratio); + } + else + { + temp = (int)(lat*cpu_ratio); + lat = (lat*cpu_ratio == temp)?temp:(temp+1); /*round up*/ + } + + /*fprintf(stderr,"%4d \n",lat);debugging*/ + + if (overlap <= 0) /*memory interface is not busy*/ + { + if (memctrlpipe_enable == true) + { + busy_until[current_bank]=curTick+lat+ + timing_correction; + } + else + { + if (busy_until[current_bank] >= curTick) + { + busy_until[current_bank]+=(lat+ + timing_correction); + total_arb_latency += (busy_until[current_bank] + - curTick - lat + - timing_correction); + lat=busy_until[current_bank] - curTick; + } + else busy_until[current_bank]=curTick+lat+ + timing_correction; + } + } + else/*the memory request will be satisfied temp cycles after curTick*/ + { + busy_until[current_bank] +=(lat+ + timing_correction); + command_overlapping++; + lat+=overlap; + total_arb_latency += overlap; + } + + // DR for power stats + if( was_miss ) { + cycles_between_misses[0] += (busy_until[current_bank] - time_last_miss); + time_last_miss = busy_until[current_bank]; + } + // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl; + // if((_cpu_num < num_cpus) && (_cpu_num >= 0)) + // bank_access_profile[_cpu_num][current_bank]++; + + return lat; + } + + + /***********************************************************/ + /******************** DRDRAM ***********************/ + /***********************************************************/ + + else if ((mem_type == "DRDRAM") && (mem_actpolicy == "open"))/*DRDRAM*/ /*a closed bank has an activ_row number of DR_NUM_ROWS: highest +1*/ + { + if ((memctrladdr_type != "interleaved"))/* i.e. mc_type is linear */ + { + current_bank=physic_address/DR_BANK_SIZE; + temp=physic_address-current_bank*DR_BANK_SIZE;/*address in bank*/ + current_row=temp/DR_ROW_SIZE; + current_device=current_bank/(DR_NUM_BANKS/DR_NUM_DEVS); + } + + else/*mc_type interleaved*/ + /* This memory controller maps the addresses differently + * depending on the row-size, every row is mapped to another + * bank. So the text segment uses half of every bank. The heap + * the next quarter of each bank and the stack the rest. + */ + + { + num_blocks = physic_address/DR_ROW_SIZE; /* row number */ + current_bank=(num_blocks%DR_NUM_BANKS)*2; /*every 'second' bank will be used*/ + /*banks above DR_NUM_BANKS are the uneven banks*/ + current_bank = ((current_bank < DR_NUM_BANKS) ? current_bank:(current_bank - DR_NUM_BANKS+1)); + current_row=num_blocks/DR_NUM_BANKS; + current_device=current_bank/(DR_NUM_BANKS/DR_NUM_DEVS); + } + if (abs(current_bank-last_bank)==1)/*access to an adjacent bank*/ + { + if (!((current_bank%DR_BANK_SAMP == (DR_BANK_SAMP-1))&&(last_bank%DR_BANK_SAMP == 0))/*not 15/16 (current/last)*/ + &&(!((last_bank%DR_BANK_SAMP == (DR_BANK_SAMP-1))&&(current_bank%DR_BANK_SAMP == 0))))/*not 16/15(current/last)*/ + { + adjacent_access++; + adjacent=1;/*an adjacent bank is accessed*/ + if (cmdIsRead) + adjacent_read++; + else + adjacent_write++; + } + } + precharge=0;/*at this moment no bank needs to be precharged*/ + if (active_row[current_bank] == DR_NUM_ROWS)/*bank is precharged*/ + { + if (prechargeBanksAround(current_bank)> 0)/*a bank next to the current is activated*/ + { + if ((adjacent==1)&&(precharge==1)) + { + /*since adjacent banks share SAMPs, this access would be the same as (in terms of latency) + *an access to another row in the same bank if only one adjacent bank was active*/ + last_bank = current_bank; + last_row = current_row+1; + precharge=0;/*set to 0 for next memory access*/ + } + } + } + if (mem_access_details == true) + { + //fprintf(mem_accessfd," %09u %4d %3d %15d\n",physic_address,current_row,current_bank,(int)adjacent_access); + } + else + { + if (mem_access_output!=NULL) + { + //fprintf(mem_accessfd,"\n"); + } + } + total_access++; + + if (memctrlpipe_enable == true) + { + overlap=(int)(busy_until[current_bank] - curTick); + } + else overlap=0; + + if (cpu_ratio < 1.0) + { + corrected_overlap = overlap*((int)(1/cpu_ratio)); /* floor */ + } + else + { + corrected_overlap = (int) (overlap/cpu_ratio); + } + + /*fprintf(stderr,"%10.0f %10.0f %6d %6d %2d %2d ",(double)busy_until, (double)curTick, overlap, corrected_overlap,precharge,adjacent);debugging*/ + + if (cmdIsRead == lastCmdIsRead)/*same command*/ + { + if (current_bank == last_bank)/*same bank*/ + { + if (current_row == last_row)/*same row*/ + { + if (cmdIsRead) + { + if (corrected_overlap > 0)/*overlapping*/ + { + /*best case*/ + if (corrected_overlap >= DR_T_READ_READ_SROW) + { + lat=DR_BEST_T_READ_READ_SROW; + srow_flag = true; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_READ_READ_SROW-corrected_overlap; + srow_flag = true; + in_between_case++; + partial_overlapping++; + } + } + else + { + /*worst case*/ + lat = DR_T_READ_READ_SROW; + srow_flag = true; + worst_case++; + } + same_row_read_access++; + srr_after_read++; + } + else/*write, always retire the previous data*/ + { + if (corrected_overlap > 0)/*overlapping*/ + { + /*best case*/ + if (corrected_overlap >= DR_T_OWR) + { + lat=DR_BEST_T_WRITE_WRITE_SROW; + srow_flag = true; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_WRITE_WRITE_SROW-corrected_overlap; + srow_flag = true; + in_between_case++; + partial_overlapping++; + } + } + else + { + /*worst case*/ + lat = DR_T_WRITE_WRITE_SROW; + srow_flag = true; + worst_case++; + } + same_row_write_access++; + srw_after_write++; + } + } + else /*other row in same bank*/ + { + if (cmdIsRead) + { + if (corrected_overlap > 0)/*overlapping*/ + { + if (corrected_overlap >= DR_T_HELP)/*best case*/ + { + lat = DR_BEST_T_READ_READ_SBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_READ_READ_SBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_READ_READ_SBANK; + worst_case++; + } + same_bank_read_access++; + sbr_after_read++; + } + else/*write*/ + { + if (corrected_overlap > 0)/*overlapping*/ + { + if (corrected_overlap >= DR_T_OWR)/*best case*/ + { + lat = DR_BEST_T_WRITE_WRITE_SBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_WRITE_WRITE_SBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_WRITE_WRITE_SBANK; + worst_case++; + } + same_bank_write_access++; + sbw_after_write++; + } + } + } + else /*other bank*/ + { + if (cmdIsRead) + { + if (current_row == active_row[current_bank])/*row is still active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_CAC+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_READ_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_CAC+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*in between case*/ + { + lat = DR_T_CAC+DR_T_PACKET; + in_between_case++; + } + other_bank_read_access_hit++; + obr_after_read_hit++; + } + else/*row is not active or bank is precharged/not active*/ + { + if (active_row[current_bank]!=DR_NUM_ROWS)/*row is not active, but bank is active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_READ_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET; + in_between_case++; + } + } + else/*current_row == DR_NUM_ROWS:precharged or inactive*/ + { + if(precharge == 0)/*no adjacent bank is active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_RCD+DR_T_CAC+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_READ_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_RCD+DR_T_CAC+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_RCD+DR_T_CAC+DR_T_PACKET; + in_between_case++; + } + } + else/*one ore two adjacent banks are active*/ + { + if (precharge == 1) + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_READ_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET)-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET); + in_between_case++; + } + } + else /*precharge ==2: two rows must be precharged*/ + { + if (adjacent == 1)/*these banks are adjacent*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= DR_T_PP+2*DR_T_PACKET-DR_T_RDP+DR_T_CAC)/*best case*/ + { + lat = DR_T_RDP+DR_T_RP+DR_T_RCD-DR_T_PACKET; + in_between_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_READ_READ_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_READ_READ_OBANK; + worst_case++; + } + } + else/*adjacent == 0: two not adjacent banks need to be precharged*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= DR_T_READ_READ_OBANK)/*best case*/ + { + lat = DR_BEST_T_READ_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_READ_READ_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_READ_READ_OBANK; + worst_case++; + } + } + } + } + } + other_bank_read_access_miss[0]++; + obr_after_read_miss++; + } + } + else/*write*/ + { + if (current_row == active_row[current_bank])/*row is still active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_WRITE_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_CWD+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_CWD+DR_T_PACKET; + in_between_case++; + } + other_bank_write_access_hit++; + obw_after_write_hit++; + } + else/*row is not active or bank is precharged/not active*/ + { + if (active_row[current_bank] != DR_NUM_ROWS)/*row is not active,but bank is active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_WRITE_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET; + in_between_case++; + } + } + else/*current_row == DR_NUM_ROWS:precharged or inactive*/ + { + if(precharge == 0)/*no adjacent bank is active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_RCD+DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_WRITE_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_RCD+DR_T_CWD+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_RCD+DR_T_CWD+DR_T_PACKET; + in_between_case++; + } + } + else/*one ore two adjacent banks are active*/ + { + if (precharge == 1)/*last_bank is no adjacent*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_WRITE_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET)-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET); + in_between_case++; + } + } + else /*precharge ==2: two rows have to be precharged*/ + { + if (adjacent == 1)/*these banks are adjacent*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= DR_T_OWR+DR_T_PP)/*best case*/ + { + lat = DR_T_WRITE_WRITE_OBANK-DR_T_OWR-DR_T_PP; + in_between_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_WRITE_WRITE_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_WRITE_WRITE_OBANK; + worst_case++; + } + } + else/*adjacent == 0: two not adjacent banks need to be precharged*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= DR_T_WRITE_WRITE_OBANK)/*best case*/ + { + lat = DR_BEST_T_WRITE_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_WRITE_WRITE_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_WRITE_WRITE_OBANK; + worst_case++; + } + } + } + } + } + other_bank_write_access_miss[0]++; + obw_after_write_miss++; + } + } + } + } + else /*lastCmdIsRead != cmdIsRead*/ + { + if (current_bank == last_bank)/*same bank*/ + { + if (current_row == last_row)/*same row*/ + { + if (cmdIsRead) + { + if (corrected_overlap > 0)/*overlapping*/ + { + /*best case*/ + if (corrected_overlap >= DR_T_OWR) + { + lat=DR_BEST_T_READ_WRITE_SROW; + srow_flag = true; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_READ_WRITE_SROW-corrected_overlap; + srow_flag = true; + in_between_case++; + partial_overlapping++; + } + } + else + { + /*worst case*/ + lat = DR_T_READ_WRITE_SROW; + srow_flag = true; + worst_case++; + } + same_row_read_access++; + srr_after_write++; + } + else/*write*/ + { + if (corrected_overlap > 0)/*overlapping*/ + { + /*best case*/ + if (corrected_overlap >= DR_T_WRITE_READ_SROW) + { + lat=DR_BEST_T_WRITE_READ_SROW; + srow_flag = true; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_WRITE_READ_SROW-corrected_overlap; + srow_flag = true; + in_between_case++; + partial_overlapping++; + } + } + else + { + /*worst case*/ + lat = DR_T_WRITE_READ_SROW; + srow_flag = true; + worst_case++; + } + same_row_write_access++; + srw_after_read++; + } + } + else /*other row in same bank*/ + { + if (cmdIsRead) + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if (corrected_overlap >= DR_T_OWR)/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_SBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_READ_WRITE_SBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_READ_WRITE_SBANK; + worst_case++; + } + same_bank_read_access++; + sbr_after_write++; + } + else/*write*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if (corrected_overlap >= DR_T_HELP)/*best case*/ + { + lat = DR_BEST_T_WRITE_READ_SBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_WRITE_READ_SBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_WRITE_READ_SBANK; + worst_case++; + } + same_bank_write_access++; + sbw_after_read++; + } + } + } + else /*other bank*/ + { + if (cmdIsRead) + { + if (current_row == active_row[current_bank])/*row is still active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(last_dev != current_device) + { + if(corrected_overlap >= DR_T_CWD+DR_T_PACKET)/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_ODEV; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_CAC+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else /* same device */ + { + if(corrected_overlap >= DR_T_OWR)/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_CAC+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + } + else/*in between case, no overlap*/ + { + lat = DR_T_CAC+DR_T_PACKET; + in_between_case++; + } + other_bank_read_access_hit++; + obr_after_write_hit++; + } + + else/*row is not active or bank is precharged/not active*/ + { + if (active_row[current_bank] != DR_NUM_ROWS)/*row is not active,but bank is active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if (last_dev != current_device) + { + if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_ODEV; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else /* same device */ + { + if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_OWR))/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + } + else/*worst case*/ + { + lat = DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET; + in_between_case++; + } + } + else/*current_row == DR_NUM_ROWS:precharged or inactive*/ + { + if(precharge == 0)/*no adjacent bank is active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(last_dev != current_device) + { + if(corrected_overlap >= (DR_T_RCD+DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_ODEV; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_RCD+DR_T_CAC+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else /* same device */ + { + if(corrected_overlap >= (DR_T_RCD+DR_T_OWR))/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_RCD+DR_T_CAC+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + } + else/*worst case*/ + { + lat = DR_T_RCD+DR_T_CAC+DR_T_PACKET; + in_between_case++; + } + } + else/*one or two adjacent banks are active*/ + { + if (precharge == 1)/*an adjacent bank (!=last_bank) needs to be precharged*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(last_dev != current_device) + { + if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_ODEV; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET)-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else /* same device */ + { + if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_OWR))/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET)-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + } + else/*worst case*/ + { + lat = (DR_T_RP+DR_T_RCD+DR_T_CAC+DR_T_PACKET); + in_between_case++; + } + } + else /*precharge ==2: two rows have to be precharged*/ + { + if (adjacent == 1) /* the banks are adjacent */ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= DR_T_OWR + DR_T_PP)/*best case*/ + { + lat = DR_T_READ_WRITE_OBANK-DR_T_OWR - DR_T_PP; + in_between_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_READ_WRITE_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_READ_WRITE_OBANK; + worst_case++; + } + } + else/*adjacent == 0: two not adjacent banks need to be precharged*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if (last_dev != current_device) + { + if(corrected_overlap >= (DR_T_PP+DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_ODEV; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_READ_WRITE_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else /* same device */ + { + if(corrected_overlap >= (DR_T_PP+DR_T_RP+DR_T_RCD+DR_T_OWR))/*best case*/ + { + lat = DR_BEST_T_READ_WRITE_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_READ_WRITE_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + } + else/*worst case*/ + { + lat = DR_T_READ_WRITE_OBANK; + worst_case++; + } + } + } + } + } + other_bank_read_access_miss[0]++; + obr_after_write_miss++; + } + } + else/*write*/ + { + if (current_row == active_row[current_bank])/*row is still active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= DR_T_CWD+DR_T_PACKET)/*best case*/ + { + lat = DR_BEST_T_WRITE_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_CWD+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*in between case*/ + { + lat = DR_T_CWD+DR_T_PACKET; + in_between_case++; + } + other_bank_write_access_hit++; + obw_after_read_hit++; + } + else/*row is not active or bank is precharged/not active*/ + { + if (active_row[current_bank] != DR_NUM_ROWS)/*row is not active,but bank is active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_WRITE_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET; + in_between_case++; + } + } + else/*current_row == DR_NUM_ROWS:precharged or inactive*/ + { + if(precharge == 0)/*no adjacent bank is active*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_RCD+DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_WRITE_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_RCD+DR_T_CWD+DR_T_PACKET-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_RCD+DR_T_CWD+DR_T_PACKET; + in_between_case++; + } + } + else/*one or two adjacent banks are active*/ + { + if (precharge == 1)/*an adjacent bank (!=last_bank) needs to be precharged first*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET))/*best case*/ + { + lat = DR_BEST_T_WRITE_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET)-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = (DR_T_RP+DR_T_RCD+DR_T_CWD+DR_T_PACKET); + in_between_case++; + } + } + else /*precharge ==2: two rows have to be precharged*/ + { + if (adjacent == 1)/*these banks are adjacent*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= DR_T_PP-DR_T_RDP+2*DR_T_PACKET+DR_T_CAC)/*best case*/ + { + lat = DR_T_WRITE_READ_OBANK-(DR_T_PP-DR_T_RDP+2*DR_T_PACKET+DR_T_CAC); + in_between_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_WRITE_READ_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_WRITE_READ_OBANK; + worst_case++; + } + } + else/*adjacent == 0: two not adjacent banks need to be precharged*/ + { + if (corrected_overlap > 0 )/*overlapping*/ + { + if(corrected_overlap >= DR_T_WRITE_READ_OBANK)/*best case*/ + { + lat = DR_BEST_T_WRITE_READ_OBANK; + best_case++; + full_overlapping++; + } + else/*in between case*/ + { + lat = DR_T_WRITE_READ_OBANK-corrected_overlap; + in_between_case++; + partial_overlapping++; + } + } + else/*worst case*/ + { + lat = DR_T_WRITE_READ_OBANK; + worst_case++; + } + } + } + } + } + other_bank_write_access_miss[0]++; + obw_after_read_miss++; + } + } + } + } + /*fprintf(stderr,"%4d %4d ",lat,active_row[current_bank]);debugging*/ + + lat += chunks * DR_T_PACKET; /*every 128 bit need DR_NUM_CYCLES*/ + + /*fprintf(stderr,"%4d ",lat);debugging*/ + + if (cpu_ratio < 1.0) + { + lat = (lat+((int)(1/cpu_ratio)-1))/(int)(1/cpu_ratio); + } + else + { + temp = (int)(lat*cpu_ratio); + lat = (lat*cpu_ratio == temp)?temp:(temp+1); /*round up*/ + } + + active_row[current_bank]=current_row; + lastCmdIsRead = cmdIsRead; + last_bank=current_bank; + last_row = current_row; + last_dev = current_device; + + /*fprintf(stderr,"%4d \n",lat);debugging*/ + + if (overlap <= 0) /*memory interface is not busy*/ + { + if (memctrlpipe_enable == true) + { + busy_until[current_bank] =curTick+lat; + } + else + { + if (busy_until[current_bank] >= curTick) + { + busy_until[current_bank] +=lat; + lat=busy_until[current_bank] - curTick; + } + else busy_until[current_bank] = curTick+lat; + } + } + else/*the memory request will be satisfied temp cycles after curTick*/ + { + busy_until[current_bank] +=lat; + command_overlapping++; + lat+=overlap; + } + + // if((_cpu_num < num_cpus) && (_cpu_num >= 0)) + // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl; + // bank_access_profile[_cpu_num][current_bank]++; + return lat; + } + + /******************************************************************/ + + else if ((mem_type== "SDRAM") && (mem_actpolicy == "closed") && (memctrlpipe_enable == true)) + /* SDRAM closed-page with overlap, 2/00 MG */ + { + if ((memctrladdr_type != "interleaved"))/* i.e. mc_type is linear*/ + { + // current_bank=physic_address/SD_BANK_SIZE; + current_bank=physic_address/bank_size; + } + else/*mc_type interleaved*/ + /* This memory management unit maps the addresses different + * depending on the row_size, every row is mapped to another + * bank. So the text segment uses half of every bank. The heap + * the next quarter of each bank and the stack the rest. + */ + { + num_blocks = physic_address/SD_ROW_SIZE; /* row number */ + // current_bank=num_blocks%SD_NUM_BANKS; + current_bank=num_blocks%num_banks; + } + + if (mem_access_details == true) + { + //fprintf(mem_accessfd," %09u %3d\n",physic_address,current_bank); + } + else + { + if (mem_access_output!=NULL) + { + //fprintf(mem_accessfd,"\n"); + } + } + total_access++; + + overlap=(int)(busy_until[current_bank] - curTick); + + if (current_bank == last_bank)/*same bank*/ + { + if ((lastCmdIsRead == cmdIsRead) && (cmdIsRead))/* RAR */ + { + lat = act_lat + cas_lat; + } + else if ((lastCmdIsRead == cmdIsRead) && (!cmdIsRead)) /* WAW */ + { + lat = act_lat; + } + else if ((lastCmdIsRead != cmdIsRead) && (cmdIsRead)) /* RAW */ + { + lat = act_lat + cas_lat; + } + else /* WAR */ + { + lat = act_lat; + } + } + else /* other bank */ + { + if (cpu_ratio < 1.0) + { + corrected_overlap = overlap*((int)(1/cpu_ratio)); /* floor */ + } + else + { + corrected_overlap = (int) (overlap/cpu_ratio); + } + + if ((lastCmdIsRead == cmdIsRead) && (cmdIsRead))/* RAR */ + { + if (corrected_overlap > act_lat + cas_lat) + { + lat = 0; + best_case++; + full_overlapping++; + } + else if (corrected_overlap > 0) + { + lat = act_lat + cas_lat - corrected_overlap; + in_between_case++; + partial_overlapping++; + } + else + { + lat = act_lat + cas_lat; + worst_case++; + } + } + else if ((lastCmdIsRead == cmdIsRead) && (!cmdIsRead)) /* WAW */ + { + if (corrected_overlap > act_lat + pre_lat + (dpl_lat-1)) + { + lat = - pre_lat - dpl_lat +1; + best_case++; + full_overlapping++; + } + else if (corrected_overlap > 0) + { + lat = act_lat - corrected_overlap; + in_between_case++; + partial_overlapping++; + } + else + { + lat = act_lat; + worst_case++; + } + } + else if ((lastCmdIsRead != cmdIsRead) && (cmdIsRead)) /* RAW */ + { + if (corrected_overlap > cas_lat + pre_lat + dpl_lat - 1 ) + { + lat = act_lat - (pre_lat + dpl_lat - 1); + best_case++; + partial_overlapping++; + } + else if (corrected_overlap > 0) + { + lat = act_lat + cas_lat - corrected_overlap; + in_between_case++; + partial_overlapping++; + } + else + { + lat = act_lat + cas_lat; + worst_case++; + } + } + else /* WAR */ + { + if (corrected_overlap > act_lat - (dpl_lat-1)) + { + lat = dpl_lat-1; + best_case++; + partial_overlapping++; + } + else if (corrected_overlap > 0) + { + lat = act_lat - corrected_overlap; + in_between_case++; + partial_overlapping++; + } + else + { + lat = act_lat; + worst_case++; + } + } + } + lastCmdIsRead = cmdIsRead; + last_bank=current_bank; + last_row = current_row; + + lat += chunks; + + if (cpu_ratio < 1.0) + { + lat = (lat+((int)(1/cpu_ratio)-1))/(int)(1/cpu_ratio); + } + else + { + temp = (int)(lat*cpu_ratio); + lat = (lat*cpu_ratio == temp)?temp:(temp+1); /*round up*/ + } + + /*fprintf(stderr,"%4d \n",lat); debugging */ + + if (overlap <= 0) /*memory interface is not busy*/ + { + busy_until[current_bank] = curTick+lat; + } + else /*the memory request will be satisfied temp cycles after curTick*/ + { + busy_until[current_bank] +=lat; + command_overlapping++; + total_arb_latency += overlap; + lat+=overlap; + } + if (!cmdIsRead) + { + temp = (int)(((dpl_lat-1) + pre_lat)*cpu_ratio); + busy_until[current_bank] += (((dpl_lat-1) + pre_lat)*cpu_ratio == temp)?temp:(temp+1); + } + + + + /*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick, overlap, lat);debug*/ + // if((_cpu_num < num_cpus) && (_cpu_num >= 0)) + // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl; + // bank_access_profile[_cpu_num][current_bank]++; + return lat; + } + + /******************************************************************/ + + else if ((mem_type == "DRDRAM") && (mem_actpolicy == "closed") && (memctrlpipe_enable == true)) + /* DRDRAM closed-page with overlap*/ + { + + if ((memctrladdr_type != "interleaved"))/*i.e. mc_type is linear*/ + { + current_bank=physic_address/DR_BANK_SIZE; + current_device=current_bank/(DR_NUM_BANKS/DR_NUM_DEVS); + } + else/*mc_type interleaved*/ + /* This memory management unit maps the addresses different + * depending on the row-size, every row is mapped to another + * bank. So the text segment uses half of every bank. The heap + * the next quarter of each bank and the stack the rest. + */ + { + num_blocks = physic_address/DR_ROW_SIZE; /* row number */ + current_bank=(num_blocks%DR_NUM_BANKS)*2; /*every 'second' bank will be used*/ + /*banks above DR_NUM_BANKS are the uneven banks*/ + current_bank = ((current_bank < DR_NUM_BANKS) ? current_bank:(current_bank - DR_NUM_BANKS+1)); + current_device=current_bank/(DR_NUM_BANKS/DR_NUM_DEVS); + } + + + if (mem_access_details == true) + { + //fprintf(mem_accessfd," %09u %3d \n",physic_address,current_bank); + } + else + { + if (mem_access_output!=NULL) + { + //fprintf(mem_accessfd,"\n"); + } + } + total_access++; + + overlap=(int)(busy_until[current_bank] - curTick); + + if (cpu_ratio < 1.0) + { + corrected_overlap = overlap*((int)(1/cpu_ratio)); /* floor */ + } + else + { + corrected_overlap = (int) (overlap/cpu_ratio); + } + + if (current_bank == last_bank)/*same bank*/ + { + if ((lastCmdIsRead == cmdIsRead) && (cmdIsRead))/* RAR */ + { + lat = DR_T_RCD + DR_T_CAC + DR_T_PACKET; + worst_case++; + } + else if ((lastCmdIsRead == cmdIsRead) && (!cmdIsRead)) /* WAW */ + { + lat = DR_T_RCD + DR_T_CWD + DR_T_PACKET; + worst_case++; + } + else if ((lastCmdIsRead != cmdIsRead) && (cmdIsRead)) /* RAW */ + { + lat = DR_T_RCD + DR_T_CAC + DR_T_PACKET; + worst_case++; + } + else /* WAR */ + { + lat = DR_T_RCD + DR_T_CWD + DR_T_PACKET; + worst_case++; + } + } + else /* other bank */ + { + if ((lastCmdIsRead == cmdIsRead) && (cmdIsRead))/* RAR */ + { + if (corrected_overlap > DR_T_RAS + DR_T_RP - 2 * DR_T_PACKET) + { + lat = - DR_T_RAS + DR_T_RCD + DR_T_PACKET + DR_T_CAC; + best_case++; + full_overlapping++; + } + else if (corrected_overlap > 0) + { + lat = DR_T_RCD + DR_T_CAC + DR_T_PACKET - corrected_overlap; + in_between_case++; + partial_overlapping++; + } + else + { + lat = DR_T_RCD + DR_T_CAC + DR_T_PACKET; + worst_case++; + } + } + else if ((lastCmdIsRead == cmdIsRead) && (!cmdIsRead)) /* WAW */ + { + if (corrected_overlap > DR_T_RCD + DR_T_RTR + DR_T_RP) + { + lat = - DR_T_CWD - 2 * DR_T_PACKET + DR_T_RTR; + best_case++; + full_overlapping++; + } + else if (corrected_overlap > 0) + { + lat = DR_T_RCD + DR_T_CWD + DR_T_PACKET - corrected_overlap; + in_between_case++; + partial_overlapping++; + } + else + { + lat = DR_T_RCD + DR_T_CWD + DR_T_PACKET; + worst_case++; + } + } + else if ((lastCmdIsRead != cmdIsRead) && (cmdIsRead)) /* RAW */ + { + if (current_device == last_dev) /* same device */ + { + if (corrected_overlap > DR_T_RCD + DR_T_RP) + { + lat = DR_T_PACKET + DR_T_CAC - DR_T_RP; + best_case++; + partial_overlapping++; + } + else if (corrected_overlap > 0) + { + lat = DR_T_RCD + DR_T_CAC + DR_T_PACKET - corrected_overlap; + in_between_case++; + partial_overlapping++; + } + else + { + lat = DR_T_RCD + DR_T_CAC + DR_T_PACKET; + worst_case++; + } + } + else /* other device */ + { + if (corrected_overlap > DR_T_RCD + DR_T_RP + 2 * DR_T_PACKET) + { + lat = - DR_T_PACKET + DR_T_CAC - DR_T_RP; + best_case++; + partial_overlapping++; + } + else if (corrected_overlap > 0) + { + lat = DR_T_RCD + DR_T_CAC + DR_T_PACKET - corrected_overlap; + in_between_case++; + partial_overlapping++; + } + else + { + lat = DR_T_RCD + DR_T_CAC + DR_T_PACKET; + worst_case++; + } + } + } + else /* WAR */ + { + if (corrected_overlap > DR_T_RAS + DR_T_RP - 2 * DR_T_PACKET - (DR_T_CAC - DR_T_CWD)) + { + lat = - DR_T_RAS + DR_T_RCD + DR_T_PACKET + DR_T_CAC; + best_case++; + full_overlapping++; + } + else if (corrected_overlap > 0) + { + lat = DR_T_RCD + DR_T_CWD + DR_T_PACKET - corrected_overlap; + in_between_case++; + partial_overlapping++; + } + else + { + lat = DR_T_RCD + DR_T_CWD + DR_T_PACKET; + worst_case++; + } + } + } + + lat += chunks * DR_T_PACKET; /*every 128 bit need DR_NUM_CYCLES*/ + + /*fprintf(stderr,"%4d ",lat);debugging*/ + + if (cpu_ratio < 1.0) + { + lat = (lat+((int)(1/cpu_ratio)-1))/(int)(1/cpu_ratio); + } + else + { + temp = (int)(lat*cpu_ratio); + lat = (lat*cpu_ratio == temp)?temp:(temp+1); /*round up*/ + } + + lastCmdIsRead=cmdIsRead; + last_bank=current_bank; + last_dev = current_device; + + /*fprintf(stderr,"%4d \n",lat);debugging*/ + + if (overlap <= 0) /*memory interface is not busy*/ + { + busy_until[current_bank] = curTick+lat; + } + else/*the memory request will be satisfied temp cycles after curTick*/ + { + busy_until[current_bank] +=lat; + command_overlapping++; + lat+=overlap; + } + + /*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick, overlap, lat);*/ + + if (cmdIsRead) + { + if (cpu_ratio < 1.0) + { + busy_until[current_bank] += abs(((DR_T_RAS - (DR_T_RCD + DR_T_PACKET + DR_T_CAC)) + 1)/((int)(1/cpu_ratio))); /* CPU clock cycles */ + } + else + { + busy_until[current_bank] += (int) abs(((DR_T_RAS - (DR_T_RCD + DR_T_PACKET + DR_T_CAC)) + 1)*cpu_ratio); /* CPU clock cycles */ + } + } + else /* !cmdIsRead */ + { + if (cpu_ratio < 1.0) + { + busy_until[current_bank] += abs((-DR_T_PACKET + DR_T_RTR + DR_T_RP - DR_T_CWD + 1)/((int)(1/cpu_ratio))); /* CPU clock cycles */ + } + else + { + busy_until[current_bank] += (int) abs((-DR_T_PACKET + DR_T_RTR + DR_T_RP - DR_T_CWD + 1)*cpu_ratio); /* CPU clock cycles */ + } + } + + // if((_cpu_num < num_cpus) && (_cpu_num >= 0)) + // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl; + // bank_access_profile[_cpu_num][current_bank]++; + return lat; + } + + /******************************************************************/ + + else if ((mem_type == "SDRAM") && (mem_actpolicy == "closed") && (memctrlpipe_enable == false)) + /* SDRAM closed-page without overlap, 7/99 MG */ + { + if (mem_access_output != NULL) + { + //fprintf(mem_accessfd,"\n"); + } + assert(chunks >0); + + if (cmdIsRead) + { + lat = act_lat + cas_lat; + } + else /* !cmdIsRead */ + { + lat = act_lat; + } + total_access++; + lat += chunks; + + overlap=(int)(busy_until[current_bank] - curTick); + lastCmdIsRead=cmdIsRead; + + if (cpu_ratio < 1.0) + { + lat = (lat+((int)(1/cpu_ratio)-1))/(int)(1/cpu_ratio); + } + else + { + temp = (int)(lat*cpu_ratio); + lat = (lat*cpu_ratio == temp)?temp:(temp+1); /*round up*/ + } + + if (overlap <= 0) /*memory interface is not busy*/ + { + busy_until[current_bank] = curTick+lat; + } + else/*the memory request will be satisfied temp cycles after curTick*/ + { + busy_until[current_bank] +=lat; + command_overlapping++; + lat+=overlap; + } + if (!cmdIsRead) + { + temp = (int)(((dpl_lat-1) + pre_lat)*cpu_ratio); + busy_until[current_bank] += (((dpl_lat-1) + pre_lat)*cpu_ratio == temp)?temp:(temp+1); + } + + // if((_cpu_num < num_cpus) && (_cpu_num >= 0)) + // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl; + // bank_access_profile[_cpu_num][current_bank]++; + return lat; + } + + /******************************************************************/ + + else if ((mem_type == "DRDRAM") && (mem_actpolicy == "closed") && (memctrlpipe_enable == false)) + /* DRDRAM closed-page without overlap */ + { + if (cmdIsRead) + { + lat = DR_T_RCD + DR_T_CAC + DR_T_PACKET; /* DR_T_RP + */ + } + else /* !cmdIsRead */ + { + lat = DR_T_RCD + DR_T_CWD + DR_T_PACKET; /* DR_T_RP + */ + } + total_access++; + overlap=(int)(busy_until[current_bank] - curTick); + lat += chunks * DR_T_PACKET; /*every 128 bit need DR_NUM_CYCLES*/ + + if (cpu_ratio < 1.0) + { + lat = (lat+((int)(1/cpu_ratio)-1))/(int)(1/cpu_ratio); + } + else + { + temp = (int)(lat*cpu_ratio); + lat = (lat*cpu_ratio == temp)?temp:(temp+1); /*round up*/ + } + + lastCmdIsRead=cmdIsRead; + + if (overlap <= 0) /*memory interface is not busy*/ + { + busy_until[current_bank] = curTick+lat; + } + else/*the memory request will be satisfied temp cycles after curTick*/ + { + busy_until[current_bank] += lat; + command_overlapping++; + lat+=overlap; + } + + if (cmdIsRead) + { + if (cpu_ratio < 1.0) + { + busy_until[current_bank] += abs(((DR_T_RAS - (DR_T_RCD + DR_T_PACKET + DR_T_CAC)) + 1)/((int)(1/cpu_ratio))); /* CPU clock cycles */ + } + else + { + busy_until[current_bank] += (int) abs(((DR_T_RAS - (DR_T_RCD + DR_T_PACKET + DR_T_CAC)) + 1)*cpu_ratio); /* CPU clock cycles */ + } + } + else /* !cmdIsRead */ + { + if (cpu_ratio < 1.0) + { + busy_until[current_bank] += abs((-DR_T_PACKET + DR_T_RTR + DR_T_RP - DR_T_CWD + 1)/((int)(1/cpu_ratio))); /* CPU clock cycles */ + } + else + { + busy_until[current_bank] += (int) abs((-DR_T_PACKET + DR_T_RTR + DR_T_RP - DR_T_CWD + 1)*cpu_ratio); /* CPU clock cycles */ + } + } + // if((_cpu_num < num_cpus) && (_cpu_num >= 0)) + // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl; + // bank_access_profile[_cpu_num][current_bank]++; + return lat; + } + + /******************************************************************/ + + else /*STD*/ + { + if (mem_access_output != NULL) + { + //fprintf(mem_accessfd,"\n"); + } + assert(chunks >0); + // if((_cpu_num < num_cpus) && (_cpu_num >= 0)) + // cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl; + // bank_access_profile[_cpu_num][current_bank]++; + return(/* first chunk latency */act_lat + + (/* remainder chunk latency */cas_lat * (chunks - 1))); + } + +} + +/*end added by ar, MG*/ + +/*begin added by ar, MG*/ + +/* ================ helper functions ========================= */ + +/****** DRDRAM specific: shared sense amplifiers ******/ +/* precharges the adjacent banks and returns the number of them (1 or 2)*/ +int /*number of precharged banks*/ +DRAMMemory::prechargeBanksAround(int bank)/*access to bank */ +{ +int temp; + +temp=bank%DR_BANK_SAMP; + +if (temp == 0) /*bank 0, 16,32 ....*/ + { + if (active_row[bank+1]!=DR_NUM_ROWS) + { + precharge++; + active_row[bank+1]=DR_NUM_ROWS; + } + } +else + { + if (temp==DR_BANK_SAMP-1)/*banks 15,31 ...*/ + { + if (active_row[bank-1]!=DR_NUM_ROWS) + { + precharge++; + active_row[bank-1]=DR_NUM_ROWS; + } + } + else + { + if (active_row[bank-1]!=DR_NUM_ROWS) + { + precharge++; + active_row[bank-1]=DR_NUM_ROWS; + } + if (active_row[bank+1]!=DR_NUM_ROWS) + { + precharge++; + active_row[bank+1]=DR_NUM_ROWS; + } + } + } +return precharge; +} + + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +BEGIN_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory) + + Param<std::string> file; + Param<Range<Addr> > range; + Param<Tick> latency; + /* additional params for dram protocol*/ + Param<int> cpu_ratio; + Param<std::string> mem_type; + Param<std::string> mem_actpolicy; + Param<std::string> memctrladdr_type; + Param<int> bus_width; + Param<int> act_lat; + Param<int> cas_lat; + Param<int> war_lat; + Param<int> pre_lat; + Param<int> dpl_lat; + Param<int> trc_lat; + Param<int> num_banks; + Param<int> num_cpus; + +END_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory) + +BEGIN_INIT_SIM_OBJECT_PARAMS(DRAMMemory) + + INIT_PARAM_DFLT(file, "memory mapped file", ""), + INIT_PARAM(range, "Device Address Range"), + INIT_PARAM(latency, "Memory access latency"), + + /* additional params for dram protocol*/ + INIT_PARAM_DFLT(cpu_ratio,"ratio between CPU speed and memory bus speed",5), + INIT_PARAM_DFLT(mem_type,"type of DRAM","SDRAM"), + INIT_PARAM_DFLT(mem_actpolicy,"open / closed page policy","open"), + INIT_PARAM_DFLT(memctrladdr_type,"interleaved or direct mapping","interleaved"), + INIT_PARAM_DFLT(bus_width,"memory access bus width",16), + INIT_PARAM_DFLT(act_lat,"RAS to CAS delay",2), + INIT_PARAM_DFLT(cas_lat,"CAS delay",1), + INIT_PARAM_DFLT(war_lat,"write after read delay",2), + INIT_PARAM_DFLT(pre_lat,"precharge delay",2), + INIT_PARAM_DFLT(dpl_lat,"data in to precharge delay",2), + INIT_PARAM_DFLT(trc_lat,"row cycle delay",6), + INIT_PARAM_DFLT(num_banks,"Number of Banks",4), + INIT_PARAM_DFLT(num_cpus,"Number of CPUs connected to DRAM",4) + +END_INIT_SIM_OBJECT_PARAMS(DRAMMemory) + +CREATE_SIM_OBJECT(DRAMMemory) +{ + DRAMMemory::Params *p = new DRAMMemory::Params; + p->name = getInstanceName(); + p->addrRange = range; + p->latency = latency; + + /* additional params for dram */ + p->cpu_ratio = cpu_ratio; + p->bus_width = bus_width; + p->mem_type = mem_type; + p->mem_actpolicy = mem_actpolicy; + p->memctrladdr_type = memctrladdr_type; + p->act_lat = act_lat; + p->cas_lat = cas_lat; + p->war_lat = war_lat; + p->pre_lat = pre_lat; + p->dpl_lat = dpl_lat; + p->trc_lat = trc_lat; + p->num_banks = num_banks; + p->num_cpus = num_cpus; + + return new DRAMMemory(p); +} + +REGISTER_SIM_OBJECT("DRAMMemory", DRAMMemory) + +#endif // DOXYGEN_SHOULD_SKIP_THIS + + diff --git a/src/mem/dram.hh b/src/mem/dram.hh new file mode 100644 index 000000000..32d117596 --- /dev/null +++ b/src/mem/dram.hh @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ron Dreslinski + * Ali Saidi + */ + +/** + * @file + * Derrive a class from PhysicalMemory that support DRAM like timing access. + */ +#ifndef __MEM_DRAM_HH__ +#define __MEM_DRAM_HH__ + +#include "base/statistics.hh" +#include "mem/physical.hh" + +class DRAMMemory : public PhysicalMemory +{ + protected: + /* added for dram support */ + const int cpu_ratio; // ratio between CPU speed and memory bus speed + const int bus_width; // memory access bus width (in bytes) + /* memory access latency (<first_chunk> <inter_chunk>) */ + const std::string mem_type; + const std::string mem_actpolicy; + const std::string memctrladdr_type; + const int act_lat; + const int cas_lat; + const int war_lat; + const int pre_lat; + const int dpl_lat; + const int trc_lat; + const int num_banks; + const int num_cpus; + + int bank_size; + int num_rows; + int *active_row; + int last_bank; + int last_row; + Tick *busy_until; + int last_dev; + bool lastCmdIsRead; + int precharge; + + /* memory access statistics */ + int same_row_read_access; + int srr_after_read; + int srr_after_write; + int same_row_write_access; + int srw_after_read; + int srw_after_write; + + int same_bank_read_access; + int sbr_after_read; + int sbr_after_write; + int same_bank_write_access; + int sbw_after_read; + int sbw_after_write; + + int other_bank_read_access_hit; + int obr_after_read_hit; + int obr_after_write_hit; + int other_bank_write_access_hit; + int obw_after_read_hit; + int obw_after_write_hit; + // DR + // int other_bank_read_access_miss; + int obr_after_read_miss; + int obr_after_write_miss; + // DR + // int other_bank_write_access_miss; + int obw_after_read_miss; + int obw_after_write_miss; + + int total_access; + + int adjacent_access; + int adjacent_read; + int adjacent_write; + int command_overlapping; + int best_case; + int in_between_case; + int worst_case; + int full_overlapping; + int partial_overlapping; + + int mem_access_details; + int memctrlpipe_enable; + + Tick time_last_access; + + + Stats::Vector<> accesses; + Stats::Vector<> bytesRequested; + Stats::Vector<> bytesSent; + Stats::Vector<> compressedAccesses; + + Stats::Vector<> cycles_nCKE; + Stats::Vector<> cycles_all_precharge_CKE; + Stats::Vector<> cycles_all_precharge_nCKE; + Stats::Vector<> cycles_bank_active_nCKE; + Stats::Vector<> cycles_avg_ACT; + Stats::Vector<> cycles_read_out; + Stats::Vector<> cycles_write_in; + Stats::Vector<> cycles_between_misses; + Stats::Vector<> other_bank_read_access_miss; + Stats::Vector<> other_bank_write_access_miss; + Stats::Scalar<> total_latency; + Stats::Scalar<> total_icache_req; + Stats::Scalar<> total_arb_latency; + Stats::Formula avg_latency; + Stats::Formula avg_arb_latency; + Stats::Vector2d<> bank_access_profile; + + + protected: + Tick calculateLatency(Packet *pkt); + int prechargeBanksAround(int bank); + + public: + struct Params : public PhysicalMemory::Params + { + /* additional params for dram protocol*/ + int cpu_ratio; + int bus_width; + + std::string mem_type; /* DRDRAM, SDRAM */ + std::string mem_actpolicy; /* closed, open */ + std::string memctrladdr_type; /* interleaved, anythingelse */ + + int act_lat; + int cas_lat; + int war_lat; + int pre_lat; + int dpl_lat; + int trc_lat; + int num_banks; + int num_cpus; + + }; + virtual void regStats(); + DRAMMemory(Params *p); +}; + +#endif// __MEM_DRAM_HH__ + diff --git a/src/mem/packet.hh b/src/mem/packet.hh index a88c78a78..5d8308df7 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -223,7 +223,7 @@ class Packet bool isNoAllocate() { return (flags & NO_ALLOCATE) != 0; } bool isCompressed() { return (flags & COMPRESSED) != 0; } - bool nic_pkt() { assert("Unimplemented\n" && 0); } + bool nic_pkt() { assert("Unimplemented\n" && 0); return false; } /** Possible results of a packet's request. */ enum Result diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 291c70d8c..f4fbd2fb1 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -54,25 +54,22 @@ using namespace std; using namespace TheISA; -PhysicalMemory::PhysicalMemory(const string &n, Tick latency) - : MemObject(n),base_addr(0), pmem_addr(NULL), port(NULL), lat(latency) +PhysicalMemory::PhysicalMemory(Params *p) + : MemObject(p->name), pmemAddr(NULL), port(NULL), lat(p->latency), _params(p) { - // Hardcoded to 128 MB for now. - pmem_size = 1 << 27; - - if (pmem_size % TheISA::PageBytes != 0) + if (params()->addrRange.size() % TheISA::PageBytes != 0) panic("Memory Size not divisible by page size\n"); int map_flags = MAP_ANON | MAP_PRIVATE; - pmem_addr = (uint8_t *)mmap(NULL, pmem_size, PROT_READ | PROT_WRITE, + pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE, map_flags, -1, 0); - if (pmem_addr == (void *)MAP_FAILED) { + if (pmemAddr == (void *)MAP_FAILED) { perror("mmap"); fatal("Could not mmap!\n"); } - page_ptr = 0; + pagePtr = 0; } void @@ -85,18 +82,18 @@ PhysicalMemory::init() PhysicalMemory::~PhysicalMemory() { - if (pmem_addr) - munmap(pmem_addr, pmem_size); + if (pmemAddr) + munmap(pmemAddr, params()->addrRange.size()); //Remove memPorts? } Addr PhysicalMemory::new_page() { - Addr return_addr = page_ptr << LogVMPageSize; - return_addr += base_addr; + Addr return_addr = pagePtr << LogVMPageSize; + return_addr += params()->addrRange.start; - ++page_ptr; + ++pagePtr; return return_addr; } @@ -107,20 +104,25 @@ PhysicalMemory::deviceBlockSize() return 0; } - Tick +PhysicalMemory::calculateLatency(Packet *pkt) +{ + return lat; +} + +void PhysicalMemory::doFunctionalAccess(Packet *pkt) { - assert(pkt->getAddr() + pkt->getSize() < pmem_size); + assert(pkt->getAddr() + pkt->getSize() < params()->addrRange.size()); switch (pkt->cmd) { case Packet::ReadReq: memcpy(pkt->getPtr<uint8_t>(), - pmem_addr + pkt->getAddr() - base_addr, + pmemAddr + pkt->getAddr() - params()->addrRange.start, pkt->getSize()); break; case Packet::WriteReq: - memcpy(pmem_addr + pkt->getAddr() - base_addr, + memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start, pkt->getPtr<uint8_t>(), pkt->getSize()); // temporary hack: will need to add real LL/SC implementation @@ -134,7 +136,6 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt) } pkt->result = Packet::Success; - return lat; } Port * @@ -181,7 +182,7 @@ PhysicalMemory::getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) { snoop.clear(); resp.clear(); - resp.push_back(RangeSize(base_addr, pmem_size)); + resp.push_back(RangeSize(params()->addrRange.start, params()->addrRange.size())); } int @@ -195,7 +196,9 @@ PhysicalMemory::MemoryPort::recvTiming(Packet *pkt) { assert(pkt->result != Packet::Nacked); - Tick latency = memory->doFunctionalAccess(pkt); + Tick latency = memory->calculateLatency(pkt); + + memory->doFunctionalAccess(pkt); pkt->makeTimingResponse(); sendTiming(pkt, latency); @@ -206,7 +209,8 @@ PhysicalMemory::MemoryPort::recvTiming(Packet *pkt) Tick PhysicalMemory::MemoryPort::recvAtomic(Packet *pkt) { - return memory->doFunctionalAccess(pkt); + memory->doFunctionalAccess(pkt); + return memory->calculateLatency(pkt); } void @@ -232,7 +236,6 @@ PhysicalMemory::serialize(ostream &os) gzFile compressedMem; string filename = name() + ".physmem"; - SERIALIZE_SCALAR(pmem_size); SERIALIZE_SCALAR(filename); // write memory file @@ -248,7 +251,7 @@ PhysicalMemory::serialize(ostream &os) fatal("Insufficient memory to allocate compression state for %s\n", filename); - if (gzwrite(compressedMem, pmem_addr, pmem_size) != pmem_size) { + if (gzwrite(compressedMem, pmemAddr, params()->addrRange.size()) != params()->addrRange.size()) { fatal("Write failed on physical memory checkpoint file '%s'\n", filename); } @@ -269,12 +272,8 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string §ion) const int chunkSize = 16384; - // unmap file that was mmaped in the constructor - munmap(pmem_addr, pmem_size); - string filename; - UNSERIALIZE_SCALAR(pmem_size); UNSERIALIZE_SCALAR(filename); filename = cp->cptDir + "/" + filename; @@ -291,11 +290,15 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string §ion) fatal("Insufficient memory to allocate compression state for %s\n", filename); + // unmap file that was mmaped in the constructor + // This is done here to make sure that gzip and open don't muck with our + // nice large space of memory before we reallocate it + munmap(pmemAddr, params()->addrRange.size()); - pmem_addr = (uint8_t *)mmap(NULL, pmem_size, PROT_READ | PROT_WRITE, + pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0); - if (pmem_addr == (void *)MAP_FAILED) { + if (pmemAddr == (void *)MAP_FAILED) { perror("mmap"); fatal("Could not mmap physical memory!\n"); } @@ -306,19 +309,19 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string §ion) fatal("Unable to malloc memory to read file %s\n", filename); /* Only copy bytes that are non-zero, so we don't give the VM system hell */ - while (curSize < pmem_size) { + while (curSize < params()->addrRange.size()) { bytesRead = gzread(compressedMem, tempPage, chunkSize); - if (bytesRead != chunkSize && bytesRead != pmem_size - curSize) + if (bytesRead != chunkSize && bytesRead != params()->addrRange.size() - curSize) fatal("Read failed on physical memory checkpoint file '%s'" " got %d bytes, expected %d or %d bytes\n", - filename, bytesRead, chunkSize, pmem_size-curSize); + filename, bytesRead, chunkSize, params()->addrRange.size()-curSize); assert(bytesRead % sizeof(long) == 0); for (int x = 0; x < bytesRead/sizeof(long); x++) { if (*(tempPage+x) != 0) { - pmem_current = (long*)(pmem_addr + curSize + x * sizeof(long)); + pmem_current = (long*)(pmemAddr + curSize + x * sizeof(long)); *pmem_current = *(tempPage+x); } } @@ -352,8 +355,11 @@ END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) CREATE_SIM_OBJECT(PhysicalMemory) { - - return new PhysicalMemory(getInstanceName(), latency); + PhysicalMemory::Params *p = new PhysicalMemory::Params; + p->name = getInstanceName(); + p->addrRange = range; + p->latency = latency; + return new PhysicalMemory(p); } REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory) diff --git a/src/mem/physical.hh b/src/mem/physical.hh index b549c1f8b..1489e6700 100644 --- a/src/mem/physical.hh +++ b/src/mem/physical.hh @@ -80,19 +80,28 @@ class PhysicalMemory : public MemObject const PhysicalMemory &operator=(const PhysicalMemory &specmem); protected: - Addr base_addr; - Addr pmem_size; - uint8_t *pmem_addr; + uint8_t *pmemAddr; MemoryPort *port; - int page_ptr; + int pagePtr; Tick lat; public: Addr new_page(); - uint64_t size() { return pmem_size; } + uint64_t size() { return params()->addrRange.size(); } + + struct Params + { + std::string name; + Range<Addr> addrRange; + Tick latency; + }; + + protected: + Params *_params; public: - PhysicalMemory(const std::string &n, Tick latency); + const Params *params() const { return _params; } + PhysicalMemory(Params *p); virtual ~PhysicalMemory(); public: @@ -102,9 +111,9 @@ class PhysicalMemory : public MemObject void virtual init(); unsigned int drain(Event *de); - private: - Tick doFunctionalAccess(Packet *pkt); - + protected: + void doFunctionalAccess(Packet *pkt); + virtual Tick calculateLatency(Packet *pkt); void recvStatusChange(Port::Status status); public: diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 88a8bf5e3..41e90b12b 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -6,7 +6,7 @@ from Bus import Bus class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - mem = Param.MemObject(Parent.any, "memory") + mem = Param.MemObject("memory") system = Param.System(Parent.any, "system object") if build_env['FULL_SYSTEM']: diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py index 9cc7510a2..bc427aa88 100644 --- a/src/python/m5/objects/PhysicalMemory.py +++ b/src/python/m5/objects/PhysicalMemory.py @@ -4,6 +4,24 @@ from MemObject import * class PhysicalMemory(MemObject): type = 'PhysicalMemory' port = Port("the access port") - range = Param.AddrRange("Device Address") + range = Param.AddrRange(AddrRange('128MB'), "Device Address") file = Param.String('', "memory mapped file") latency = Param.Latency(Parent.clock, "latency of an access") + +class DRAMMemory(PhysicalMemory): + type = 'DRAMMemory' + # Many of these should be observed from the configuration + cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed") + mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)") + mem_actpolicy = Param.String("open", "Open/Close policy") + memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct") + bus_width = Param.Int(16, "") + act_lat = Param.Int(2, "RAS to CAS delay") + cas_lat = Param.Int(1, "CAS delay") + war_lat = Param.Int(2, "write after read delay") + pre_lat = Param.Int(2, "precharge delay") + dpl_lat = Param.Int(2, "data in to precharge delay") + trc_lat = Param.Int(6, "row cycle delay") + num_banks = Param.Int(4, "Number of Banks") + num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") + diff --git a/tests/SConscript b/tests/SConscript index 8720939de..b538ec557 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -61,10 +61,12 @@ def check_test(target, source, env): # Exclude m5stats.txt since we will use diff-out on that. Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' + '-I "^command line:" ' + # for stdout file - '-I "^M5 compiled on" ' + # for stderr file - '-I "^M5 simulation started" ' + # for stderr file + '-I "^M5 compiled " ' + # for stderr file + '-I "^M5 started " ' + # for stderr file + '-I "^M5 executing on " ' + # for stderr file '-I "^Simulation complete at" ' + # for stderr file '-I "^Listening for" ' + # for stderr file + '-I "listening for remote gdb" ' + # for stderr file '--exclude=m5stats.txt --exclude=SCCS ' + '--exclude=${TARGETS[0].file} ' + '> ${TARGETS[0]}', target=target, source=source), None) @@ -169,6 +171,7 @@ def test_builder(env, ref_dir): # Prefix test run with batch job submission command if appropriate. # Output redirection is also different for batch runs. # Batch command also supports timeout arg (in seconds, not minutes). + timeout = 15 # used to be a param, probably should be again if env['BATCH']: cmd = [env['BATCH_CMD'], '-t', str(timeout * 60), '-o', cmd_stdout, '-e', cmd_stderr, base_cmd] diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 78dfabe3b..7bb76db0e 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -40,6 +40,7 @@ cpu = TimingSimpleCPU() cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) cpu.mem = cpu.dcache +cpu.mem = cpu.dcache system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 6bcefd74f..e3945f7dc 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -39,5 +39,6 @@ system = FSConfig.makeLinuxAlphaSystem('atomic') system.cpu = cpus for c in cpus: c.connectMemPorts(system.membus) + c.mem = system.physmem root = Root(clock = '2GHz', system = system) diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 67499ac45..ca1dd5c77 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -35,5 +35,6 @@ cpu = AtomicSimpleCPU() system = FSConfig.makeLinuxAlphaSystem('atomic') system.cpu = cpu cpu.connectMemPorts(system.membus) +cpu.mem = system.physmem root = Root(clock = '2GHz', system = system) diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 59a783b3a..967d6a2d2 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -39,5 +39,6 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpus for c in cpus: c.connectMemPorts(system.membus) + c.mem = system.physmem root = Root(clock = '2GHz', system = system) diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 5dba7508d..b3fc9d105 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -35,5 +35,6 @@ cpu = TimingSimpleCPU() system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu cpu.connectMemPorts(system.membus) +cpu.mem = system.physmem root = Root(clock = '2GHz', system = system) diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini new file mode 100644 index 000000000..a530874f5 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -0,0 +1,98 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.physmem +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out new file mode 100644 index 000000000..a3621a08a --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -0,0 +1,93 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.physmem +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 029e66f89..2317e88dc 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2486 # Simulator instruction rate (inst/s) -host_mem_usage 146652 # Number of bytes of host memory used -host_seconds 1.04 # Real time elapsed on the host -host_tick_rate 2484 # Simulator tick rate (ticks/s) +host_inst_rate 58510 # Simulator instruction rate (inst/s) +host_mem_usage 146720 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 57971 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 0b884e31a..d7cbe766c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:05:10 -M5 started Wed Aug 16 14:41:52 2006 +M5 compiled Aug 18 2006 00:06:43 +M5 started Fri Aug 18 00:12:48 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Exiting @ tick 2577 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini new file mode 100644 index 000000000..fe8183125 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -0,0 +1,214 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +system=system +workload=system.cpu.workload + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out new file mode 100644 index 000000000..09d8f0c22 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -0,0 +1,214 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.cpu.dcache +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..40ce485d3 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -0,0 +1,213 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 37119 # Simulator instruction rate (inst/s) +host_mem_usage 158176 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 54058 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2578 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 3777 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 2918912699678311424 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 361 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 160540198482307121152 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.132212 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.132212 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4476343852030456320 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 120861284004822319104 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 54 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 7.658537 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 710 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3431725396184505344 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.demand_hits 628 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 281401482487129440256 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.115493 # miss rate for demand accesses +system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.115493 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 710 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3431725396184505344 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 628 # number of overall hits +system.cpu.dcache.overall_miss_latency 281401482487129440256 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.115493 # miss rate for overall accesses +system.cpu.dcache.overall_misses 82 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.115493 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use +system.cpu.dcache.total_refs 628 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3447887748754160128 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 562005703046928072704 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 326 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 14.822086 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3447887748754160128 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 562005703046928072704 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses +system.cpu.icache.demand_misses 163 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3447887748754160128 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 2416 # number of overall hits +system.cpu.icache.overall_miss_latency 562005703046928072704 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses +system.cpu.icache.overall_misses 163 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 93.126257 # Cycle average of tags in use +system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 490 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 245 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 490 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 245 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 490 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 245 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 146.200635 # Cycle average of tags in use +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.num_insts 2578 # Number of instructions executed +system.cpu.num_refs 710 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr new file mode 100644 index 000000000..c2154cff2 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8 +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout new file mode 100644 index 000000000..1dfd9ca29 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Aug 18 2006 00:06:43 +M5 started Sun Aug 20 01:42:05 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +Exiting @ tick 3777 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini new file mode 100644 index 000000000..d845c0efb --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -0,0 +1,98 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.physmem +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/tru64/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out new file mode 100644 index 000000000..ae24ae2a8 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -0,0 +1,93 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.physmem +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt new file mode 100644 index 000000000..2317e88dc --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 58510 # Simulator instruction rate (inst/s) +host_mem_usage 146720 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 57971 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2578 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 2577 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 2578 # number of cpu cycles simulated +system.cpu.num_insts 2578 # Number of instructions executed +system.cpu.num_refs 710 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr new file mode 100644 index 000000000..c2154cff2 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8 +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout new file mode 100644 index 000000000..d7cbe766c --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Aug 18 2006 00:06:43 +M5 started Fri Aug 18 00:12:48 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +Exiting @ tick 2577 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini new file mode 100644 index 000000000..fe8183125 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -0,0 +1,214 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +system=system +workload=system.cpu.workload + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out new file mode 100644 index 000000000..09d8f0c22 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -0,0 +1,214 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.cpu.dcache +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt new file mode 100644 index 000000000..5b851e100 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -0,0 +1,213 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 39478 # Simulator instruction rate (inst/s) +host_mem_usage 158176 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 57469 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2578 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 3777 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 2918912699678311424 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 361 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 160540198482307121152 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.132212 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.132212 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4476343852030456320 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 120861284004822319104 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 54 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 7.658537 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 710 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3431725396184505344 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.demand_hits 628 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 281401482487129440256 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.115493 # miss rate for demand accesses +system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.115493 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 710 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3431725396184505344 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 628 # number of overall hits +system.cpu.dcache.overall_miss_latency 281401482487129440256 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.115493 # miss rate for overall accesses +system.cpu.dcache.overall_misses 82 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.115493 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use +system.cpu.dcache.total_refs 628 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3447887748754160128 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 562005703046928072704 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 326 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 14.822086 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3447887748754160128 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 562005703046928072704 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses +system.cpu.icache.demand_misses 163 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3447887748754160128 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 2416 # number of overall hits +system.cpu.icache.overall_miss_latency 562005703046928072704 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses +system.cpu.icache.overall_misses 163 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 93.126257 # Cycle average of tags in use +system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 490 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 245 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 490 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 245 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 490 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 245 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 146.200635 # Cycle average of tags in use +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.num_insts 2578 # Number of instructions executed +system.cpu.num_refs 710 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr new file mode 100644 index 000000000..c2154cff2 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8 +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout new file mode 100644 index 000000000..d4669aed9 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Aug 18 2006 00:06:43 +M5 started Fri Aug 18 00:12:48 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +Exiting @ tick 3777 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini new file mode 100644 index 000000000..f0eb69e7f --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -0,0 +1,98 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.physmem +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/mips/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out new file mode 100644 index 000000000..8678c0d97 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -0,0 +1,93 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/mips/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.physmem +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index 5659ba97e..a45e5a877 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6870 # Simulator instruction rate (inst/s) -host_mem_usage 147292 # Number of bytes of host memory used -host_seconds 0.82 # Real time elapsed on the host -host_tick_rate 6865 # Simulator tick rate (ticks/s) +host_inst_rate 124620 # Simulator instruction rate (inst/s) +host_mem_usage 147356 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 122794 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index 9414b5014..12a95eebc 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:10:25 -M5 started Wed Aug 16 14:41:57 2006 +M5 compiled Aug 18 2006 00:09:15 +M5 started Fri Aug 18 00:12:56 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/test/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic +command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Exiting @ tick 5656 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini new file mode 100644 index 000000000..ab77b14a7 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -0,0 +1,214 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +system=system +workload=system.cpu.workload + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/mips/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out new file mode 100644 index 000000000..a7270a97e --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -0,0 +1,214 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/mips/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.cpu.dcache +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..e497ba79b --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -0,0 +1,214 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 67697 # Simulator instruction rate (inst/s) +host_mem_usage 158936 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 102046 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5657 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 8573 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 1791574296802328064 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 141534369447383908352 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.069850 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 79 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 158 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.069850 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 79 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 933 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2766176443076198912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 875 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 160438233698419539968 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.062165 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 100 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.053591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 14.065693 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2204179585005864704 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1927 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 301972603145803464704 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.066376 # miss rate for demand accesses +system.cpu.dcache.demand_misses 137 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 258 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.062500 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 129 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2204179585005864704 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1927 # number of overall hits +system.cpu.dcache.overall_miss_latency 301972603145803464704 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.066376 # miss rate for overall accesses +system.cpu.dcache.overall_misses 137 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 258 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.062500 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 129 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 91.822487 # Cycle average of tags in use +system.cpu.dcache.total_refs 1927 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 1549898021785231104 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.993399 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 469619100600925028352 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 604 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 1549898021785231104 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency +system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 469619100600925028352 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses +system.cpu.icache.demand_misses 303 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 604 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 1549898021785231104 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 5355 # number of overall hits +system.cpu.icache.overall_miss_latency 469619100600925028352 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses +system.cpu.icache.overall_misses 303 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 604 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 13 # number of replacements +system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 138.188010 # Cycle average of tags in use +system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 440 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 1.963470 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 860 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995455 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 438 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 430 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977273 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 430 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004566 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 440 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 1.963470 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 860 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995455 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 438 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 430 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.977273 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 440 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 1.963470 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 860 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995455 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 438 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 430 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.977273 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 430 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 231.300093 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.num_insts 5657 # Number of instructions executed +system.cpu.num_refs 2055 # Number of memory references +system.cpu.workload.PROG:num_syscalls 13 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr new file mode 100644 index 000000000..f33d007a7 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr @@ -0,0 +1,2 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout new file mode 100644 index 000000000..b9431269e --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello World! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Aug 18 2006 00:09:15 +M5 started Fri Aug 18 00:12:56 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing +Exiting @ tick 8573 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..c22373526 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,98 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.physmem +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/sparc/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out new file mode 100644 index 000000000..45412a511 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -0,0 +1,93 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/sparc/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.physmem +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index 27de77ab6..1a605634b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3565 # Simulator instruction rate (inst/s) -host_mem_usage 147204 # Number of bytes of host memory used -host_seconds 1.25 # Real time elapsed on the host -host_tick_rate 3564 # Simulator tick rate (ticks/s) +host_inst_rate 73574 # Simulator instruction rate (inst/s) +host_mem_usage 147268 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 73065 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4450 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 6c17750cc..b1a7c18f8 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:15:12 -M5 started Wed Aug 16 14:42:01 2006 +M5 compiled Aug 18 2006 00:11:48 +M5 started Fri Aug 18 00:12:59 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/test/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Exiting @ tick 4449 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index a0cc28b23..8b48b8a92 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1386533 # Simulator instruction rate (inst/s) -host_mem_usage 194484 # Number of bytes of host memory used -host_seconds 45.63 # Real time elapsed on the host -host_tick_rate 77934911 # Simulator tick rate (ticks/s) +host_inst_rate 1433278 # Simulator instruction rate (inst/s) +host_mem_usage 194568 # Number of bytes of host memory used +host_seconds 44.14 # Real time elapsed on the host +host_tick_rate 80562367 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 63264995 # Number of instructions simulated sim_seconds 1.778030 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 4dab1dfbd..d503ac399 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:33:58 -M5 started Wed Aug 16 14:38:40 2006 +M5 compiled Aug 17 2006 23:41:21 +M5 started Thu Aug 17 23:50:27 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Exiting @ tick 3556060806 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 6e83016e9..a4b2a851b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1410348 # Simulator instruction rate (inst/s) -host_mem_usage 194320 # Number of bytes of host memory used -host_seconds 42.49 # Real time elapsed on the host -host_tick_rate 82214431 # Simulator tick rate (ticks/s) +host_inst_rate 1371456 # Simulator instruction rate (inst/s) +host_mem_usage 194364 # Number of bytes of host memory used +host_seconds 43.70 # Real time elapsed on the host +host_tick_rate 79947218 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 59929520 # Number of instructions simulated sim_seconds 1.746773 # Number of seconds simulated @@ -138,7 +138,7 @@ system.tsunami.ethernet.coalescedRxOrn <err: div-0> # av system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 4741dd710..6204251a5 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,4 +1,4 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 +Listening for console connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 5c4d8c01e..372fa2960 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:33:58 -M5 started Wed Aug 16 14:37:55 2006 +M5 compiled Aug 17 2006 23:41:21 +M5 started Thu Aug 17 23:41:25 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Exiting @ tick 3493545624 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 532e94849..1dc674569 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 868070 # Simulator instruction rate (inst/s) -host_mem_usage 194536 # Number of bytes of host memory used -host_seconds 72.68 # Real time elapsed on the host -host_tick_rate 48701109 # Simulator tick rate (ticks/s) +host_inst_rate 845052 # Simulator instruction rate (inst/s) +host_mem_usage 194484 # Number of bytes of host memory used +host_seconds 74.66 # Real time elapsed on the host +host_tick_rate 47409778 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 63088076 # Number of instructions simulated sim_seconds 1.769718 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 55bb62d6c..47e826dde 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:33:58 -M5 started Wed Aug 16 14:40:36 2006 +M5 compiled Aug 17 2006 23:41:21 +M5 started Thu Aug 17 23:51:44 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Exiting @ tick 3539435029 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 107769ef2..5e5ce79af 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 864969 # Simulator instruction rate (inst/s) -host_mem_usage 194104 # Number of bytes of host memory used -host_seconds 69.27 # Real time elapsed on the host -host_tick_rate 50617416 # Simulator tick rate (ticks/s) +host_inst_rate 859270 # Simulator instruction rate (inst/s) +host_mem_usage 194168 # Number of bytes of host memory used +host_seconds 69.73 # Real time elapsed on the host +host_tick_rate 50283954 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 59915182 # Number of instructions simulated sim_seconds 1.753109 # Number of seconds simulated @@ -138,7 +138,7 @@ system.tsunami.ethernet.coalescedRxOrn <err: div-0> # av system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 6204251a5..4741dd710 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,4 +1,4 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for console connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 7c772b20b..3ad24fa97 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:33:58 -M5 started Wed Aug 16 14:39:26 2006 +M5 compiled Aug 17 2006 23:41:21 +M5 started Thu Aug 17 23:41:25 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Exiting @ tick 3506218170 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index d322a7a40..4f9d886f0 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -84,6 +84,7 @@ bus_id=0 type=PhysicalMemory file= latency=1 +range=0:134217727 [trace] bufsize=0 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 32bafae43..8f236d9cc 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -8,7 +8,7 @@ output_file=cout [system.physmem] type=PhysicalMemory file= -// range not specified +range=[0,134217727] latency=1 [system] diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index e91773070..508b7b1e3 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1501109 # Simulator instruction rate (inst/s) -host_mem_usage 146480 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host -host_tick_rate 1499216 # Simulator tick rate (ticks/s) +host_inst_rate 1431500 # Simulator instruction rate (inst/s) +host_mem_usage 146556 # Number of bytes of host memory used +host_seconds 0.35 # Real time elapsed on the host +host_tick_rate 1429839 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 2fa2166aa..20413a23c 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:05:10 -M5 started Wed Aug 16 14:41:54 2006 +M5 compiled Aug 18 2006 00:06:43 +M5 started Fri Aug 18 00:12:49 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Exiting @ tick 499999 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index c4c381b93..0352c1b88 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -48,13 +48,13 @@ text_file=m5stats.txt [system] type=System -children=cpu physmem workload +children=cpu membus physmem mem_mode=atomic physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=mem +children=dcache icache l2cache toL2Bus workload clock=1 defer_registration=false function_trace=false @@ -63,26 +63,145 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.mem +mem=system.cpu.dcache system=system -workload=system.workload +workload=system.cpu.workload -[system.cpu.mem] -type=Bus -bus_id=0 +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 -[system.physmem] -type=PhysicalMemory -file= +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 -[system.workload] +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[system.cpu.workload] type=EioProcess chkpt= -file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz +file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz output=cout system=system +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 + [trace] bufsize=0 dump_on_exit=false diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index 882db9c06..ba6875a7b 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -8,7 +8,7 @@ output_file=cout [system.physmem] type=PhysicalMemory file= -// range not specified +range=[0,134217727] latency=1 [system] @@ -16,26 +16,65 @@ type=System physmem=system.physmem mem_mode=atomic -[system.workload] +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.workload] type=EioProcess -file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz +file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz chkpt= output=cout system=system -[system.cpu.mem] -type=Bus -bus_id=0 - [system.cpu] type=TimingSimpleCPU max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -mem=system.cpu.mem +mem=system.cpu.dcache system=system -workload=system.workload +workload=system.cpu.workload clock=1 defer_registration=false // width not specified @@ -43,6 +82,88 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + [trace] flags= start=0 @@ -81,6 +202,7 @@ print_data=true print_iregs=false print_fetchseq=false print_cpseq=false +print_reg_delta=false pc_symbol=true intel_format=false trace_system=client diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index 5f7766bac..1de3f9376 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,18 +1,213 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 781730 # Simulator instruction rate (inst/s) -host_mem_usage 147616 # Number of bytes of host memory used -host_seconds 0.64 # Real time elapsed on the host -host_tick_rate 1063244 # Simulator tick rate (ticks/s) +host_inst_rate 619761 # Simulator instruction rate (inst/s) +host_mem_usage 158236 # Number of bytes of host memory used +host_seconds 0.81 # Real time elapsed on the host +host_tick_rate 845354 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 680774 # Number of ticks simulated +sim_ticks 682354 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 124564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency -2174448991928520960 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 124315 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency -541437798990201749504 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001999 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 249 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 496 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001991 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 248 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 56744 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency -6113309131580347 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 56412 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency -2029618631684675072 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005851 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 332 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 278 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002450 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 311.061962 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 181308 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency -935400030330269184 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.demand_hits 180727 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency -543467417621886402560 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003204 # miss rate for demand accesses +system.cpu.dcache.demand_misses 581 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 774 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002134 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 387 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 181308 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency -935400030330269184 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 180727 # number of overall hits +system.cpu.dcache.overall_miss_latency -543467417621886402560 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003204 # miss rate for overall accesses +system.cpu.dcache.overall_misses 581 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 774 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002134 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 387 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 581 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 347.118131 # Cycle average of tags in use +system.cpu.dcache.total_refs 180727 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency -561967136127090496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency -226472755859217481728 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 806 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1239.694789 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency -561967136127090496 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency -226472755859217481728 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses +system.cpu.icache.demand_misses 403 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 806 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency -561967136127090496 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 499597 # number of overall hits +system.cpu.icache.overall_miss_latency -226472755859217481728 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses +system.cpu.icache.overall_misses 403 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 806 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 268.434590 # Cycle average of tags in use +system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 984 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 1.605691 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1580 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 984 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 790 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.802846 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 790 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 984 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 1.605691 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1580 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 984 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 790 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.802846 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 984 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 1.605691 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1580 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 984 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 790 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.802846 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 984 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 615.553879 # Cycle average of tags in use +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 0 # number of cpu cycles simulated system.cpu.num_insts 500000 # Number of instructions executed system.cpu.num_refs 182203 # Number of memory references -system.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr index 6f99fb456..4e444fa6b 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr @@ -1,11 +1,3 @@ -Traceback (most recent call last): - File "<string>", line 1, in ? - File "build/ALPHA_SE/python/m5/main.py", line 314, in main - execfile(sys.argv[0], scope) - File "tests/run.py", line 18, in ? - execfile(os.path.join(tests_root, 'configs', config + '.py')) - File "tests/configs/simple-timing.py", line 13, in ? - MyCache(size = '2MB')) - File "build/ALPHA_SE/python/m5/objects/BaseCPU.py", line 52, in addTwoLevelCacheHierarchy - self.l2cache.cpu_side = toL2Bus.port -NameError: global name 'toL2Bus' is not defined +warn: Entering event queue @ 0. Starting simulation... + +gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index bb29247b4..d400bd509 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -1,11 +1,14 @@ -M5 Simulator System +main dictionary has 1245 entries +49508 bytes wasted +>M5 Simulator System Copyright (c) 2001-2006 The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:05:10 -M5 started Wed Aug 16 14:41:54 2006 +M5 compiled Aug 18 2006 00:06:43 +M5 started Fri Aug 18 00:12:49 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing +Exiting @ tick 682354 because a thread reached the max instruction count diff --git a/tests/test-progs/hello/bin/alpha/linux/hello b/tests/test-progs/hello/bin/alpha/linux/hello Binary files differindex 59c0d195c..b8a6d1001 100755 --- a/tests/test-progs/hello/bin/alpha/linux/hello +++ b/tests/test-progs/hello/bin/alpha/linux/hello diff --git a/tests/test-progs/hello/bin/alpha/tru64/hello b/tests/test-progs/hello/bin/alpha/tru64/hello Binary files differnew file mode 100755 index 000000000..59c0d195c --- /dev/null +++ b/tests/test-progs/hello/bin/alpha/tru64/hello diff --git a/tests/test-progs/hello/src/hello.c b/tests/test-progs/hello/src/hello.c new file mode 100644 index 000000000..be6ec83c3 --- /dev/null +++ b/tests/test-progs/hello/src/hello.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + */ + +#include <stdio.h> + +int main() +{ + printf("Hello world!\n"); +} + diff --git a/util/m5/m5.c b/util/m5/m5.c index c9d7d5a47..193c0e329 100644 --- a/util/m5/m5.c +++ b/util/m5/m5.c @@ -32,6 +32,7 @@ #include <stdio.h> #include <stdlib.h> #include <string.h> +#include <unistd.h> #include "m5op.h" @@ -49,6 +50,7 @@ usage() " m5 dumpstats [delay [period]]\n" " m5 dumpresetstats [delay [period]]\n" " m5 checkpoint [delay [period]]\n" + " m5 readfile\n" "\n" "All times in nanoseconds!\n"); exit(1); @@ -184,5 +186,21 @@ main(int argc, char *argv[]) return 0; } + if (COMPARE("readfile")) { + char buf[256*1024]; + int offset = 0; + int len; + + if (argc != 2) + usage(); + + while ((len = m5_readfile(buf, sizeof(buf), offset)) > 0) { + write(STDOUT_FILENO, buf, len); + offset += len; + } + + return 0; + } + usage(); } |