diff options
| -rw-r--r-- | src/arch/x86/intmessage.hh | 31 | ||||
| -rw-r--r-- | src/dev/x86/intdev.hh | 3 |
2 files changed, 6 insertions, 28 deletions
diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh index 429b0f9f6..d2a5dfa1c 100644 --- a/src/arch/x86/intmessage.hh +++ b/src/arch/x86/intmessage.hh @@ -76,40 +76,17 @@ namespace X86ISA static const Addr TriggerIntOffset = 0; - static inline PacketPtr - prepIntRequest(const uint8_t id, Addr offset, Addr size) + template<class T> + PacketPtr + buildIntPacket(Addr addr, T payload) { RequestPtr req = std::make_shared<Request>( - x86InterruptAddress(id, offset), - size, Request::UNCACHEABLE, - Request::intMasterId); - + addr, sizeof(T), Request::UNCACHEABLE, Request::intMasterId); PacketPtr pkt = new Packet(req, MemCmd::WriteReq); pkt->allocate(); - return pkt; - } - - template<class T> - PacketPtr - buildIntRequest(const uint8_t id, T payload, Addr offset, Addr size) - { - PacketPtr pkt = prepIntRequest(id, offset, size); pkt->setRaw<T>(payload); return pkt; } - - static inline PacketPtr - buildIntRequest(const uint8_t id, TriggerIntMessage payload) - { - return buildIntRequest(id, payload, TriggerIntOffset, - sizeof(TriggerIntMessage)); - } - - static inline PacketPtr - buildIntResponse() - { - panic("buildIntResponse not implemented.\n"); - } } #endif diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh index 274873370..052928043 100644 --- a/src/dev/x86/intdev.hh +++ b/src/dev/x86/intdev.hh @@ -115,7 +115,8 @@ class IntMasterPort : public QueuedMasterPort sendMessage(X86ISA::ApicList apics, TriggerIntMessage message, bool timing) { for (auto id: apics) { - PacketPtr pkt = buildIntRequest(id, message); + Addr addr = x86InterruptAddress(id, TriggerIntOffset); + PacketPtr pkt = buildIntPacket(addr, message); if (timing) { schedTimingReq(pkt, curTick() + latency); // The target handles cleaning up the packet in timing mode. |