diff options
| -rw-r--r-- | src/mem/Bus.py | 2 | ||||
| -rw-r--r-- | src/sim/System.py | 9 |
2 files changed, 4 insertions, 7 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py index 447fc723e..45b1f1b0a 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -47,8 +47,6 @@ class BaseBus(MemObject): abstract = True slave = VectorSlavePort("vector port for connecting masters") master = VectorMasterPort("vector port for connecting slaves") - # Override the default clock - clock = '1GHz' header_cycles = Param.Cycles(1, "cycles of overhead per transaction") width = Param.Unsigned(8, "bus width (bytes)") block_size = Param.Unsigned(64, "The default block size if not set by " \ diff --git a/src/sim/System.py b/src/sim/System.py index 88afea873..92883b299 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -42,11 +42,10 @@ class System(MemObject): system_port = MasterPort("System port") # Override the clock from the ClockedObject which looks at the - # parent clock by default - clock = '1t' - # @todo Either make this value 0 and treat it as an error if it is - # not overridden, or choose a more sensible value in the range of - # 1GHz + # parent clock by default. The 1 GHz default system clock serves + # as a start for the modules that rely on the parent to provide + # the clock. + clock = '1GHz' @classmethod def export_method_cxx_predecls(cls, code): |