diff options
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 2 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.hh | 5 | ||||
| -rw-r--r-- | src/cpu/o3/lsq.hh | 6 | ||||
| -rw-r--r-- | src/cpu/o3/lsq_unit.hh | 10 |
4 files changed, 8 insertions, 15 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index ebe882a88..b6b8c045a 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -910,7 +910,7 @@ BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, } reqToVerify = new Request(*req); } - fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); + fault = cpu->read(req, sreqLow, sreqHigh, lqIdx); } else { // Commit will have to clean up whatever happened. Set this // instruction as executed. diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 09177d404..eed5811cb 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -678,10 +678,9 @@ class FullO3CPU : public BaseO3CPU /** CPU read function, forwards read to LSQ. */ Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, - uint8_t *data, int load_idx) + int load_idx) { - return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, - data, load_idx); + return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx); } /** CPU write function, forwards write to LSQ. */ diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index d726088ef..dcd676221 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -275,7 +275,7 @@ class LSQ { * index. */ Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, - uint8_t *data, int load_idx); + int load_idx); /** Executes a store operation, using the store specified at the store * index. @@ -332,11 +332,11 @@ class LSQ { template <class Impl> Fault LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, - uint8_t *data, int load_idx) + int load_idx) { ThreadID tid = req->threadId(); - return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx); + return thread[tid].read(req, sreqLow, sreqHigh, load_idx); } template <class Impl> diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 039bba8b6..b1b0aae3a 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -511,7 +511,7 @@ class LSQUnit { public: /** Executes the load at the given index. */ Fault read(Request *req, Request *sreqLow, Request *sreqHigh, - uint8_t *data, int load_idx); + int load_idx); /** Executes the store at the given index. */ Fault write(Request *req, Request *sreqLow, Request *sreqHigh, @@ -550,7 +550,7 @@ class LSQUnit { template <class Impl> Fault LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, - uint8_t *data, int load_idx) + int load_idx) { DynInstPtr load_inst = loadQueue[load_idx]; @@ -676,12 +676,6 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, // Get shift amount for offset into the store's data. int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr; - if (storeQueue[store_idx].isAllZeros) - memset(data, 0, req->getSize()); - else - memcpy(data, storeQueue[store_idx].data + shift_amt, - req->getSize()); - // Allocate memory if this is the first time a load is issued. if (!load_inst->memData) { load_inst->memData = new uint8_t[req->getSize()]; |