diff options
-rw-r--r-- | arch/mips/isa/decoder.isa | 19 | ||||
-rw-r--r-- | arch/mips/isa/formats.isa | 4 | ||||
-rw-r--r-- | arch/mips/isa/formats/branch.isa | 2 | ||||
-rw-r--r-- | arch/mips/isa/formats/util.isa | 26 |
4 files changed, 43 insertions, 8 deletions
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 6bb5bf4d8..62b0c1b7e 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -1,3 +1,5 @@ +// -*- mode:c++ -*- + //////////////////////////////////////////////////////////////////// // // The actual MIPS32 ISA decoder @@ -144,10 +146,13 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: decode REGIMM_HI { 0x0: decode REGIMM_LO { - format CondBranch { + format Branch { 0x0: bltz({{ cond = (Rs.sw < 0); }}); 0x1: bgez({{ cond = (Rs.sw >= 0); }}); + } + + format BranchLikely { //MIPS obsolete instructions 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); @@ -166,10 +171,12 @@ decode OPCODE_HI default Unknown::unknown() { } 0x2: decode REGIMM_LO { - format CondBranch { + format Branch { 0x0: bltzal({{ cond = (Rs.sw < 0); }}); 0x1: bgezal({{ cond = (Rs.sw >= 0); }}); + } + format BranchLikely { //MIPS obsolete instructions 0x2: bltzall({{ cond = (Rs.sw < 0); }}); 0x3: bgezall({{ cond = (Rs.sw >= 0); }}); @@ -188,7 +195,7 @@ decode OPCODE_HI default Unknown::unknown() { 0x3: jal(IsCall); } - format CondBranch { + format Branch { 0x4: beq({{ cond = (Rs.sw == 0); }}); 0x5: bne({{ cond = (Rs.sw != 0); }}); 0x6: blez({{ cond = (Rs.sw <= 0); }}); @@ -360,14 +367,14 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: decode ND { 0x0: decode TF { - format CondBranch { + format Branch { 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); } } 0x1: decode TF { - format CondBranch { + format BranchLikely { 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); } @@ -737,7 +744,7 @@ decode OPCODE_HI default Unknown::unknown() { } //MIPS obsolete instructions - format CondBranch { + format BranchLikely { 0x4: beql({{ cond = (Rs.sw == 0); }}); 0x5: bnel({{ cond = (Rs.sw != 0); }}); 0x6: blezl({{ cond = (Rs.sw <= 0); }}); diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa index 20ef49d82..61ac185d3 100644 --- a/arch/mips/isa/formats.isa +++ b/arch/mips/isa/formats.isa @@ -1,5 +1,7 @@ -//Include the basic format //Templates from this format are used later +##include "m5/arch/mips/isa/formats/util.isa" + +//Include the basic format ##include "m5/arch/mips/isa/formats/basic.isa" //Include the integerOp and integerOpCc format diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa index 45980349d..c7c97c2c8 100644 --- a/arch/mips/isa/formats/branch.isa +++ b/arch/mips/isa/formats/branch.isa @@ -1,4 +1,4 @@ -e// -*- mode:c++ -*- +// -*- mode:c++ -*- //////////////////////////////////////////////////////////////////// // diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa new file mode 100644 index 000000000..c6dae6783 --- /dev/null +++ b/arch/mips/isa/formats/util.isa @@ -0,0 +1,26 @@ +// -*- mode:c++ -*- + +let {{ +def UncondCtrlBase(name, Name, base_class, npc_expr, flags): + # Declare basic control transfer w/o link (i.e. link reg is R31) + nolink_code = 'NPC = %s;\n' % npc_expr + nolink_iop = InstObjParams(name, Name, base_class, + CodeBlock(nolink_code), flags) + header_output = BasicDeclare.subst(nolink_iop) + decoder_output = BasicConstructor.subst(nolink_iop) + exec_output = BasicExecute.subst(nolink_iop) + + # Generate declaration of '*AndLink' version, append to decls + link_code = 'Ra = NPC & ~3;\n' + nolink_code + link_iop = InstObjParams(name, Name + 'AndLink', base_class, + CodeBlock(link_code), flags) + header_output += BasicDeclare.subst(link_iop) + decoder_output += BasicConstructor.subst(link_iop) + exec_output += BasicExecute.subst(link_iop) + + # need to use link_iop for the decode template since it is expecting + # the shorter version of class_name (w/o "AndLink") + + return (header_output, decoder_output, + JumpOrBranchDecode.subst(nolink_iop), exec_output) +}}; |