diff options
| -rw-r--r-- | dev/pcidev.cc | 28 | ||||
| -rw-r--r-- | dev/tsunamireg.h | 7 |
2 files changed, 30 insertions, 5 deletions
diff --git a/dev/pcidev.cc b/dev/pcidev.cc index 13663b32c..342561750 100644 --- a/dev/pcidev.cc +++ b/dev/pcidev.cc @@ -47,6 +47,7 @@ #include "sim/builder.hh" #include "sim/param.hh" #include "sim/universe.hh" +#include "dev/tsunamireg.h" using namespace std; @@ -176,21 +177,38 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) if(config.data[offset] & 0x1) { *(uint32_t *)&config.data[offset] = (word_value & ~0x3) | (config.data[offset] & 0x3); - if (word_value) { + + if (word_value & ~0x1) { // It's never been set if (BARAddrs[barnum] == 0) - AddMapping(word_value, BARSize[barnum]-1, MMU); + AddMapping((word_value & ~0x1) + TSUNAMI_PCI0_IO, + BARSize[barnum]-1, MMU); else ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1, - word_value, BARSize[barnum]-1, MMU); - BARAddrs[barnum] = word_value; + (word_value & ~0x1) + TSUNAMI_PCI0_IO, + BARSize[barnum]-1, MMU); + BARAddrs[barnum] = (word_value & ~0x1) + TSUNAMI_PCI0_IO; } } else { // This is memory space, bottom four bits are read only *(uint32_t *)&config.data[offset] = (word_value & ~0xF) | (config.data[offset] & 0xF); - } + + if (word_value & ~0x3) { + // It's never been set + if (BARAddrs[barnum] == 0) + AddMapping((word_value & ~0x3) + TSUNAMI_PCI0_MEMORY, + BARSize[barnum]-1, MMU); + else + ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1, + (word_value & ~0x3) + + TSUNAMI_PCI0_MEMORY, + BARSize[barnum]-1, MMU); + BARAddrs[barnum] = (word_value & ~0x3) + + TSUNAMI_PCI0_MEMORY; + } + } } break; diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h index 7201edf94..c74279ecf 100644 --- a/dev/tsunamireg.h +++ b/dev/tsunamireg.h @@ -2,6 +2,8 @@ #ifndef __TSUNAMIREG_H__ #define __TSUNAMIREG_H__ +#define ALPHA_K0SEG_BASE 0xfffffc0000000000 + // CChip Registers #define TSDEV_CC_CSR 0x00 #define TSDEV_CC_MTR 0x01 @@ -99,5 +101,10 @@ #define RTC_CONTROL_REGISTERD 13 // control register D #define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1 +#define PCHIP_PCI0_MEMORY 0x10000000000 +#define PCHIP_PCI0_IO 0x101FC000000 +#define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY +#define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO + #endif // __TSUNAMIREG_H__ |