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-rw-r--r--SConscript9
-rw-r--r--arch/alpha/SConscript1
-rw-r--r--arch/alpha/isa/decoder.isa14
-rw-r--r--arch/alpha/isa/main.isa6
-rw-r--r--arch/mips/isa/bitfields.isa1
-rw-r--r--arch/mips/isa/decoder.isa403
-rw-r--r--base/loader/object_file.hh2
-rw-r--r--base/loader/symtab.hh2
-rw-r--r--cpu/base.hh2
-rw-r--r--cpu/static_inst.hh2
-rw-r--r--dev/ide_disk.cc2
-rw-r--r--dev/platform.hh2
-rw-r--r--dev/simple_disk.hh2
-rw-r--r--kern/linux/linux_threadinfo.hh2
-rw-r--r--kern/tru64/dump_mbuf.cc2
-rw-r--r--kern/tru64/mbuf.hh2
-rw-r--r--kern/tru64/tru64_events.cc2
-rw-r--r--kern/tru64/tru64_system.cc2
-rw-r--r--kern/tru64/tru64_system.hh2
-rw-r--r--sim/process.hh2
-rw-r--r--sim/pseudo_inst.cc (renamed from arch/alpha/pseudo_inst.cc)42
-rw-r--r--sim/pseudo_inst.hh (renamed from arch/alpha/pseudo_inst.hh)19
-rw-r--r--sim/syscall_emul.hh2
-rw-r--r--sim/vptr.hh (renamed from arch/alpha/vptr.hh)10
24 files changed, 337 insertions, 198 deletions
diff --git a/SConscript b/SConscript
index 589b2a17c..fc2e6ae0b 100644
--- a/SConscript
+++ b/SConscript
@@ -292,6 +292,7 @@ full_system_sources = Split('''
mem/functional/physical.cc
sim/system.cc
+ sim/pseudo_inst.cc
''')
# These are now included by the architecture specific SConscript
@@ -347,16 +348,16 @@ targetarch_files = Split('''
ecoff_machdep.h
ev5.hh
faults.hh
- isa_fullsys_traits.hh
- isa_traits.hh
- pseudo_inst.hh
stacktrace.hh
- vptr.hh
vtophys.hh
''')
+# pseudo_inst.hh
+# isa_traits.hh
# osfpal.hh
# byte_swap.hh
# alpha_common_syscall_emul.hh
+# vptr.hh
+# isa_fullsys_traits.hh
# Set up bridging headers to the architecture specific versions
for f in targetarch_files:
diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript
index 2c98125bc..8bf408c06 100644
--- a/arch/alpha/SConscript
+++ b/arch/alpha/SConscript
@@ -244,7 +244,6 @@ arch_full_system_sources = Split('''
arch/alpha/arguments.cc
arch/alpha/ev5.cc
arch/alpha/osfpal.cc
- arch/alpha/pseudo_inst.cc
arch/alpha/stacktrace.cc
arch/alpha/vtophys.cc
''')
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index 29124f191..aff8571e9 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -768,23 +768,23 @@ decode OPCODE default Unknown::unknown() {
AlphaPseudo::m5exit_old(xc->xcBase());
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
- AlphaPseudo::m5exit(xc->xcBase());
+ AlphaPseudo::m5exit(xc->xcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
0x40: resetstats({{
- AlphaPseudo::resetstats(xc->xcBase());
+ AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x41: dumpstats({{
- AlphaPseudo::dumpstats(xc->xcBase());
+ AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x42: dumpresetstats({{
- AlphaPseudo::dumpresetstats(xc->xcBase());
+ AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
- AlphaPseudo::m5checkpoint(xc->xcBase());
+ AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x50: m5readfile({{
- AlphaPseudo::readfile(xc->xcBase());
+ R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
}}, IsNonSpeculative);
0x51: m5break({{
AlphaPseudo::debugbreak(xc->xcBase());
@@ -793,7 +793,7 @@ decode OPCODE default Unknown::unknown() {
AlphaPseudo::switchcpu(xc->xcBase());
}}, IsNonSpeculative);
0x53: m5addsymbol({{
- AlphaPseudo::addsymbol(xc->xcBase());
+ AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
}
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index c082df8c8..ef4d83ce2 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -50,7 +50,7 @@ output exec {{
#include <math.h>
#if FULL_SYSTEM
-#include "arch/alpha/pseudo_inst.hh"
+#include "sim/pseudo_inst.hh"
#endif
#include "base/fenv.hh"
#include "config/ss_compatible_fp.hh"
@@ -160,7 +160,9 @@ def operands {{
'FPCR': (' ControlReg', 'uq', 'Fpcr', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
- 'R16': ('IntReg', 'uq', '16', None, 1)
+ 'R16': ('IntReg', 'uq', '16', None, 1),
+ 'R17': ('IntReg', 'uq', '17', None, 1),
+ 'R18': ('IntReg', 'uq', '18', None, 1)
}};
////////////////////////////////////////////////////////////////////
diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
index 94a8a6467..bead9c151 100644
--- a/arch/mips/isa/bitfields.isa
+++ b/arch/mips/isa/bitfields.isa
@@ -15,6 +15,7 @@ def bitfield RT_HI <20:19>;
def bitfield RT_LO <18:16>;
def bitfield RS <25:21>;
+def bitfield RS_MSB <25:25>;
def bitfield RS_HI <25:24>;
def bitfield RS_LO <23:21>;
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index acd00e70d..2ec7da805 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -66,7 +66,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x3: movn({{ if (Rt != 0) Rd = Rs; }});
}
- format Trap {
+ format WarnUnimpl {
0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
0x5: break({{ }});
0x7: sync({{ }});
@@ -131,12 +131,12 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x6: decode FUNCTION_LO {
format Trap {
- 0x0: tge({{ }});
- 0x1: tgeu({{ }});
- 0x2: tlt({{ }});
- 0x3: tltu({{ }});
- 0x4: teq({{ }});
- 0x6: tne({{ }});
+ 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
+ 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
+ 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
+ 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
+ 0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
+ 0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
}
}
}
@@ -155,12 +155,12 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode REGIMM_LO {
format Trap {
- 0x0: tgei({{ }});
- 0x1: tgeiu({{ }});
- 0x2: tlti({{ }});
- 0x3: tltiu({{ }});
- 0x4: teqi({{ }});
- 0x6: tnei({{ }});
+ 0x0: tgei({{ cond = (Rs.sw >= INTIMM; }});
+ 0x1: tgeiu({{ cond = (Rs.uw < INTIMM); }});
+ 0x2: tlti({{ cond = (Rs.sw < INTIMM); }});
+ 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
+ 0x4: teqi({{ cond = (Rs.sw == INTIMM); }});
+ 0x6: tnei({{ cond = (Rs.sw != INTIMM); }});
}
}
@@ -176,7 +176,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
0x3: decode REGIMM_LO {
- format Trap {
+ format WarnUnimpl {
0x7: synci({{ }});
}
}
@@ -229,7 +229,7 @@ decode OPCODE_HI default FailUnimpl::unknown() {
Rt = xc->miscRegs.cop0[reg_num];
}});
- 0xC: mtc0({{
+ 0x4: mtc0({{
//The contents of the coprocessor 0 register specified by the
//combination of rd and sel are loaded into general register
//rt. Note that not all coprocessor 0 registers support the
@@ -243,6 +243,25 @@ decode OPCODE_HI default FailUnimpl::unknown() {
xc->miscRegs.cop0[reg_num] = Rt;
}});
+ 0x8: mftr({{
+ //The contents of the coprocessor 0 register specified by the
+ //combination of rd and sel are loaded into general register
+ //rt. Note that not all coprocessor 0 registers support the
+ //sel field. In those instances, the sel field must be zero.
+
+ //MT Code Needed Here
+ }});
+
+ 0xC: mttr({{
+ //The contents of the coprocessor 0 register specified by the
+ //combination of rd and sel are loaded into general register
+ //rt. Note that not all coprocessor 0 registers support the
+ //sel field. In those instances, the sel field must be zero.
+
+ //MT Code Needed Here
+ }});
+
+
0xA: rdpgpr({{
//Accessing Previous Shadow Set Register Number
uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
@@ -252,23 +271,52 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}});
}
- 0xB: decode SC {
- format BasicOp {
- 0x0: di({{
- //Accessing Coprocessor 0 "Status" Register
- Rt.sw = xc->miscRegs.cop0[12];
- xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 0;
+ 0xB: decode RD {
+
+ 0x0: decode SC {
+ format BasicOp {
+ 0x0: dvpe({{
+ Rt.sw = xc->miscRegs.cop0.MVPControl;
+ xc->miscRegs.cop0.MVPControl[EVP] = 0;
}});
- 0x1: ei({{
- //Accessing Coprocessor 0 "Status" Register
- Rt.sw = xc->miscRegs.cop0[12];
- xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 1;
+ 0x1: evpe({{
+ Rt.sw = xc->miscRegs.cop0.MVPControl;
+ xc->miscRegs.cop0.MVPControl[EVP] = 1;
}});
+ }
+ }
+
+ 0x1: decode SC {
+ format BasicOp {
+ 0x0: dmt({{
+ Rt.sw = xc->miscRegs.cop0.VPEControl;
+ xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0;
+ }});
+
+ 0x1: emt({{
+ Rt.sw = xc->miscRegs.cop0.VPEControl;
+ xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1;
+ }});
+ }
+ }
+
+ 0xC: decode SC {
+ format BasicOp {
+ 0x0: di({{
+ Rt.sw = xc->miscRegs.cop0.Status;
+ xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0;
+ }});
+
+ 0x1: ei({{
+ Rt.sw = xc->miscRegs.cop0.Status;
+ xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1;
+ }});
+ }
+ }
}
- }
- 0xE: BasicOp::wrpgpr({{
+ 0xE: BasicOp::wrpgpr({{
//Accessing Previous Shadow Set Register Number
uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
uint64_t reg_num = Rd.uw;
@@ -334,61 +382,69 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x0: decode RS_HI {
0x0: decode RS_LO {
format FloatOp {
- 0x0: add_fmt({{ }});
- 0x1: sub_fmt({{ }});
- 0x2: mul_fmt({{ }});
- 0x3: div_fmt({{ }});
- 0x4: sqrt_fmt({{ }});
- 0x5: abs_fmt({{ }});
- 0x6: mov_fmt({{ }});
- 0x7: neg_fmt({{ }});
+ 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}});
+ 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}});
+ 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}});
+ 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}});
+ 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}});
+ 0x5: abss({{ Fd.sf = abs(Fs.sf);}});
+ 0x6: movs({{ Fd.sf = Fs.sf;}});
+ 0x7: negs({{ Fd.sf = -1 * Fs.sf;}});
}
}
0x1: decode RS_LO {
//only legal for 64 bit
format Float64Op {
- 0x0: round_l({{ }});
- 0x1: trunc_l({{ }});
- 0x2: ceil_l({{ }});
- 0x3: floor_l({{ }});
+ 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}});
+ 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}});
+ 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}});
+ 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}});
}
format FloatOp {
- 0x4: round_w({{ }});
- 0x5: trunc_w({{ }});
- 0x6: ceil_w({{ }});
- 0x7: floor_w({{ }});
+ 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}});
+ 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}});
+ 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}});
+ 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}});
}
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
- 0x0: movf_fmt({{ }});
- 0x1: movt_fmt({{ }});
+ 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }});
+ 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}});
}
}
format BasicOp {
- 0x2: movz({{ if (Rt == 0) Rd = Rs; }});
- 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+ 0x2: movzs({{ if (Rt == 0) Fd = Fs; }});
+ 0x3: movns({{ if (Rt != 0) Fd = Fs; }});
}
format Float64Op {
- 0x2: recip({{ }});
- 0x3: rsqrt{{ }});
+ 0x2: recips({{ Fd = 1 / Fs; }});
+ 0x3: rsqrts{{ Fd = 1 / sqrt(Fs); }});
}
}
0x4: decode RS_LO {
- 0x1: cvt_d({{ }});
- 0x4: cvt_w({{ }});
+ 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
+ }});
+
+ 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
+ }});
//only legal for 64 bit
format Float64Op {
- 0x5: cvt_l({{ }});
- 0x6: cvt_ps({{ }});
+ 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
+ }});
+
+ 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }});
}
}
}
@@ -397,62 +453,72 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode RS_HI {
0x0: decode RS_LO {
format FloatOp {
- 0x0: add_fmt({{ }});
- 0x1: sub_fmt({{ }});
- 0x2: mul_fmt({{ }});
- 0x3: div_fmt({{ }});
- 0x4: sqrt_fmt({{ }});
- 0x5: abs_fmt({{ }});
- 0x6: mov_fmt({{ }});
- 0x7: neg_fmt({{ }});
+ 0x0: addd({{ Fd.df = Fs.df + Ft.df;}});
+ 0x1: subd({{ Fd.df = Fs.df - Ft.df;}});
+ 0x2: muld({{ Fd.df = Fs.df * Ft.df;}});
+ 0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
+ 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
+ 0x5: absd({{ Fd.df = abs(Fs.df);}});
+ 0x6: movd({{ Fd.df = Fs.df;}});
+ 0x7: negd({{ Fd.df = -1 * Fs.df;}});
}
}
0x1: decode RS_LO {
//only legal for 64 bit
format FloatOp64 {
- 0x0: round_l({{ }});
- 0x1: trunc_l({{ }});
- 0x2: ceil_l({{ }});
- 0x3: floor_l({{ }});
+ 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
+ 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}});
+ 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}});
+ 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}});
}
format FloatOp {
- 0x4: round_w({{ }});
- 0x5: trunc_w({{ }});
- 0x6: ceil_w({{ }});
- 0x7: floor_w({{ }});
+ 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
+ 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }});
+ 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }});
+ 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }});
}
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp {
- 0x0: movf_fmt({{ }});
- 0x1: movt_fmt({{ }});
+ 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }});
+ 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }});
}
}
format BasicOp {
- 0x2: movz({{ if (Rt == 0) Rd = Rs; }});
- 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+ 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }});
+ 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }});
}
format FloatOp64 {
- 0x5: recip({{ }});
- 0x6: rsqrt{{ }});
+ 0x5: recipd({{ Fd.df = 1 / Fs.df}});
+ 0x6: rsqrtd{{ Fd.df = 1 / sqrt(Fs.df) }});
}
}
0x4: decode RS_LO {
format FloatOp {
- 0x0: cvt_s({{ }});
- 0x4: cvt_w({{ }});
+ 0x0: cvt_s_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE);
+ }});
+
+ 0x4: cvt_w_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE);
+ }});
}
//only legal for 64 bit
format FloatOp64 {
- 0x5: cvt_l({{ }});
+ 0x5: cvt_l_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
+ }});
}
}
}
@@ -460,8 +526,15 @@ decode OPCODE_HI default FailUnimpl::unknown() {
//Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
0x4: decode FUNCTION {
format FloatOp {
- 0x10: cvt_s({{ }});
- 0x10: cvt_d({{ }});
+ 0x10: cvt_s({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
+ }});
+
+ 0x10: cvt_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
+ }});
}
}
@@ -470,8 +543,15 @@ decode OPCODE_HI default FailUnimpl::unknown() {
//are enabled."
0x5: decode FUNCTION_HI {
format FloatOp {
- 0x10: cvt_s({{ }});
- 0x11: cvt_d({{ }});
+ 0x10: cvt_s_l({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG);
+ }});
+
+ 0x11: cvt_d_l({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG);
+ }});
}
}
@@ -481,36 +561,65 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x6: decode RS_HI {
0x0: decode RS_LO {
format FloatOp64 {
- 0x0: add_fmt({{ }});
- 0x1: sub_fmt({{ }});
- 0x2: mul_fmt({{ }});
- 0x5: abs_fmt({{ }});
- 0x6: mov_fmt({{ }});
- 0x7: neg_fmt({{ }});
+ 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs.df + Ft.df;
+ }});
+
+ 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs.df - Ft.df;
+ }});
+
+ 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs.df * Ft.df;
+ }});
+
+ 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = abs(Fs.df);
+ }});
+
+ 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs<31:0> | Ft<31:0>;
+ }});
+
+ 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = -1 * Fs.df;
+ }});
}
}
0x2: decode RS_LO {
0x1: decode MOVCF {
format FloatOp64 {
- 0x0: movf_fmt({{ }});
- 0x1: movt_fmt({{ }});
+ 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}})
+ 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}})
}
}
}
0x4: decode RS_LO {
- 0x0: FloatOp64::cvt_s_pu({{ }});
+ 0x0: FloatOp64::cvt_s_pu({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
+ }});
}
0x5: decode RS_LO {
format FloatOp64 {
- 0x0: cvt_s_pl({{ }});
- 0x4: pll_s_pl({{ }});
- 0x5: plu_s_pl({{ }});
- 0x6: pul_s_pl({{ }});
- 0x7: puu_s_pl({{ }});
+ 0x0: cvt_s_pl({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
+ }});
+ 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}});
+ 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}});
+ 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}});
+ 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}});
}
}
}
@@ -532,14 +641,14 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode ND {
0x0: decode TF {
- format Branch {
+ format WarnUnimpl {
0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
}
}
0x1: decode TF {
- format Branch {
+ format WarnUnimpl {
0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
}
@@ -554,46 +663,70 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x3: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
format Memory {
- 0x0: lwxc1({{ }});
- 0x1: ldxc1({{ }});
- 0x5: luxc1({{ }});
+ 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }});
+ 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }});
+ 0x5: luxc1({{ //Need to make EA<2:0> = 0
+ EA = Rs + Rt;
+ }},
+ {{ Ft<31:0> = Mem.df; }});
}
}
0x1: decode FUNCTION_LO {
format Memory {
- 0x0: swxc1({{ }});
- 0x1: sdxc1({{ }});
- 0x5: suxc1({{ }});
+ 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }});
+ 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}});
+ 0x5: suxc1({{ //Need to make EA<2:0> = 0
+ EA = Rs + Rt;
+ }},
+ {{ Mem.df = Ft<63:0>;}});
0x7: prefx({{ }});
}
}
format FloatOp {
- 0x3: alnv_ps({{ }});
+ 0x3: WarnUnimpl::alnv_ps({{ }});
- 0x4: decode FUNCTION_LO {
- 0x0: madd_s({{ }});
- 0x1: madd_d({{ }});
- 0x6: madd_ps({{ }});
- }
+ format BasicOp {
+ 0x4: decode FUNCTION_LO {
+ 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }});
+ 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }});
+ 0x6: madd_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (Fs.df * Fs.df) + Fr.df;
+ }});
+ }
- 0x5: decode FUNCTION_LO {
- 0x0: msub_s({{ }});
- 0x1: msub_d({{ }});
- 0x6: msub_ps({{ }});
- }
+ 0x5: decode FUNCTION_LO {
+ 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }});
+ 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }});
+ 0x6: msub_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (Fs.df * Fs.df) - Fr.df;
+ }});
+ }
- 0x6: decode FUNCTION_LO {
- 0x0: nmadd_s({{ }});
- 0x1: nmadd_d({{ }});
- 0x6: nmadd_ps({{ }});
- }
+ 0x6: decode FUNCTION_LO {
+ 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
+ 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }});
+ 0x6: nmadd_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
+ }});
+ }
- 0x7: decode FUNCTION_LO {
- 0x0: nmsub_s({{ }});
- 0x1: nmsub_d({{ }});
- 0x6: nmsub_ps({{ }});
+ 0x7: decode FUNCTION_LO {
+ 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
+ 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }});
+ 0x6: nmsub_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
+ }});
+ }
}
}
}
@@ -687,17 +820,27 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
}
+ 0x1: decode FUNCTION_LO {
+ format WarnUnimpl {
+ 0x0: fork({{ }});
+ 0x1: yield({{ }});
+ }
+ }
+
+
//Table A-10 MIPS32 BSHFL Encoding of sa Field
0x4: decode SA {
+
+ 0x02: WarnUnimpl::wsbh({{ }});
+
format BasicOp {
- 0x02: wsbh({{ }});
0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}});
0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}});
}
}
0x6: decode FUNCTION_LO {
- 0x7: BasicOp::rdhwr({{ }});
+ 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}});
}
}
};
@@ -726,24 +869,24 @@ decode OPCODE_HI default FailUnimpl::unknown() {
};
format WarnUnimpl {
- 0x4: reserved({{ }});
- 0x5: reserved({{ }});
0x7: cache({{ }});
};
};
0x6: decode OPCODE_LO default FailUnimpl::reserved() {
+ 0x0: WarnUnimpl::ll({{ }});
+
format Memory {
- 0x0: ll({{ }});
0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
};
};
0x7: decode OPCODE_LO default FailUnimpl::reserved() {
+ 0x0: WarnUnimpl::sc({{ }});
+
format Memory {
- 0x0: sc({{ }});
0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
};
diff --git a/base/loader/object_file.hh b/base/loader/object_file.hh
index 26d3ef3b0..3c8659e18 100644
--- a/base/loader/object_file.hh
+++ b/base/loader/object_file.hh
@@ -29,7 +29,7 @@
#ifndef __OBJECT_FILE_HH__
#define __OBJECT_FILE_HH__
-#include "targetarch/isa_traits.hh" // for Addr
+#include "arch/isa_traits.hh" // for Addr
class FunctionalMemory;
class SymbolTable;
diff --git a/base/loader/symtab.hh b/base/loader/symtab.hh
index 324fd8b45..ebcda1345 100644
--- a/base/loader/symtab.hh
+++ b/base/loader/symtab.hh
@@ -32,7 +32,7 @@
#include <iosfwd>
#include <map>
-#include "targetarch/isa_traits.hh" // for Addr
+#include "arch/isa_traits.hh" // for Addr
class Checkpoint;
class SymbolTable
diff --git a/cpu/base.hh b/cpu/base.hh
index 4a44ab804..2bd1210d8 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -36,7 +36,7 @@
#include "cpu/sampler/sampler.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
#if FULL_SYSTEM
class System;
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 85cfb5ae7..24997eadc 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -36,7 +36,7 @@
#include "base/refcnt.hh"
#include "encumbered/cpu/full/op_class.hh"
#include "sim/host.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
// forward declarations
struct AlphaSimpleImpl;
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc
index ea8f151c0..9d8bb8825 100644
--- a/dev/ide_disk.cc
+++ b/dev/ide_disk.cc
@@ -50,7 +50,7 @@
#include "sim/builder.hh"
#include "sim/sim_object.hh"
#include "sim/root.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
using namespace std;
diff --git a/dev/platform.hh b/dev/platform.hh
index ee9c72617..1ee645454 100644
--- a/dev/platform.hh
+++ b/dev/platform.hh
@@ -35,7 +35,7 @@
#define __DEV_PLATFORM_HH__
#include "sim/sim_object.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
class PciConfigAll;
class IntrControl;
diff --git a/dev/simple_disk.hh b/dev/simple_disk.hh
index 006155168..6560e15c2 100644
--- a/dev/simple_disk.hh
+++ b/dev/simple_disk.hh
@@ -34,7 +34,7 @@
#define __DEV_SIMPLE_DISK_HH__
#include "sim/sim_object.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
class DiskImage;
class PhysicalMemory;
diff --git a/kern/linux/linux_threadinfo.hh b/kern/linux/linux_threadinfo.hh
index 0c60b9f5c..9bab1dc49 100644
--- a/kern/linux/linux_threadinfo.hh
+++ b/kern/linux/linux_threadinfo.hh
@@ -31,7 +31,7 @@
#include "kern/linux/thread_info.hh"
#include "kern/linux/sched.hh"
-#include "targetarch/vptr.hh"
+#include "sim/vptr.hh"
namespace Linux {
diff --git a/kern/tru64/dump_mbuf.cc b/kern/tru64/dump_mbuf.cc
index 215930923..85cb4de96 100644
--- a/kern/tru64/dump_mbuf.cc
+++ b/kern/tru64/dump_mbuf.cc
@@ -35,7 +35,7 @@
#include "kern/tru64/mbuf.hh"
#include "sim/host.hh"
#include "targetarch/arguments.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "targetarch/vtophys.hh"
namespace tru64 {
diff --git a/kern/tru64/mbuf.hh b/kern/tru64/mbuf.hh
index f89074653..93424858f 100644
--- a/kern/tru64/mbuf.hh
+++ b/kern/tru64/mbuf.hh
@@ -30,7 +30,7 @@
#define __MBUF_HH__
#include "sim/host.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
namespace tru64 {
diff --git a/kern/tru64/tru64_events.cc b/kern/tru64/tru64_events.cc
index 2079922b7..d769aab0f 100644
--- a/kern/tru64/tru64_events.cc
+++ b/kern/tru64/tru64_events.cc
@@ -34,7 +34,7 @@
#include "kern/tru64/printf.hh"
#include "mem/functional/memory_control.hh"
#include "targetarch/arguments.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
//void SkipFuncEvent::process(ExecContext *xc);
diff --git a/kern/tru64/tru64_system.cc b/kern/tru64/tru64_system.cc
index f65293474..ebcdc1553 100644
--- a/kern/tru64/tru64_system.cc
+++ b/kern/tru64/tru64_system.cc
@@ -36,7 +36,7 @@
#include "mem/functional/memory_control.hh"
#include "mem/functional/physical.hh"
#include "sim/builder.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "targetarch/vtophys.hh"
using namespace std;
diff --git a/kern/tru64/tru64_system.hh b/kern/tru64/tru64_system.hh
index a9077e112..d4eb5a59a 100644
--- a/kern/tru64/tru64_system.hh
+++ b/kern/tru64/tru64_system.hh
@@ -30,7 +30,7 @@
#define __KERN_TRU64_TRU64_SYSTEM_HH__
#include "sim/system.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
class ExecContext;
diff --git a/sim/process.hh b/sim/process.hh
index 2116ef632..43fafd9d7 100644
--- a/sim/process.hh
+++ b/sim/process.hh
@@ -40,7 +40,7 @@
#include <vector>
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
#include "base/statistics.hh"
diff --git a/arch/alpha/pseudo_inst.cc b/sim/pseudo_inst.cc
index e105b3cc8..11ab55f53 100644
--- a/arch/alpha/pseudo_inst.cc
+++ b/sim/pseudo_inst.cc
@@ -33,8 +33,8 @@
#include <string>
-#include "arch/alpha/pseudo_inst.hh"
-#include "arch/alpha/vtophys.hh"
+#include "sim/pseudo_inst.hh"
+#include "targetarch/vtophys.hh"
#include "cpu/base.hh"
#include "cpu/sampler/sampler.hh"
#include "cpu/exec_context.hh"
@@ -46,7 +46,7 @@
#include "sim/stats.hh"
#include "sim/system.hh"
#include "sim/debug.hh"
-#include "targetarch/vptr.hh"
+#include "sim/vptr.hh"
using namespace std;
@@ -94,21 +94,18 @@ namespace AlphaPseudo
}
void
- m5exit(ExecContext *xc)
+ m5exit(ExecContext *xc, Tick delay)
{
- Tick delay = xc->regs.intRegFile[16];
Tick when = curTick + delay * Clock::Int::ns;
SimExit(when, "m5_exit instruction encountered");
}
void
- resetstats(ExecContext *xc)
+ resetstats(ExecContext *xc, Tick delay, Tick period)
{
if (!doStatisticsInsts)
return;
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
Tick when = curTick + delay * Clock::Int::ns;
Tick repeat = period * Clock::Int::ns;
@@ -118,13 +115,11 @@ namespace AlphaPseudo
}
void
- dumpstats(ExecContext *xc)
+ dumpstats(ExecContext *xc, Tick delay, Tick period)
{
if (!doStatisticsInsts)
return;
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
Tick when = curTick + delay * Clock::Int::ns;
Tick repeat = period * Clock::Int::ns;
@@ -134,11 +129,10 @@ namespace AlphaPseudo
}
void
- addsymbol(ExecContext *xc)
+ addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr)
{
- Addr addr = xc->regs.intRegFile[16];
char symb[100];
- CopyString(xc, symb, xc->regs.intRegFile[17], 100);
+ CopyString(xc, symb, symbolAddr, 100);
std::string symbol(symb);
DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
@@ -147,13 +141,11 @@ namespace AlphaPseudo
}
void
- dumpresetstats(ExecContext *xc)
+ dumpresetstats(ExecContext *xc, Tick delay, Tick period)
{
if (!doStatisticsInsts)
return;
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
Tick when = curTick + delay * Clock::Int::ns;
Tick repeat = period * Clock::Int::ns;
@@ -163,13 +155,11 @@ namespace AlphaPseudo
}
void
- m5checkpoint(ExecContext *xc)
+ m5checkpoint(ExecContext *xc, Tick delay, Tick period)
{
if (!doCheckpointInsts)
return;
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
Tick when = curTick + delay * Clock::Int::ns;
Tick repeat = period * Clock::Int::ns;
@@ -177,18 +167,14 @@ namespace AlphaPseudo
Checkpoint::setup(when, repeat);
}
- void
- readfile(ExecContext *xc)
+ uint64_t
+ readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset)
{
const string &file = xc->cpu->system->params->readfile;
if (file.empty()) {
- xc->regs.intRegFile[0] = ULL(0);
- return;
+ return ULL(0);
}
- Addr vaddr = xc->regs.intRegFile[16];
- uint64_t len = xc->regs.intRegFile[17];
- uint64_t offset = xc->regs.intRegFile[18];
uint64_t result = 0;
int fd = ::open(file.c_str(), O_RDONLY, 0);
@@ -213,7 +199,7 @@ namespace AlphaPseudo
close(fd);
CopyIn(xc, vaddr, buf, result);
delete [] buf;
- xc->regs.intRegFile[0] = result;
+ return result;
}
class Context : public ParamContext
diff --git a/arch/alpha/pseudo_inst.hh b/sim/pseudo_inst.hh
index 0e7462a56..3857f2050 100644
--- a/arch/alpha/pseudo_inst.hh
+++ b/sim/pseudo_inst.hh
@@ -28,6 +28,11 @@
class ExecContext;
+//We need the "Tick" data type from here
+#include "sim/host.hh"
+//We need the "Addr" data type from here
+#include "arch/isa_traits.hh"
+
namespace AlphaPseudo
{
/**
@@ -41,14 +46,14 @@ namespace AlphaPseudo
void quiesce(ExecContext *xc);
void ivlb(ExecContext *xc);
void ivle(ExecContext *xc);
- void m5exit(ExecContext *xc);
+ void m5exit(ExecContext *xc, Tick delay);
void m5exit_old(ExecContext *xc);
- void resetstats(ExecContext *xc);
- void dumpstats(ExecContext *xc);
- void dumpresetstats(ExecContext *xc);
- void m5checkpoint(ExecContext *xc);
- void readfile(ExecContext *xc);
+ void resetstats(ExecContext *xc, Tick delay, Tick period);
+ void dumpstats(ExecContext *xc, Tick delay, Tick period);
+ void dumpresetstats(ExecContext *xc, Tick delay, Tick period);
+ void m5checkpoint(ExecContext *xc, Tick delay, Tick period);
+ uint64_t readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset);
void debugbreak(ExecContext *xc);
void switchcpu(ExecContext *xc);
- void addsymbol(ExecContext *xc);
+ void addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr);
}
diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh
index 8f5402413..d8029ddb0 100644
--- a/sim/syscall_emul.hh
+++ b/sim/syscall_emul.hh
@@ -47,7 +47,7 @@
#include "base/intmath.hh" // for RoundUp
#include "mem/functional/functional.hh"
-#include "targetarch/isa_traits.hh" // for Addr
+#include "arch/isa_traits.hh" // for Addr
#include "base/trace.hh"
#include "cpu/exec_context.hh"
diff --git a/arch/alpha/vptr.hh b/sim/vptr.hh
index d1bda4061..7ec43602d 100644
--- a/arch/alpha/vptr.hh
+++ b/sim/vptr.hh
@@ -29,7 +29,8 @@
#ifndef __ARCH_ALPHA_VPTR_HH__
#define __ARCH_ALPHA_VPTR_HH__
-#include "arch/alpha/vtophys.hh"
+#include "targetarch/vtophys.hh"
+#include "arch/isa_traits.hh"
class ExecContext;
@@ -69,15 +70,16 @@ class VPtr
const VPtr<T> &operator+=(int offset)
{
ptr += offset;
- assert((ptr & (AlphaISA::PageBytes - 1)) + sizeof(T)
- < AlphaISA::PageBytes);
+ assert((ptr & (TheISA::PageBytes - 1)) + sizeof(T)
+ < TheISA::PageBytes);
return *this;
}
const VPtr<T> &operator=(Addr p)
{
- assert((p & (AlphaISA::PageBytes)) + sizeof(T) < AlphaISA::PageBytes);
+ assert((p & (TheISA::PageBytes - 1)) + sizeof(T)
+ < TheISA::PageBytes);
ptr = p;
return *this;
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-03 21:02:43 +0000