diff options
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 12 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index a9acc21af..4f1960b95 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -177,9 +177,9 @@ let {{ default: uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2); if (isRead) { - return new Mrc14(machInst, rt, (IntRegIndex)miscReg, iss); + return new Mrc14(machInst, rt, miscReg, iss); } else { - return new Mcr14(machInst, (IntRegIndex)miscReg, rt, iss); + return new Mcr14(machInst, miscReg, rt, iss); } } } diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 3aeee0456..f1c6acff3 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -875,11 +875,11 @@ let {{ Dest = MiscOp1; ''' - mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp", + mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp", { "code": mrc14code, "predicate_test": predicateTest }, []) - header_output += RegRegImmOpDeclare.subst(mrc14Iop) - decoder_output += RegRegImmOpConstructor.subst(mrc14Iop) + header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop) + decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop) exec_output += PredOpExecute.subst(mrc14Iop) @@ -899,12 +899,12 @@ let {{ } MiscDest = Op1; ''' - mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp", + mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp", { "code": mcr14code, "predicate_test": predicateTest }, ["IsSerializeAfter","IsNonSpeculative"]) - header_output += RegRegImmOpDeclare.subst(mcr14Iop) - decoder_output += RegRegImmOpConstructor.subst(mcr14Iop) + header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop) + decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop) exec_output += PredOpExecute.subst(mcr14Iop) mrc15code = ''' |