diff options
| -rw-r--r-- | src/arch/x86/cpuid.cc | 10 | ||||
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 12 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py | 37 | ||||
| -rw-r--r-- | src/arch/x86/isa/microops/ldstop.isa | 5 |
4 files changed, 60 insertions, 4 deletions
diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc index c78b72030..867087eb0 100644 --- a/src/arch/x86/cpuid.cc +++ b/src/arch/x86/cpuid.cc @@ -37,6 +37,12 @@ namespace X86ISA { enum StandardCpuidFunction { VendorAndLargestStdFunc, FamilyModelStepping, + CacheAndTLB, + SerialNumber, + CacheParams, + MonitorMwait, + ThermalPowerMgmt, + ExtendedFeatures, NumStandardCpuidFuncs }; @@ -158,6 +164,10 @@ namespace X86ISA { result = CpuidResult(0x00020f51, 0x00000805, 0xe7dbfbff, 0x04000209); break; + case ExtendedFeatures: + result = CpuidResult(0x00000000, 0x01800000, + 0x00000000, 0x00000000); + break; default: warn("x86 cpuid family 0x0000: unimplemented function %u", funcNum); diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index f0698ce18..aa60e4c48 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -800,8 +800,16 @@ 0x3: Inst::STMXCSR(Md); 0x4: xsave(); 0x5: xrstor(); - 0x6: Inst::UD2(); - 0x7: clflush(); + 0x6: decode LEGACY_DECODEVAL { + 0x0: Inst::UD2(); + 0x1: Inst::CLWB(Mb); + default: Inst::UD2(); + } + 0x7: decode LEGACY_DECODEVAL { + 0x0: Inst::CLFLUSH(Mb); + 0x1: Inst::CLFLUSHOPT(Mb); + default: Inst::CLFLUSH(Mb); + } } } 0x7: Inst::IMUL(Gv,Ev); diff --git a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py index d42c68795..4dc0b308e 100644 --- a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py +++ b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py @@ -58,6 +58,41 @@ def macroop PREFETCH_T0_P ld t0, seg, riprel, disp, dataSize=1, prefetch=True }; +def macroop CLFLUSH_M +{ + clflushopt t0, seg, sib, disp, dataSize=1 + mfence +}; + +def macroop CLFLUSH_P +{ + rdip t7 + clflushopt t0, seg, riprel, disp, dataSize=1 + mfence +}; + +def macroop CLFLUSHOPT_M +{ + clflushopt t0, seg, sib, disp, dataSize=1 +}; + +def macroop CLFLUSHOPT_P +{ + rdip t7 + clflushopt t0, seg, riprel, disp, dataSize=1 +}; + +def macroop CLWB_M +{ + clwb t1, seg, sib, disp, dataSize=1 +}; + +def macroop CLWB_P +{ + rdip t7 + clwb t1, seg, riprel, disp, dataSize=1 +}; + ''' #let {{ @@ -71,6 +106,4 @@ def macroop PREFETCH_T0_P # "GenFault ${new UnimpInstFault}" # class PREFETCHW(Inst): # "GenFault ${new UnimpInstFault}" -# class CLFLUSH(Inst): -# "GenFault ${new UnimpInstFault}" #}}; diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index a3d9c5a70..83e24e154 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -634,6 +634,11 @@ let {{ ''') defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") + defineMicroStoreOp('Clflushopt', 'Mem = 0;', + mem_flags="Request::CLEAN | Request::INVALIDATE" + + " | Request::DST_POC") + defineMicroStoreOp('Clwb', 'Mem = 0;', + mem_flags="Request::CLEAN | Request::DST_POC") def defineMicroStoreSplitOp(mnemonic, code, completeCode="", mem_flags="0"): |