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-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out3092
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini187
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out178
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt230
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out3092
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr7
-rw-r--r--tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout33
7 files changed, 6819 insertions, 0 deletions
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
new file mode 100644
index 000000000..6bbb02cf0
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
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diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
new file mode 100644
index 000000000..dfb81664a
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -0,0 +1,187 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
new file mode 100644
index 000000000..e5ed0b288
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
@@ -0,0 +1,178 @@
+[root]
+type=Root
+dummy=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+input=/dist/m5/cpu2000/data/mcf/lgred/input/mcf.in
+output=cout
+env=
+cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
new file mode 100644
index 000000000..b11288b2d
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
@@ -0,0 +1,230 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 446147 # Simulator instruction rate (inst/s)
+host_mem_usage 154148 # Number of bytes of host memory used
+host_seconds 3854.32 # Real time elapsed on the host
+host_tick_rate 13681801 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1719594534 # Number of instructions simulated
+sim_seconds 0.052734 # Number of seconds simulated
+sim_ticks 52734070003 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3420.154300 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2420.154300 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 44693656366 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 31625925366 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency 3631.818182 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2631.818182 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 39950 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 28950 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3255.499606 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2255.499606 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 5557128061 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 3850131061 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 51.440428 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3401.130933 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 50250784427 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 35476056427 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3401.130933 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 760003458 # number of overall hits
+system.cpu.dcache.overall_miss_latency 50250784427 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 14774728 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 35476056427 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 14770643 # number of replacements
+system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4094.978951 # Cycle average of tags in use
+system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 35437000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 4191356 # number of writebacks
+system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4032.295228 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3032.295228 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 3633098 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 2732098 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1908538.994451 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4032.295228 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 3633098 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
+system.cpu.icache.demand_misses 901 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 2732098 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4032.295228 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1719593634 # number of overall hits
+system.cpu.icache.overall_miss_latency 3633098 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
+system.cpu.icache.overall_misses 901 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 2732098 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 31 # number of replacements
+system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 750.163929 # Cycle average of tags in use
+system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3097.556051 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1926.730191 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 19151739918 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 11912693395 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 4164131 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 0.006496 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 27225 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 0.006496 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 27225 # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 2.063273 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3097.556051 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 19151739918 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 11912693395 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3083.976361 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 12756915 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 19151739918 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 6210080 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 11912693395 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 6150087 # number of replacements
+system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 27594.660688 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 12316534000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1069081 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 52734070003 # number of cpu cycles simulated
+system.cpu.num_insts 1719594534 # Number of instructions executed
+system.cpu.num_refs 774793634 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 632 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
new file mode 100644
index 000000000..6bbb02cf0
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out
@@ -0,0 +1,3092 @@
+()
+1642
+***
+1759
+()
+1641
+***
+1691
+()
+1640
+()
+1639
+()
+1638
+()
+1637
+()
+1636
+()
+1635
+()
+1634
+()
+1633
+()
+1632
+()
+1631
+()
+1630
+()
+1629
+()
+1628
+()
+1627
+()
+1626
+()
+1625
+***
+1784
+()
+1624
+()
+1623
+()
+1622
+***
+1688
+()
+1621
+()
+1618
+()
+1617
+***
+1796
+()
+1616
+()
+1615
+***
+1668
+()
+1614
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diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr
new file mode 100644
index 000000000..9c09fd847
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr
@@ -0,0 +1,7 @@
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0xa2000 length 0x10.
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x0 length 0x0.
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
+warn: Ignoring request to flush register windows.
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
new file mode 100644
index 000000000..7d97093d4
--- /dev/null
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
@@ -0,0 +1,33 @@
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 1800
+active arcs : 8190
+simplex iterations : 6837
+flow value : 12860044181
+new implicit arcs : 300000
+active arcs : 308190
+simplex iterations : 11843
+flow value : 9360043604
+new implicit arcs : 22787
+active arcs : 330977
+simplex iterations : 11931
+flow value : 9360043512
+checksum : 798014
+optimal
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Mar 29 2007 15:41:48
+M5 started Thu Mar 29 15:42:11 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+Exiting @ tick 52734070003 because target called exit()