diff options
| -rw-r--r-- | configs/common/FSConfig.py | 4 | ||||
| -rw-r--r-- | src/dev/arm/RealView.py | 30 |
2 files changed, 28 insertions, 6 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index bf09c4804..fa383bb93 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -365,7 +365,9 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, self.realview.attachIO(self.iobus) elif ruby: self._dma_ports = [ ] - self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports) + self._mem_ports = [ ] + self.realview.attachOnChipIO(self.iobus, + dma_ports=self._dma_ports, mem_ports=self._mem_ports) self.realview.attachIO(self.iobus, dma_ports=self._dma_ports) else: self.realview.attachOnChipIO(self.membus, self.bridge) diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 1ff098e79..d24dbe2ad 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -550,9 +550,14 @@ class RealView(Platform): _off_chip_ranges = [] + def _attach_memory(self, mem, bus, mem_ports=None): + if hasattr(mem, "port"): + if mem_ports is None: + mem.port = bus.master + else: + mem_ports.append(mem.port) + def _attach_device(self, device, bus, dma_ports=None): - if hasattr(device, "port"): - device.port = bus.master if hasattr(device, "pio"): device.pio = bus.master if hasattr(device, "dma"): @@ -565,6 +570,10 @@ class RealView(Platform): for d in devices: self._attach_device(d, *args, **kwargs) + def _attach_mem(self, memories, *args, **kwargs): + for mem in memories: + self._attach_memory(mem, *args, **kwargs) + def _attach_clk(self, devices, clkdomain): for d in devices: if hasattr(d, "clk_domain"): @@ -582,8 +591,9 @@ class RealView(Platform): def offChipIOClkDomain(self, clkdomain): self._attach_clk(self._off_chip_devices(), clkdomain) - def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): - self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) + def attachOnChipIO(self, bus, bridge=None, dma_ports=None, mem_ports=None): + self._attach_mem(self._on_chip_memory(), bus, mem_ports) + self._attach_io(self._on_chip_devices(), bus, dma_ports) if bridge: bridge.ranges = self._off_chip_ranges @@ -643,7 +653,6 @@ class VExpress_EMM(RealView): def _on_chip_devices(self): devices = [ self.gic, self.vgic, - self.bootmem, self.local_cpu_timer ] if hasattr(self, "gicv2m"): @@ -651,6 +660,12 @@ class VExpress_EMM(RealView): devices.append(self.hdlcd) return devices + def _on_chip_memory(self): + memories = [ + self.bootmem, + ] + return memories + ### Off-chip devices ### uart = Pl011(pio_addr=0x1c090000, int_num=37) pci_host = GenericPciHost( @@ -882,8 +897,13 @@ Interrupts: def _on_chip_devices(self): return [ self.generic_timer, + ] + + def _on_chip_memory(self): + memories = [ self.bootmem, ] + return memories ### Off-chip devices ### clock24MHz = SrcClockDomain(clock="24MHz", |