diff options
| -rw-r--r-- | src/arch/sparc/isa_traits.hh | 12 | ||||
| -rw-r--r-- | src/arch/sparc/tlb.hh | 5 |
2 files changed, 5 insertions, 12 deletions
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 5bcfc04a4..f42cdb9f5 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -44,23 +44,11 @@ namespace SparcISA // This makes sure the big endian versions of certain functions are used. using namespace BigEndianGuest; -// real address virtual mapping -// sort of like alpha super page, but less frequently used -const Addr SegKPMEnd = ULL(0xfffffffc00000000); -const Addr SegKPMBase = ULL(0xfffffac000000000); - const Addr PageShift = 13; const Addr PageBytes = ULL(1) << PageShift; StaticInstPtr decodeInst(ExtMachInst); -/////////// TLB Stuff //////////// -const Addr StartVAddrHole = ULL(0x0000800000000000); -const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); -const Addr VAddrAMask = ULL(0xFFFFFFFF); -const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); -const Addr BytesInPageMask = ULL(0x1FFF); - // Memory accesses cannot be unaligned const bool HasUnalignedMemAcc = false; diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index e5e6753be..0d173da32 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -44,6 +44,11 @@ class Packet; namespace SparcISA { +const Addr StartVAddrHole = ULL(0x0000800000000000); +const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); +const Addr VAddrAMask = ULL(0xFFFFFFFF); +const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); + class TLB : public BaseTLB { // These faults need to be able to populate the tlb in SE mode. |