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-rw-r--r--src/arch/arm/tlb.cc12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 3fc317048..1f6910262 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1197,11 +1197,15 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
DPRINTF(TLBVerbose, "TLB variables changed!\n");
cpsr = tc->readMiscReg(MISCREG_CPSR);
+
// Dependencies: SCR/SCR_EL3, CPSR
- isSecure = inSecureState(tc);
- isSecure &= (tranType & HypMode) == 0;
- isSecure &= (tranType & S1S2NsTran) == 0;
- aarch64 = !cpsr.width;
+ isSecure = inSecureState(tc) &&
+ !(tranType & HypMode) && !(tranType & S1S2NsTran);
+
+ const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode;
+ aarch64 = opModeIs64(op_mode) ||
+ (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1));
+
if (aarch64) { // AArch64
aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el;
switch (aarch64EL) {